596 lines
38 KiB
C
596 lines
38 KiB
C
/*!
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\file gd32f3x0_usart.h
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\brief definitions for the USART
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\version 2017-06-06, V1.0.0, firmware for GD32F3x0
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\version 2019-06-01, V2.0.0, firmware for GD32F3x0
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F3X0_USART_H
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#define GD32F3X0_USART_H
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#include "gd32f3x0.h"
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/* USARTx(x=0,1) definitions */
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#define USART0 (USART_BASE + 0x0000F400U)
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#define USART1 USART_BASE
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/* registers definitions */
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#define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */
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#define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */
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#define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */
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#define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate register */
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#define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART guard time and prescaler register */
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#define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */
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#define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */
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#define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */
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#define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART status clear register */
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#define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */
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#define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */
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#define USART_RFCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART receive FIFO control and status register */
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/* bits definitions */
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/* USARTx_CTL0 */
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#define USART_CTL0_UEN BIT(0) /*!< USART enable */
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#define USART_CTL0_UESM BIT(1) /*!< USART enable in deep-sleep mode */
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#define USART_CTL0_REN BIT(2) /*!< receiver enable */
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#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */
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#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */
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#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */
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#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */
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#define USART_CTL0_TBEIE BIT(7) /*!< transmitter register empty interrupt enable */
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#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */
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#define USART_CTL0_PM BIT(9) /*!< parity mode */
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#define USART_CTL0_PCEN BIT(10) /*!< parity control enable */
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#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
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#define USART_CTL0_WL BIT(12) /*!< word length */
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#define USART_CTL0_MEN BIT(13) /*!< mute mode enable */
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#define USART_CTL0_AMIE BIT(14) /*!< address match interrupt enable */
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#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */
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#define USART_CTL0_DED BITS(16,20) /*!< driver enable deassertion time */
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#define USART_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */
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#define USART_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */
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#define USART_CTL0_EBIE BIT(27) /*!< end of block interrupt enable */
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/* USARTx_CTL1 */
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#define USART_CTL1_ADDM BIT(4) /*!< address detection mode */
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#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
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#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */
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#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */
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#define USART_CTL1_CPH BIT(9) /*!< clock phase */
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#define USART_CTL1_CPL BIT(10) /*!< clock polarity */
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#define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */
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#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */
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#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */
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#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */
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#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */
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#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */
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#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */
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#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */
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#define USART_CTL1_ABDEN BIT(20) /*!< auto baud rate enable */
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#define USART_CTL1_ABDM BITS(21,22) /*!< auto baud rate mode */
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#define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */
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#define USART_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */
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/* USARTx_CTL2 */
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#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */
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#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */
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#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
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#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */
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#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
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#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */
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#define USART_CTL2_DENR BIT(6) /*!< DMA enable for reception */
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#define USART_CTL2_DENT BIT(7) /*!< DMA enable for transmission */
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#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */
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#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */
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#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */
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#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */
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#define USART_CTL2_OVRD BIT(12) /*!< overrun disable */
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#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */
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#define USART_CTL2_DEM BIT(14) /*!< driver enable mode */
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#define USART_CTL2_DEP BIT(15) /*!< driver enable polarity mode */
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#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */
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#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */
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#define USART_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */
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/* USARTx_BAUD */
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#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */
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#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */
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/* USARTx_GP */
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#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
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#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
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/* USARTx_RT */
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#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */
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#define USART_RT_BL BITS(24,31) /*!< block length */
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/* USARTx_CMD */
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#define USART_CMD_ABDCMD BIT(0) /*!< auto baudrate detection command */
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#define USART_CMD_SBKCMD BIT(1) /*!< send break command */
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#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */
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#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */
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#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */
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/* USARTx_STAT */
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#define USART_STAT_PERR BIT(0) /*!< parity error flag */
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#define USART_STAT_FERR BIT(1) /*!< frame error flag */
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#define USART_STAT_NERR BIT(2) /*!< noise error flag */
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#define USART_STAT_ORERR BIT(3) /*!< overrun error */
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#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */
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#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */
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#define USART_STAT_TC BIT(6) /*!< transmission completed */
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#define USART_STAT_TBE BIT(7) /*!< transmit data register empty */
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#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */
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#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */
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#define USART_STAT_CTS BIT(10) /*!< CTS level */
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#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */
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#define USART_STAT_EBF BIT(12) /*!< end of block flag */
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#define USART_STAT_ABDE BIT(14) /*!< auto baudrate detection error */
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#define USART_STAT_ABDF BIT(15) /*!< auto baudrate detection flag */
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#define USART_STAT_BSY BIT(16) /*!< busy flag */
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#define USART_STAT_AMF BIT(17) /*!< address match flag */
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#define USART_STAT_SBF BIT(18) /*!< send break flag */
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#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */
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#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */
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#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */
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#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */
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/* USARTx_INTC */
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#define USART_INTC_PEC BIT(0) /*!< parity error clear */
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#define USART_INTC_FEC BIT(1) /*!< frame error flag clear */
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#define USART_INTC_NEC BIT(2) /*!< noise detected clear */
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#define USART_INTC_OREC BIT(3) /*!< overrun error clear */
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#define USART_INTC_IDLEC BIT(4) /*!< idle line detected clear */
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#define USART_INTC_TCC BIT(6) /*!< transmission complete clear */
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#define USART_INTC_LBDC BIT(8) /*!< LIN break detected clear */
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#define USART_INTC_CTSC BIT(9) /*!< CTS change clear */
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#define USART_INTC_RTC BIT(11) /*!< receiver timeout clear */
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#define USART_INTC_EBC BIT(12) /*!< end of timeout clear */
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#define USART_INTC_AMC BIT(17) /*!< address match clear */
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#define USART_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */
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/* USARTx_RDATA */
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#define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */
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/* USARTx_TDATA */
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#define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */
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/* USARTx_RFCS */
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#define USART_RFCS_ELNACK BIT(0) /*!< early NACK */
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#define USART_RFCS_RFEN BIT(8) /*!< receive FIFO enable */
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#define USART_RFCS_RFFIE BIT(9) /*!< receive FIFO full interrupt enable */
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#define USART_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */
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#define USART_RFCS_RFF BIT(11) /*!< receive FIFO full flag */
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#define USART_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */
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#define USART_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */
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/* constants definitions */
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/* define the USART bit position and its register index offset */
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#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
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#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
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#define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
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#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
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| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
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#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
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#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
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/* register offset */
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#define USART_CTL0_REG_OFFSET (0x00000000U) /*!< CTL0 register offset */
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#define USART_CTL1_REG_OFFSET (0x00000004U) /*!< CTL1 register offset */
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#define USART_CTL2_REG_OFFSET (0x00000008U) /*!< CTL2 register offset */
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#define USART_STAT_REG_OFFSET (0x0000001CU) /*!< STAT register offset */
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#define USART_RFCS_REG_OFFSET (0x000000D0U) /*!< RFCS register offset */
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/* USART flags */
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typedef enum{
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/* flags in STAT register */
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USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */
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USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */
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USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode flag */
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USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */
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USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */
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USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */
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USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */
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USART_FLAG_ABD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 15U), /*!< auto baudrate detection flag */
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USART_FLAG_ABDE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 14U), /*!< auto baudrate detection error */
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USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */
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USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */
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USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */
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USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
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USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
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USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */
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USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */
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USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */
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USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */
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USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */
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USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */
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USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */
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USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */
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/* flags in RFCS register */
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USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */
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USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */
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}usart_flag_enum;
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/* USART interrupt flags */
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typedef enum
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{
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/* interrupt flags in CTL0 register */
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USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt flag */
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USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt flag */
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USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt flag */
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USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt flag */
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USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt flag */
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USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt flag */
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USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt flag */
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USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< overrun error interrupt flag */
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USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt flag */
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/* interrupt flags in CTL1 register */
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USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt flag */
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/* interrupt flags in CTL2 register */
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USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt flag */
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USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt flag */
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USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< noise error interrupt flag */
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USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< overrun error interrupt flag */
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USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< frame error interrupt flag */
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/* interrupt flags in RFCS register */
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USART_INT_FLAG_RFFINT = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */
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}usart_interrupt_flag_enum;
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/* USART interrupt enable or disable */
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typedef enum
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{
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/* interrupt in CTL0 register */
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USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */
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USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */
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USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */
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USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
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USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
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USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
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USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */
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USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
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/* interrupt in CTL1 register */
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USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
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/* interrupt in CTL2 register */
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USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */
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USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
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USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
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/* interrupt in RFCS register */
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USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */
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}usart_interrupt_enum;
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/* USART invert configure */
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typedef enum {
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/* data bit level inversion */
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USART_DINV_ENABLE, /*!< data bit level inversion */
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USART_DINV_DISABLE, /*!< data bit level not inversion */
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/* TX pin level inversion */
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USART_TXPIN_ENABLE, /*!< TX pin level inversion */
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USART_TXPIN_DISABLE, /*!< TX pin level not inversion */
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/* RX pin level inversion */
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USART_RXPIN_ENABLE, /*!< RX pin level inversion */
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USART_RXPIN_DISABLE, /*!< RX pin level not inversion */
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/* swap TX/RX pins */
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USART_SWAP_ENABLE, /*!< swap TX/RX pins */
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USART_SWAP_DISABLE, /*!< not swap TX/RX pins */
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}usart_invert_enum;
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/* USART receiver configure */
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#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
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#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
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#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
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/* USART transmitter configure */
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#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
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#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
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#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
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/* USART parity bits definitions */
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#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
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#define USART_PM_NONE CTL0_PM(0) /*!< no parity */
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#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */
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#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */
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/* USART wakeup method in mute mode */
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#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
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#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */
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#define USART_WM_ADDR CTL0_WM(1) /*!< address match */
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/* USART word length definitions */
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#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
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#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */
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#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */
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/* USART oversample mode */
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#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15))
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#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */
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#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */
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/* USART address detection mode */
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#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4))
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#define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */
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#define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */
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/* USART LIN break frame length */
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#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
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#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */
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#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */
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/* USART last bit clock pulse */
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#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
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#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */
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#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */
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/* USART clock phase */
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#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
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#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */
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#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */
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/* USART clock polarity */
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#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
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#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
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#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
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/* USART stop bits definitions */
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#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
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#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */
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#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */
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#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */
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#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */
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/* USART data is transmitted/received with the LSB/MSB first */
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#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19))
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#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */
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#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */
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/* USART auto baud rate detection mode bits definitions */
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#define CTL1_ABDM(regval) (BITS(21,22) & ((uint32_t)(regval) << 21))
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#define USART_ABDM_FTOR CTL1_ABDM(0) /*!< falling edge to rising edge measurement */
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#define USART_ABDM_FTOF CTL1_ABDM(1) /*!< falling edge to falling edge measurement */
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/* USART IrDA low-power enable */
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#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
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#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
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#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
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/* DMA enable for reception */
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#define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
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#define USART_DENR_ENABLE CTL2_DENR(1) /*!< enable for reception */
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#define USART_DENR_DISABLE CTL2_DENR(0) /*!< disable for reception */
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/* DMA enable for transmission */
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#define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
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#define USART_DENT_ENABLE CTL2_DENT(1) /*!< enable for transmission */
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#define USART_DENT_DISABLE CTL2_DENT(0) /*!< disable for transmission */
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/* USART RTS hardware flow control configure */
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#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
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#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */
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#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */
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/* USART CTS hardware flow control configure */
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#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
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#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */
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#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */
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/* USART one sample bit method configure */
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#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
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#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */
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#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */
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/* USART driver enable polarity mode */
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#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15))
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#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */
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#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */
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/* USART wakeup mode from deep-sleep mode */
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#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
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#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */
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#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */
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#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */
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/* function declarations */
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/* initialization functions */
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/* reset USART */
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void usart_deinit(uint32_t usart_periph);
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/* configure USART baud rate value */
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void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
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/* configure USART parity function */
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void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
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/* configure USART word length */
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void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
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/* configure USART stop bit length */
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void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
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/* enable USART */
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void usart_enable(uint32_t usart_periph);
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/* disable USART */
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void usart_disable(uint32_t usart_periph);
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/* configure USART transmitter */
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void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
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/* configure USART receiver */
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void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
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/* USART normal mode communication */
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/* data is transmitted/received with the LSB/MSB first */
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void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
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/* configure USART inverted */
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void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
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/* enable the USART overrun function */
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void usart_overrun_enable(uint32_t usart_periph);
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/* disable the USART overrun function */
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void usart_overrun_disable(uint32_t usart_periph);
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/* configure the USART oversample mode */
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void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp);
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/* configure sample bit method */
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void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb);
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/* enable receiver timeout */
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void usart_receiver_timeout_enable(uint32_t usart_periph);
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/* disable receiver timeout */
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void usart_receiver_timeout_disable(uint32_t usart_periph);
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/* configure receiver timeout threshold */
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void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
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/* USART transmit data function */
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void usart_data_transmit(uint32_t usart_periph, uint32_t data);
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/* USART receive data function */
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uint16_t usart_data_receive(uint32_t usart_periph);
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/* auto baud rate detection */
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/* enable auto baud rate detection */
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void usart_autobaud_detection_enable(uint32_t usart_periph);
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/* disable auto baud rate detection */
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void usart_autobaud_detection_disable(uint32_t usart_periph);
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/* configure auto baud rate detection mode */
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void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod);
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/* multi-processor communication */
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/* configure the address of the USART in wake up by address match mode */
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void usart_address_config(uint32_t usart_periph, uint8_t addr);
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/* configure address detection mode */
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void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod);
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/* enable mute mode */
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void usart_mute_mode_enable(uint32_t usart_periph);
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/* disable mute mode */
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void usart_mute_mode_disable(uint32_t usart_periph);
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/* configure wakeup method in mute mode */
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void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
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/* LIN mode communication */
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/* enable LIN mode */
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void usart_lin_mode_enable(uint32_t usart_periph);
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/* disable LIN mode */
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void usart_lin_mode_disable(uint32_t usart_periph);
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/* configure LIN break frame length */
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void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
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/* half-duplex communication */
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/* enable half-duplex mode */
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void usart_halfduplex_enable(uint32_t usart_periph);
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/* disable half-duplex mode */
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void usart_halfduplex_disable(uint32_t usart_periph);
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/* synchronous communication */
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/* enable USART clock */
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void usart_clock_enable(uint32_t usart_periph);
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/* disable USART clock */
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void usart_clock_disable(uint32_t usart_periph);
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/* configure USART synchronous mode parameters */
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void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
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/* smartcard communication */
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/* configure guard time value in smartcard mode */
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void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
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/* enable smartcard mode */
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void usart_smartcard_mode_enable(uint32_t usart_periph);
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/* disable smartcard mode */
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void usart_smartcard_mode_disable(uint32_t usart_periph);
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/* enable NACK in smartcard mode */
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void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
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/* disable NACK in smartcard mode */
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void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
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/* enable early NACK in smartcard mode */
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void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph);
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/* disable early NACK in smartcard mode */
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void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph);
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/* configure smartcard auto-retry number */
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void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
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/* configure block length */
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void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
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/* IrDA communication */
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/* enable IrDA mode */
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void usart_irda_mode_enable(uint32_t usart_periph);
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/* disable IrDA mode */
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void usart_irda_mode_disable(uint32_t usart_periph);
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/* configure the peripheral clock prescaler in USART IrDA low-power mode or SmartCard mode */
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void usart_prescaler_config(uint32_t usart_periph, uint32_t psc);
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/* configure IrDA low-power */
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void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
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/* hardware flow communication */
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/* configure hardware flow control RTS */
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void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
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/* configure hardware flow control CTS */
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void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
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/* enable RS485 driver */
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void usart_rs485_driver_enable(uint32_t usart_periph);
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/* disable RS485 driver */
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void usart_rs485_driver_disable(uint32_t usart_periph);
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/* configure driver enable assertion time */
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void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime);
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/* configure driver enable de-assertion time */
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void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime);
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/* configure driver enable polarity mode */
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void usart_depolarity_config(uint32_t usart_periph, uint32_t dep);
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/* USART DMA */
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/* configure USART DMA for reception */
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void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
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/* configure USART DMA for transmission */
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void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
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/* disable DMA on reception error */
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void usart_reception_error_dma_disable(uint32_t usart_periph);
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/* enable DMA on reception error */
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void usart_reception_error_dma_enable(uint32_t usart_periph);
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/* enable USART to wakeup the mcu from deep-sleep mode */
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void usart_wakeup_enable(uint32_t usart_periph);
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/* disable USART to wakeup the mcu from deep-sleep mode */
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void usart_wakeup_disable(uint32_t usart_periph);
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/* configure the USART wakeup mode from deep-sleep mode */
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void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum);
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/* enable USART command */
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void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype);
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/* USART receive FIFO */
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/* enable receive FIFO */
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void usart_receive_fifo_enable(uint32_t usart_periph);
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/* disable receive FIFO */
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void usart_receive_fifo_disable(uint32_t usart_periph);
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/* read receive FIFO counter number */
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uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph);
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/* flag & interrupt functions */
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/* get flag in STAT/RFCS register */
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FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
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/* clear flag in STAT register */
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void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
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/* enable USART interrupt */
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void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt);
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/* disable USART interrupt */
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void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt);
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/* get USART interrupt and flag status */
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FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
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/* clear USART interrupt flag */
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void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
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#endif /* GD32F3X0_USART_H */
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