251 lines
16 KiB
C
251 lines
16 KiB
C
/*!
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\file gd32f3x0_cec.h
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\brief definitions for the CEC
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\version 2017-06-06, V1.0.0, firmware for GD32F3x0
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\version 2019-06-01, V2.0.0, firmware for GD32F3x0
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifdef GD32F350
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#ifndef GD32F3X0_CEC_H
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#define GD32F3X0_CEC_H
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#include "gd32f3x0.h"
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/* CEC definitions */
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#define CEC CEC_BASE /*!< CEC base address */
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/* registers definitions */
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#define CEC_CTL REG32(CEC + 0x00000000U) /*!< CEC control register */
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#define CEC_CFG REG32(CEC + 0x00000004U) /*!< CEC configuration register */
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#define CEC_TDATA REG32(CEC + 0x00000008U) /*!< CEC transmit data register */
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#define CEC_RDATA REG32(CEC + 0x0000000CU) /*!< CEC receive data register */
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#define CEC_INTF REG32(CEC + 0x00000010U) /*!< CEC interrupt flag Register */
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#define CEC_INTEN REG32(CEC + 0x00000014U) /*!< CEC interrupt enable register */
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/* bits definitions */
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/* CEC_CTL */
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#define CEC_CTL_CECEN BIT(0) /*!< enable or disable HDMI-CEC controller bit */
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#define CEC_CTL_STAOM BIT(1) /*!< start of sending a message. */
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#define CEC_CTL_ENDOM BIT(2) /*!< ENDOM bit value in the next frame in Tx mode */
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/* CEC_CFG */
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#define CEC_CFG_SFT BITS(0,2) /*!< signal free time */
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#define CEC_CFG_RTOL BIT(3) /*!< reception bit timing tolerance */
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#define CEC_CFG_BRES BIT(4) /*!< whether stop receive message when detected BRE */
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#define CEC_CFG_BREG BIT(5) /*!< generate Error-bit when detected BRE in singlecast */
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#define CEC_CFG_BPLEG BIT(6) /*!< generate Error-bit when detected BPLE in singlecast */
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#define CEC_CFG_BCNG BIT(7) /*!< do not generate Error-bit in broadcast message */
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#define CEC_CFG_SFTOPT BIT(8) /*!< the SFT start option bit */
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#define CEC_CFG_OWN_ADDRESS BITS(16,30) /*!< own address */
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#define CEC_CFG_LMEN BIT(31) /*!< listen mode enable bit */
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/* CEC_TDATA */
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#define CEC_TDATA_TDATA BITS(0,7) /*!< Tx data register */
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/* CEC_RDATA */
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#define CEC_RDATA_RDATA BITS(0,7) /*!< Rx data register */
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/* CEC_INTF */
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#define CEC_INTF_BR BIT(0) /*!< Rx-byte data received */
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#define CEC_INTF_REND BIT(1) /*!< end of reception */
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#define CEC_INTF_RO BIT(2) /*!< Rx overrun */
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#define CEC_INTF_BRE BIT(3) /*!< bit rising error */
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#define CEC_INTF_BPSE BIT(4) /*!< short bit period error */
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#define CEC_INTF_BPLE BIT(5) /*!< long bit period error */
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#define CEC_INTF_RAE BIT(6) /*!< Rx ACK error */
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#define CEC_INTF_ARBF BIT(7) /*!< arbitration fail */
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#define CEC_INTF_TBR BIT(8) /*!< Tx-byte data request */
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#define CEC_INTF_TEND BIT(9) /*!< transmission successfully end */
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#define CEC_INTF_TU BIT(10) /*!< Tx data buffer underrun */
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#define CEC_INTF_TERR BIT(11) /*!< Tx-error */
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#define CEC_INTF_TAERR BIT(12) /*!< Tx ACK error flag */
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/* CEC_INTEN */
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#define CEC_INTEN_BRIE BIT(0) /*!< BR interrupt enable */
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#define CEC_INTEN_RENDIE BIT(1) /*!< REND interrupt enable */
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#define CEC_INTEN_ROIE BIT(2) /*!< RO interrupt enable */
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#define CEC_INTEN_BREIE BIT(3) /*!< BRE interrupt enable. */
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#define CEC_INTEN_BPSEIE BIT(4) /*!< BPSE interrupt enable */
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#define CEC_INTEN_BPLEIE BIT(5) /*!< BPLE interrupt enable. */
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#define CEC_INTEN_RAEIE BIT(6) /*!< RAE interrupt enable */
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#define CEC_INTEN_ARBFIE BIT(7) /*!< ARBF interrupt enable */
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#define CEC_INTEN_TBRIE BIT(8) /*!< TBR interrupt enable */
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#define CEC_INTEN_TENDIE BIT(9) /*!< TEND interrupt enable */
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#define CEC_INTEN_TUIE BIT(10) /*!< TU interrupt enable */
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#define CEC_INTEN_TERRIE BIT(11) /*!< TE interrupt enable */
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#define CEC_INTEN_TAERRIE BIT(12) /*!< TAE interrupt enable */
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/* constants definitions */
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/* signal free time */
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#define CFG_SFT(regval) (BITS(0, 2) & ((regval) << 0U))
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#define CEC_SFT_PROTOCOL_PERIOD CFG_SFT(0) /*!< the signal free time will perform as HDMI-CEC protocol description */
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#define CEC_SFT_1POINT5_PERIOD CFG_SFT(1) /*!< 1.5 nominal data bit periods */
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#define CEC_SFT_2POINT5_PERIOD CFG_SFT(2) /*!< 2.5 nominal data bit periods */
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#define CEC_SFT_3POINT5_PERIOD CFG_SFT(3) /*!< 3.5 nominal data bit periods */
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#define CEC_SFT_4POINT5_PERIOD CFG_SFT(4) /*!< 4.5 nominal data bit periods */
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#define CEC_SFT_5POINT5_PERIOD CFG_SFT(5) /*!< 5.5 nominal data bit periods */
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#define CEC_SFT_6POINT5_PERIOD CFG_SFT(6) /*!< 6.5 nominal data bit periods */
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#define CEC_SFT_7POINT5_PERIOD CFG_SFT(7) /*!< 7.5 nominal data bit periods */
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/* signal free time start option */
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#define CEC_SFT_START_STAOM ((uint32_t)0x00000000U) /*!< signal free time counter starts counting when STAOM is asserted */
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#define CEC_SFT_START_LAST CEC_CFG_SFTOPT /*!< signal free time counter starts automatically after transmission/reception end */
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/* own address */
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#define CEC_OWN_ADDRESS_CLEAR ((uint32_t)0x00000000U) /*!< own address is cleared */
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#define CEC_OWN_ADDRESS0 BIT(16) /*!< own address is 0 */
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#define CEC_OWN_ADDRESS1 BIT(17) /*!< own address is 1 */
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#define CEC_OWN_ADDRESS2 BIT(18) /*!< own address is 2 */
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#define CEC_OWN_ADDRESS3 BIT(19) /*!< own address is 3 */
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#define CEC_OWN_ADDRESS4 BIT(20) /*!< own address is 4 */
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#define CEC_OWN_ADDRESS5 BIT(21) /*!< own address is 5 */
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#define CEC_OWN_ADDRESS6 BIT(22) /*!< own address is 6 */
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#define CEC_OWN_ADDRESS7 BIT(23) /*!< own address is 7 */
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#define CEC_OWN_ADDRESS8 BIT(24) /*!< own address is 8 */
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#define CEC_OWN_ADDRESS9 BIT(25) /*!< own address is 9 */
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#define CEC_OWN_ADDRESS10 BIT(26) /*!< own address is 10 */
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#define CEC_OWN_ADDRESS11 BIT(27) /*!< own address is 11 */
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#define CEC_OWN_ADDRESS12 BIT(28) /*!< own address is 12 */
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#define CEC_OWN_ADDRESS13 BIT(29) /*!< own address is 13 */
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#define CEC_OWN_ADDRESS14 BIT(30) /*!< own address is 14 */
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/* error-bit generate */
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#define CEC_BROADCAST_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< generate Error-bit in broadcast */
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#define CEC_BROADCAST_ERROR_BIT_OFF CEC_CFG_BCNG /*!< do not generate Error-bit in broadcast */
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#define CEC_LONG_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on long bit period error */
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#define CEC_LONG_PERIOD_ERROR_BIT_ON CEC_CFG_BPLEG /*!< do not generate Error-bit on long bit period error */
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#define CEC_RISING_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on bit rising error */
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#define CEC_RISING_PERIOD_ERROR_BIT_ON CEC_CFG_BREG /*!< do not generate Error-bit on bit rising error */
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/* whether stop receive message when detected bit rising error */
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#define CEC_STOP_RISING_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< stop reception when detected bit rising error */
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#define CEC_STOP_RISING_ERROR_BIT_OFF ((uint32_t)0x00000001U) /*!< do not stop reception when detected bit rising error */
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/* flag bits */
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#define CEC_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */
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#define CEC_FLAG_REND CEC_INTF_REND /*!< end of reception */
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#define CEC_FLAG_RO CEC_INTF_RO /*!< RX overrun */
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#define CEC_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */
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#define CEC_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */
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#define CEC_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */
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#define CEC_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */
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#define CEC_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */
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#define CEC_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */
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#define CEC_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */
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#define CEC_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */
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#define CEC_FLAG_TERR CEC_INTF_TERR /*!< TX-error */
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#define CEC_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */
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/* interrupt flag bits */
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#define CEC_INT_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */
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#define CEC_INT_FLAG_REND CEC_INTF_REND /*!< end of reception */
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#define CEC_INT_FLAG_RO CEC_INTF_RO /*!< RX overrun */
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#define CEC_INT_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */
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#define CEC_INT_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */
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#define CEC_INT_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */
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#define CEC_INT_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */
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#define CEC_INT_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */
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#define CEC_INT_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */
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#define CEC_INT_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */
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#define CEC_INT_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */
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#define CEC_INT_FLAG_TERR CEC_INTF_TERR /*!< TX-error */
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#define CEC_INT_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */
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/* interrupt enable bits */
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#define CEC_INT_BR CEC_INTEN_BRIE /*!< RBR interrupt enable */
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#define CEC_INT_REND CEC_INTEN_RENDIE /*!< REND interrupt enable */
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#define CEC_INT_RO CEC_INTEN_ROIE /*!< RO interrupt enable */
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#define CEC_INT_BRE CEC_INTEN_BREIE /*!< RBRE interrupt enable. */
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#define CEC_INT_BPSE CEC_INTEN_BPSEIE /*!< RSBPE interrupt enable */
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#define CEC_INT_BPLE CEC_INTEN_BPLEIE /*!< RLBPE interrupt enable. */
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#define CEC_INT_RAE CEC_INTEN_RAEIE /*!< RAE interrupt enable */
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#define CEC_INT_ARBF CEC_INTEN_ARBFIE /*!< ALRLST interrupt enable */
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#define CEC_INT_TBR CEC_INTEN_TBRIE /*!< TBR interrupt enable */
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#define CEC_INT_TEND CEC_INTEN_TENDIE /*!< TEND interrupt enable */
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#define CEC_INT_TU CEC_INTEN_TUIE /*!< TU interrupt enable */
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#define CEC_INT_TERR CEC_INTEN_TERRIE /*!< TE interrupt enable */
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#define CEC_INT_TAERR CEC_INTEN_TAERRIE /*!< TAE interrupt enable */
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/* function declarations */
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/* reset HDMI-CEC controller */
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void cec_deinit(void);
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/* configure signal free time,the signal free time counter start option,own address */
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void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address);
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/* configure generate Error-bit, whether stop receive message when detected bit rising error */
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void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp);
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/* enable HDMI-CEC controller */
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void cec_enable(void);
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/* disable HDMI-CEC controller */
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void cec_disable(void);
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/* start CEC message transmission */
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void cec_transmission_start(void);
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/* end CEC message transmission */
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void cec_transmission_end(void);
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/* enable CEC listen mode */
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void cec_listen_mode_enable(void);
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/* disable CEC listen mode */
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void cec_listen_mode_disable(void);
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/* configure and clear own address */
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void cec_own_address_config(uint32_t address);
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/* configure signal free time and the signal free time counter start option */
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void cec_sft_config(uint32_t sftmopt,uint32_t sft);
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/* configure generate Error-bit when detected some abnormal situation or not */
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void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre);
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/* whether stop receive message when detected bit rising error */
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void cec_stop_receive_bre_config(uint32_t rxbrestp);
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/* enable reception bit timing tolerance */
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void cec_reception_tolerance_enable(void);
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/* disable reception bit timing tolerance */
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void cec_reception_tolerance_disable(void);
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/* send a data by the CEC peripheral */
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void cec_data_send(uint8_t data);
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/* receive a data by the CEC peripheral */
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uint8_t cec_data_receive(void);
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/* enable interrupt */
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void cec_interrupt_enable(uint32_t flag);
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/* disable interrupt */
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void cec_interrupt_disable(uint32_t flag);
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/* get CEC status */
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FlagStatus cec_flag_get(uint32_t flag);
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/* clear CEC status */
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void cec_flag_clear(uint32_t flag);
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/* get CEC int flag and status */
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FlagStatus cec_interrupt_flag_get(uint32_t flag);
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/* clear CEC int flag and status */
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void cec_interrupt_flag_clear(uint32_t flag);
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#endif /* GD32F3X0_CEC_H */
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#endif /* GD32F350 */
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