185 lines
4.3 KiB
C
185 lines
4.3 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-19 Nations first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdbg.h>
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#include "rtdevice.h"
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#include "board.h"
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#ifdef RT_USING_WDT
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__IO uint32_t LsiFreq = 40000;
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static rt_err_t n32_wdt_close(rt_watchdog_t *wdt)
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{
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rt_uint32_t level;
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level = rt_hw_interrupt_disable();
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/* Disable the LSI OSC */
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RCC_EnableLsi(DISABLE);
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t n32_wdt_open(rt_watchdog_t *wdt, rt_uint16_t oflag)
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{
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rt_uint32_t level;
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level = rt_hw_interrupt_disable();
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/* Enable the LSI OSC */
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RCC_EnableLsi(ENABLE);
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/* Wait till LSI is ready */
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
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while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET)
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{
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}
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET)
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{
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}
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#endif
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/* Reload IWDG counter */
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IWDG_ReloadKey();
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/* Enable IWDG (the LSI oscillator will be enabled by hardware) */
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IWDG_Enable();
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t n32_wdt_init(rt_watchdog_t *wdt)
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{
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return RT_EOK;
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}
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static rt_err_t n32_wdt_refresh(rt_watchdog_t *wdt)
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{
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rt_uint32_t level;
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level = rt_hw_interrupt_disable();
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/* Reload IWDG counter */
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IWDG_ReloadKey();
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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/**
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* @function control wdt
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*
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* @param
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* wdt whick wdt used
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* cmd control wdt options
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* args argument of conrtol
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* @retval rt_err_t the status of control result
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*
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*
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*/
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static rt_err_t n32_wdt_control(rt_watchdog_t *wdt, int cmd, void *args)
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{
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RT_ASSERT(wdt != NULL);
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uint16_t reload_value;
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uint32_t relv, prediv;
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static rt_tick_t last_tick = 0;
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relv = IWDG->RELV;
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prediv = IWDG->PREDIV;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
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{
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*(uint16_t *)args = ((relv * LsiFreq) / prediv);
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}
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break;
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case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
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{
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RT_ASSERT(*(uint16_t *)args != 0);
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reload_value = *(uint16_t *)args;
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if (reload_value > 0xFFF * 32 *1000 / LsiFreq)
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{
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LOG_W("wdg set timeout parameter too large, please less than %d ms\n", 0xFFF * 32 *1000 / LsiFreq);
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return -RT_EINVAL;
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}
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/* Enable write access to IWDG_PR and IWDG_RLR registers */
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IWDG_WriteConfig(IWDG_WRITE_ENABLE);
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/* IWDG counter clock: LSI/32 */
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IWDG_SetPrescalerDiv(IWDG_PRESCALER_DIV32);
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reload_value = ((uint32_t)reload_value * LsiFreq / 1000) / 32;
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IWDG_CntReload(reload_value);
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IWDG_WriteConfig(IWDG_WRITE_DISABLE);
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}
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break;
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case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
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*(uint16_t *)args = ((relv * LsiFreq) / prediv) - \
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(rt_tick_get() - last_tick) / RT_TICK_PER_SECOND;
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break;
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case RT_DEVICE_CTRL_WDT_KEEPALIVE:
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{
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last_tick = rt_tick_get();
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n32_wdt_refresh(wdt);
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}
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break;
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case RT_DEVICE_CTRL_WDT_START:
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{
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n32_wdt_open(wdt, *(rt_uint32_t *)args);
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last_tick = rt_tick_get();
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}
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break;
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case RT_DEVICE_CTRL_WDT_STOP:
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{
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n32_wdt_close(wdt);
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}
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break;
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default:
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return RT_EINVAL;
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}
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return RT_EOK;
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}
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static struct rt_watchdog_ops n32_wdt_ops =
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{
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.init = n32_wdt_init,
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.control = n32_wdt_control,
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};
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static struct rt_watchdog_device n32_wdt_device;
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int rt_hw_wdt_init(void)
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{
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int result = RT_EOK;
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/* Disable the LSI OSC */
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RCC_EnableLsi(DISABLE);
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n32_wdt_device.ops = &n32_wdt_ops;
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/* register watchdog device */
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result = rt_hw_watchdog_register(&n32_wdt_device, "wdt", RT_DEVICE_FLAG_RDWR, (void *)IWDG);
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return result;
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}
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INIT_DEVICE_EXPORT(rt_hw_wdt_init);
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#endif /* BSP_USING_WDT */
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