zhangjun 2d56a27c20 修改： ../../libcpu/risc-v/e310/context_gcc.S ...

enable interrupt after return form rt_hw_context_switch

2017-07-30 15:34:32 +08:00

..

applications

修改： ../../libcpu/risc-v/e310/context_gcc.S

2017-07-30 15:34:32 +08:00

drivers

修改： ../../libcpu/risc-v/e310/context_gcc.S

2017-07-30 15:34:32 +08:00

platform

修改： ../../libcpu/risc-v/e310/context_gcc.S

2017-07-30 15:34:32 +08:00

Makefile

fix trap_entry

2017-07-29 15:37:20 +08:00

openocd.cfg

new bsp for risc-v

2017-07-16 20:37:03 +08:00

rtconfig.h

修改： ../../libcpu/risc-v/e310/context_gcc.S

2017-07-30 15:34:32 +08:00

rtconfig.py

remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();

2017-07-26 16:07:01 +08:00

SConscript

new bsp for risc-v

2017-07-16 20:37:03 +08:00

SConstruct

new bsp for risc-v

2017-07-16 20:37:03 +08:00

sdram.ld

new bsp for risc-v

2017-07-16 20:37:03 +08:00

wrap_exit.c

new bsp for risc-v

2017-07-16 20:37:03 +08:00