114 lines
5.2 KiB
C
114 lines
5.2 KiB
C
////////////////////////////////////////////////////////////////////////////////
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/// @file reg_dbg.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
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/// MM32 FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __REG_DBG_H
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#define __REG_DBG_H
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// Files includes
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#include <stdint.h>
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#include <stdbool.h>
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#include "types.h"
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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////////////////////////////////////////////////////////////////////////////////
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/// @brief DBG Base Address Definition
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////////////////////////////////////////////////////////////////////////////////
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#define DBG_BASE (0x40007080UL) ///< Base Address: 0x40007080
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////////////////////////////////////////////////////////////////////////////////
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/// @brief DEBUG Registers Structure Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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__IO u32 IDCODE; ///< Code ID offset: 0x00
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__IO u32 CR; ///< Control Register offset: 0x04
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} DBGMCU_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief DBGMCU type pointer Definition
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////////////////////////////////////////////////////////////////////////////////
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#define DBGMCU ((DBGMCU_TypeDef*) DBG_BASE)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief DBGMCU_IDCODE Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define DBGMCU_IDCODE_DEV_ID_Pos (0)
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#define DBGMCU_IDCODE_DEV_ID (0xFFFFFFFFU << DBGMCU_IDCODE_DEV_ID_Pos) ///< Device identifier
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////////////////////////////////////////////////////////////////////////////////
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/// @brief DBGMCU_CR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define DBGMCU_CR_SLEEP_Pos (0)
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#define DBGMCU_CR_SLEEP (0x01U << DBGMCU_CR_SLEEP_Pos) ///< Debug Sleep mode
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#define DBGMCU_CR_STOP_Pos (1)
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#define DBGMCU_CR_STOP (0x01U << DBGMCU_CR_STOP_Pos) ///< Debug Stop mode
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#define DBGMCU_CR_STANDBY_Pos (2)
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#define DBGMCU_CR_STANDBY (0x01U << DBGMCU_CR_STANDBY_Pos) ///< Debug Standby mode
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#define DBGMCU_CR_TRACE_IOEN_Pos (5)
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#define DBGMCU_CR_TRACE_IOEN (0x01U << DBGMCU_CR_TRACE_IOEN_Pos) ///< Trace pin assignment
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#define DBGMCU_CR_TRACE_MODE_Pos (6)
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#define DBGMCU_CR_TRACE_MODE_Msk (0x03U << DBGMCU_CR_TRACE_MODE_Pos) ///< TRACE_MODE[1:0] bits (Trace Pin Assignment Control)
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#define DBGMCU_CR_TRACE_MODE_0 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 0
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#define DBGMCU_CR_TRACE_MODE_1 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 1
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#define DBGMCU_CR_TRACE_MODE_ASYNC (0x00U << DBGMCU_CR_TRACE_MODE_Pos) ///< Tracking pin uses asynchronous mode
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#define DBGMCU_CR_TRACE_MODE_SYNC1 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 1
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#define DBGMCU_CR_TRACE_MODE_SYNC2 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 2
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#define DBGMCU_CR_IWDG_STOP_Pos (8)
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#define DBGMCU_CR_IWDG_STOP (0x01U << DBGMCU_CR_IWDG_STOP_Pos) ///< Debug independent watchdog stopped when core is halted
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#define DBGMCU_CR_WWDG_STOP_Pos (9)
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#define DBGMCU_CR_WWDG_STOP (0x01U << DBGMCU_CR_WWDG_STOP_Pos) ///< Debug window watchdog stopped when core is halted
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#define DBGMCU_CR_TIM_STOP_Pos (10)
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#define DBGMCU_CR_TIM1_STOP (0x01U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM1 counter stopped when core is halted
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#define DBGMCU_CR_TIM2_STOP (0x02U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM2 counter stopped when core is halted
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#define DBGMCU_CR_TIM3_STOP (0x04U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM3 counter stopped when core is halted
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#define DBGMCU_CR_TIM4_STOP (0x08U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM4 counter stopped when core is halted
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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#endif
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////////////////////////////////////////////////////////////////////////////////
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