305 lines
8.0 KiB
Plaintext
305 lines
8.0 KiB
Plaintext
/*
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* Copyright 2021-2023 HPMicro
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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ENTRY(_start)
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STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
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HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K;
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FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
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NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K;
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SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
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MEMORY
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{
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XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
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ILM (wx) : ORIGIN = 0, LENGTH = 256K
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DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
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AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K
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NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE
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SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE
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AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
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APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k
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}
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__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
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__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
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__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
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__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
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__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
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SECTIONS
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{
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.nor_cfg_option __nor_cfg_option_load_addr__ : {
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KEEP(*(.nor_cfg_option))
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} > XPI0
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.boot_header __boot_header_load_addr__ : {
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__boot_header_start__ = .;
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KEEP(*(.boot_header))
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KEEP(*(.fw_info_table))
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KEEP(*(.dc_info))
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__boot_header_end__ = .;
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} > XPI0
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.start __app_load_addr__ : {
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. = ALIGN(8);
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KEEP(*(.start))
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} > XPI0
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__vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
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.vectors : AT(__vector_load_addr__) {
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. = ALIGN(8);
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__vector_ram_start__ = .;
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KEEP(*(.vector_table))
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KEEP(*(.isr_vector))
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. = ALIGN(8);
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__vector_ram_end__ = .;
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} > AXI_SRAM
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.fast : AT(etext + __data_end__ - __tdata_start__) {
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. = ALIGN(8);
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__ramfunc_start__ = .;
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*(.fast)
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/* RT-Thread Core Start */
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KEEP(*context_gcc.o(.text* .rodata*))
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KEEP(*port*.o (.text .text* .rodata .rodata*))
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KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
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KEEP(*trap_common.o (.text .text* .rodata .rodata*))
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KEEP(*irq.o (.text .text* .rodata .rodata*))
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KEEP(*clock.o (.text .text* .rodata .rodata*))
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KEEP(*kservice.o (.text .text* .rodata .rodata*))
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KEEP(*scheduler.o (.text .text* .rodata .rodata*))
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KEEP(*trap*.o (.text .text* .rodata .rodata*))
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KEEP(*idle.o (.text .text* .rodata .rodata*))
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KEEP(*ipc.o (.text .text* .rodata .rodata*))
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KEEP(*thread.o (.text .text* .rodata .rodata*))
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KEEP(*object.o (.text .text* .rodata .rodata*))
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KEEP(*timer.o (.text .text* .rodata .rodata*))
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KEEP(*mem.o (.text .text* .rodata .rodata*))
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KEEP(*mempool.o (.text .text* .rodata .rodata*))
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/* RT-Thread Core End */
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/* HPMicro Driver Wrapper */
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KEEP(*drv_*.o (.text .text* .rodata .rodata*))
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. = ALIGN(8);
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__ramfunc_end__ = .;
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} > AXI_SRAM
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.text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
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. = ALIGN(8);
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*(.text)
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*(.text*)
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*(.rodata)
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*(.rodata*)
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*(.srodata)
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*(.srodata*)
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*(.hash)
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*(.dyn*)
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*(.gnu*)
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*(.pl*)
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KEEP(*(.eh_frame))
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*(.eh_frame*)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(8);
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/*********************************************
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*
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* RT-Thread related sections - Start
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*
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*********************************************/
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/* section information for finsh shell */
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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. = ALIGN(4);
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. = ALIGN(4);
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__rt_init_start = .;
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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. = ALIGN(4);
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/* section information for modules */
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. = ALIGN(4);
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__rtmsymtab_start = .;
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KEEP(*(RTMSymTab))
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__rtmsymtab_end = .;
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/* RT-Thread related sections - end */
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} > XPI0
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.rel : {
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KEEP(*(.rel*))
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} > XPI0
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PROVIDE (__etext = .);
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PROVIDE (_etext = .);
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PROVIDE (etext = .);
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.fast_ram (NOLOAD) : {
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KEEP(*(.fast_ram))
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} > DLM
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.bss(NOLOAD) : {
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. = ALIGN(8);
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__bss_start__ = .;
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*(.bss)
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*(.bss*)
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*(.sbss*)
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*(.scommon)
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*(.scommon*)
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*(.dynsbss*)
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*(COMMON)
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. = ALIGN(8);
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_end = .;
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__bss_end__ = .;
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} > AXI_SRAM
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/* Note: the .tbss and .tdata section should be adjacent */
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.tbss(NOLOAD) : {
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. = ALIGN(8);
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__tbss_start__ = .;
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*(.tbss*)
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*(.tcommon*)
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_end = .;
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__tbss_end__ = .;
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} > AXI_SRAM
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.tdata : AT(etext) {
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. = ALIGN(8);
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__tdata_start__ = .;
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__thread_pointer = .;
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*(.tdata)
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*(.tdata*)
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. = ALIGN(8);
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__tdata_end__ = .;
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} > AXI_SRAM
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.data : AT(etext + __tdata_end__ - __tdata_start__) {
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. = ALIGN(8);
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__data_start__ = .;
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__global_pointer$ = . + 0x800;
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*(.data)
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*(.data*)
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*(.sdata)
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*(.sdata*)
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KEEP(*(.jcr))
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KEEP(*(.dynamic))
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KEEP(*(.got*))
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KEEP(*(.got))
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KEEP(*(.gcc_except_table))
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KEEP(*(.gcc_except_table.*))
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. = ALIGN(8);
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PROVIDE(__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE(__preinit_array_end = .);
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. = ALIGN(8);
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PROVIDE(__init_array_start = .);
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KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE(__init_array_end = .);
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. = ALIGN(8);
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PROVIDE(__finit_array_start = .);
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KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
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KEEP(*(.finit_array))
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PROVIDE(__finit_array_end = .);
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. = ALIGN(8);
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PROVIDE(__ctors_start__ = .);
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KEEP(*crtbegin*.o(.ctors))
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KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
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KEEP(*(SORT(.ctors.*)))
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KEEP(*(.ctors))
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PROVIDE(__ctors_end__ = .);
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. = ALIGN(8);
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KEEP(*crtbegin*.o(.dtors))
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KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
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KEEP(*(SORT(.dtors.*)))
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KEEP(*(.dtors))
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. = ALIGN(8);
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__data_end__ = .;
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PROVIDE (__edata = .);
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PROVIDE (_edata = .);
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PROVIDE (edata = .);
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} > AXI_SRAM
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__fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
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.heap(NOLOAD) : {
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. = ALIGN(8);
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__heap_start__ = .;
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. += HEAP_SIZE;
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__heap_end__ = .;
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} > AXI_SRAM
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.framebuffer (NOLOAD) : {
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. = ALIGN(8);
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KEEP(*(.framebuffer))
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. = ALIGN(8);
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} > AXI_SRAM
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.stack(NOLOAD) : {
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. = ALIGN(8);
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__stack_base__ = .;
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. += STACK_SIZE;
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. = ALIGN(8);
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PROVIDE (_stack = .);
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PROVIDE (_stack_in_dlm = .);
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PROVIDE( __rt_rvstack = . );
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} > AXI_SRAM
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.noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
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. = ALIGN(8);
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__noncacheable_init_start__ = .;
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KEEP(*(.noncacheable.init))
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__noncacheable_init_end__ = .;
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. = ALIGN(8);
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} > NONCACHEABLE_RAM
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.noncacheable.bss (NOLOAD) : {
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. = ALIGN(8);
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KEEP(*(.noncacheable))
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__noncacheable_bss_start__ = .;
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KEEP(*(.noncacheable.bss))
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__noncacheable_bss_end__ = .;
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. = ALIGN(8);
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} > NONCACHEABLE_RAM
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.ahb_sram (NOLOAD) : {
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KEEP(*(.ahb_sram))
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} > AHB_SRAM
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.apb_sram (NOLOAD) : {
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KEEP(*(.backup_sram))
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} > APB_SRAM
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__noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
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__noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
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.sdram (NOLOAD) : {
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. = ALIGN(8);
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__sdram_start__ = .;
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. += SDRAM_SIZE;
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__sdram_end__ = .;
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} > SDRAM
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}
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