147 lines
3.4 KiB
C
147 lines
3.4 KiB
C
/**************************************************************************//**
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* @file timer.c
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* @brief N9H30 series TIMER driver source file
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*
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* @note
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* SPDX-License-Identifier: Apache-2.0
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* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "N9H30.h"
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#include "nu_sys.h"
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#include "nu_timer.h"
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void TIMER_SET_CMP_VALUE(uint32_t timer, uint32_t u32Cmpr)
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{
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uint32_t u32TmrCMPROffset;
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u32TmrCMPROffset = REG_TMR0_CMPR + timer * 0x10;
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outpw(u32TmrCMPROffset, u32Cmpr);
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}
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void TIMER_SET_OPMODE(uint32_t timer, uint32_t u32OpMode)
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{
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uint32_t u32TmrCSROffset;
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u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
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outpw(u32TmrCSROffset, (inpw(u32TmrCSROffset) & ~(0x3UL << 27)) | u32OpMode);
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}
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void TIMER_SET_PRESCALE_VALUE(uint32_t timer, uint32_t u32PreScale)
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{
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uint32_t u32TmrCSROffset;
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u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
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outpw(u32TmrCSROffset, (inpw(u32TmrCSROffset) & ~(0xFFUL)) | u32PreScale);
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}
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uint32_t TIMER_GetModuleClock(uint32_t timer)
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{
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return 12000000;
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}
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void TIMER_Start(uint32_t timer)
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{
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uint32_t u32TmrCSROffset;
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u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
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outpw(u32TmrCSROffset, inpw(u32TmrCSROffset) | TIMER_COUNTER_ENABLE);
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}
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void TIMER_Stop(uint32_t timer)
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{
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uint32_t u32TmrCSROffset;
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u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
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outpw(u32TmrCSROffset, inpw(u32TmrCSROffset) & ~TIMER_COUNTER_ENABLE);
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}
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void TIMER_ClearCounter(uint32_t timer)
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{
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uint32_t u32TmrCSROffset;
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u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
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outpw(u32TmrCSROffset, inpw(u32TmrCSROffset) | TIMER_COUNTER_RESET);
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}
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uint32_t TIMER_GetCounter(uint32_t timer)
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{
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uint32_t u32TmrDROffset;
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u32TmrDROffset = REG_TMR0_DR + timer * 0x10;
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return inpw(u32TmrDROffset);
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}
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uint32_t TIMER_GetCompareData(uint32_t timer)
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{
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uint32_t u32TmrCMPROffset;
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u32TmrCMPROffset = REG_TMR0_CMPR + timer * 0x10;
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return inpw(u32TmrCMPROffset);
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}
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void TIMER_EnableInt(uint32_t timer)
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{
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uint32_t u32TmrCSROffset;
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u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
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outpw(u32TmrCSROffset, inpw(u32TmrCSROffset) | TIMER_INTERRUPT_ENABLE);
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}
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void TIMER_DisableInt(uint32_t timer)
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{
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uint32_t u32TmrCSROffset;
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u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
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outpw(u32TmrCSROffset, inpw(u32TmrCSROffset) & ~TIMER_INTERRUPT_ENABLE);
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}
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void TIMER_Close(uint32_t timer)
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{
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uint32_t u32TmrCSROffset;
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u32TmrCSROffset = REG_TMR0_CSR + timer * 0x10;
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outpw(u32TmrCSROffset, 0);
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}
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uint32_t TIMER_Open(uint32_t timer, uint32_t u32Mode, uint32_t u32Freq)
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{
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uint32_t u32Clk = TIMER_GetModuleClock(timer);
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uint32_t u32Cmpr = 0, u32Prescale = 0;
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uint32_t u32TmrOffset = 0;
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// Fastest possible timer working freq is u32Clk / 2. While cmpr = 2, pre-scale = 0
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if (u32Freq > (u32Clk / 2))
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{
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u32Cmpr = 2;
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}
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else
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{
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/* Clock source is only XIN. */
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u32Cmpr = u32Clk / u32Freq;
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}
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u32TmrOffset = timer * 0x10;
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TIMER_Close(timer); /* disable timer */
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TIMER_DisableInt(timer); /* clear for safety */
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outpw(REG_TMR0_CMPR + u32TmrOffset, u32Cmpr);
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outpw(REG_TMR0_CSR + u32TmrOffset, u32Mode | u32Prescale);
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return (u32Clk / (u32Cmpr * (u32Prescale + 1)));
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}
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/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
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