119 lines
2.4 KiB
C
119 lines
2.4 KiB
C
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-04-16 bigmagic first version
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*/
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#include "drv_gpio.h"
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#ifdef BSP_USING_PIN
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static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
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{
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uint32_t fselnum = pin / 10;
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uint32_t fselrest = pin % 10;
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uint32_t gpfsel = 0;
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gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
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gpfsel |= (uint32_t)(mode << (fselrest * 3));
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switch (fselnum)
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{
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case 0:
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GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
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break;
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case 1:
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GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
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break;
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case 2:
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GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
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break;
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case 3:
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GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
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break;
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case 4:
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GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
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break;
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case 5:
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GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
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break;
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default:
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break;
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}
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}
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static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
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{
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uint32_t num = pin / 32;
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if(num == 0)
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{
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if(value == 0)
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{
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GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
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}
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else
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{
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GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
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}
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}
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else
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{
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if(value == 0)
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{
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GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
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}
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else
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{
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GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
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}
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}
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}
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static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
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{
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return 0;
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}
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static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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return RT_EOK;
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}
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static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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return RT_EOK;
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}
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rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
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{
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return RT_EOK;
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}
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static const struct rt_pin_ops ops =
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{
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raspi_pin_mode,
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raspi_pin_write,
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raspi_pin_read,
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raspi_pin_attach_irq,
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raspi_pin_detach_irq,
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raspi_pin_irq_enable,
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RT_NULL,
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};
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#endif
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int rt_hw_gpio_init(void)
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{
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#ifdef BSP_USING_PIN
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rt_device_pin_register("gpio", &ops, RT_NULL);
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#endif
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return 0;
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}
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INIT_DEVICE_EXPORT(rt_hw_gpio_init);
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