694 lines
29 KiB
C
694 lines
29 KiB
C
//*****************************************************************************
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//
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// am_hal_gpio.h
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//! @file
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//!
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//! @brief Functions for accessing and configuring the GPIO module.
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//!
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//! @addtogroup gpio2 GPIO
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//! @ingroup apollo2hal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_HAL_GPIO_H
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#define AM_HAL_GPIO_H
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// DEVICE ADDRESS IS 8-bits
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#define AM_HAL_GPIO_DEV_ADDR_8 (0)
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// DEVICE ADDRESS IS 16-bits
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#define AM_HAL_GPIO_DEV_ADDR_16 (1)
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// DEVICE OFFSET IS 8-bits
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#define AM_HAL_GPIO_DEV_OFFSET_8 (0x00000000)
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// DEVICE OFFSET IS 16-bits
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#define AM_HAL_GPIO_DEV_OFFSET_16 (0x00010000)
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// Maximum number of GPIOs on this device
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#define AM_HAL_GPIO_MAX_PADS (50)
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//*****************************************************************************
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//
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//! @name GPIO Pin defines
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//! @brief GPIO Pin defines for use with interrupt functions
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//!
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//! These macros may be used to with \e am_hal_gpio_int_x().
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_BIT(n) (((uint64_t) 0x1) << n)
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//! @}
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//
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// Helper macros used for unraveling the GPIO configuration value (configval).
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//
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// Note that the configval, which is passed into functions such as
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// am_hal_gpio_pin_config() as well as various helper macros, is a concatenated
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// value that contains values used in multiple configuration registers.
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//
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// The GPIO configuration value fields are arranged as follows:
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// [ 7: 0] PADREG configuration.
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// [11: 8] GPIOCFG
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// [15:12] Unused.
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// [23:16] ALTPADREG configuration.
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//
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// Define macros describing these configval fields.
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//
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#define CFGVAL_PADREG_S 0
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#define CFGVAL_PADREG_M (0xFF << CFGVAL_PADREG_S)
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#define CFGVAL_GPIOCFG_S 8
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#define CFGVAL_GPIOCFG_M (0x0F << CFGVAL_GPIOCFG_S)
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#define CFGVAL_ALTPAD_S 16
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#define CFGVAL_ALTPAD_M (0xFF << CFGVAL_ALTPAD_S)
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//
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// Extraction macros
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//
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#define CFGVAL_PADREG_X(x) (((uint32_t)(x) & CFGVAL_PADREG_M) >> \
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CFGVAL_PADREG_S)
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#define CFGVAL_GPIOCFG_X(x) (((uint32_t)(x) & CFGVAL_GPIOCFG_M) >> \
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CFGVAL_GPIOCFG_S)
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#define CFGVAL_ALTPAD_X(x) (((uint32_t)(x) & CFGVAL_ALTPAD_M) >> \
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CFGVAL_ALTPAD_S)
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//*****************************************************************************
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//
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// Input options.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_INPEN (0x02 << CFGVAL_PADREG_S) // Enable input transistors.
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#define AM_HAL_GPIO_INCFG_RDZERO (0x01 << CFGVAL_GPIOCFG_S) // Disable input read registers.
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//*****************************************************************************
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//
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// Output options (OUTCFG)
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_OUT_DISABLE ((0x0 << 1) << CFGVAL_GPIOCFG_S)
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#define AM_HAL_GPIO_OUT_PUSHPULL ((0x1 << 1) << CFGVAL_GPIOCFG_S)
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#define AM_HAL_GPIO_OUT_OPENDRAIN ((0x2 << 1) << CFGVAL_GPIOCFG_S)
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#define AM_HAL_GPIO_OUT_3STATE ((0x3 << 1) << CFGVAL_GPIOCFG_S)
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//*****************************************************************************
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//
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// Special options for IOM0 and IOM4 clocks.
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// For 24MHz operation, a special enable must be selected. The 24MHZ select is
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// selected via bit0 of OUTCFG (which is, in a way,an alias of OUT_PUSHPULL).
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_24MHZ_ENABLE ((0x1 << 1) << CFGVAL_GPIOCFG_S)
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//*****************************************************************************
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//
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// Pad configuration options.
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// (Configuration value bits 7:0.)
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_HIGH_DRIVE (0x04 << CFGVAL_PADREG_S)
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#define AM_HAL_GPIO_LOW_DRIVE (0x00 << CFGVAL_PADREG_S)
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#define AM_HAL_GPIO_PULLUP (0x01 << CFGVAL_PADREG_S)
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#define AM_HAL_GPIO_PULL1_5K ( (0x01 << CFGVAL_PADREG_S) | \
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AM_HAL_GPIO_PULLUP )
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#define AM_HAL_GPIO_PULL6K ( (0x40 << CFGVAL_PADREG_S) | \
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AM_HAL_GPIO_PULLUP )
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#define AM_HAL_GPIO_PULL12K ( (0x80 << CFGVAL_PADREG_S) | \
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AM_HAL_GPIO_PULLUP )
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#define AM_HAL_GPIO_PULL24K ( (0xC0 << CFGVAL_PADREG_S) | \
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AM_HAL_GPIO_PULLUP )
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// POWER SWITCH is available on selected pins
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#define AM_HAL_GPIO_POWER (0x80 << CFGVAL_PADREG_S)
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//*****************************************************************************
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//
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//! ALTPADREG configuration options.
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//! (Configuration value bits 23:16.)
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//!
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//! All Apollo2 GPIO pins can be configured for 2mA or 4mA.
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//! AM_HAL_GPIO_DRIVE_2MA = 2mA configuration.
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//! AM_HAL_GPIO_DRIVE_4MA = 4mA configuration.
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//!
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//! Certain Apollo2 GPIO pins can be configured to drive up to 12mA.
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//! AM_HAL_GPIO_DRIVE_8MA = 8mA configuration.
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//! AM_HAL_GPIO_DRIVE_12MA = 12mA configuration.
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//!
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//! Notes:
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//! - Always consult the Apollo2 data sheet for the latest details.
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//! - The higher drive GPIOxx pads generally include:
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//! 0-2,5,7-8,10,12-13,22-23,26-29,38-39,42,44-48.
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//! - GPIOxx pads that do not support the higher drive:
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//! 3-4,6,9,11,14-21,24-25,30-37,40-41,43,49.
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//! - User is responsible for ensuring that the selected pin actually supports
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//! the higher drive (8mA or 12mA) capabilities. See the Apollo2 data sheet.
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//! - Attempting to set the higher drive (8mA or 12mA) configuration on a
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//! non-supporting pad will actually set the pad for 4mA drive strength,
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//! regardless of the lower bit setting.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_DRIVE_2MA ( 0 )
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#define AM_HAL_GPIO_DRIVE_4MA AM_HAL_GPIO_HIGH_DRIVE
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#define AM_HAL_GPIO_DRIVE_8MA ( 0x01 << CFGVAL_ALTPAD_S )
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#define AM_HAL_GPIO_DRIVE_12MA ( (0x01 << CFGVAL_ALTPAD_S) | \
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AM_HAL_GPIO_HIGH_DRIVE )
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#define AM_HAL_GPIO_SLEWRATE ( 0x10 << CFGVAL_ALTPAD_S )
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//*****************************************************************************
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//
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// Interrupt polarity
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// These values can be used directly in the configval.
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//
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//*****************************************************************************
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#define AM_HAL_GPIOCFGVAL_FALLING ((1 << 2) << CFGVAL_GPIOCFG_S)
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#define AM_HAL_GPIOCFGVAL_RISING ((0 << 2) << CFGVAL_GPIOCFG_S)
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//*****************************************************************************
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//
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// Pad function select
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// This macro represents the 3 bit function select field in the PADREG byte.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_FUNC(x) ((x & 0x7) << 3)
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//*****************************************************************************
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//
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//! Interrupt polarity
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//!
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//! Important:
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//! These values are to be used with am_hal_gpio_int_polarity_bit_set().
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// They are not intended to be used as part of the GPIO configval.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_FALLING 0x00000001
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#define AM_HAL_GPIO_RISING 0x00000000
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//*****************************************************************************
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//
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// A few common pin configurations.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_DISABLE \
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(AM_HAL_GPIO_FUNC(3))
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#define AM_HAL_GPIO_INPUT \
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(AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_INPEN)
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#define AM_HAL_GPIO_OUTPUT \
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(AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_PUSHPULL)
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#define AM_HAL_GPIO_OPENDRAIN \
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(AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_OPENDRAIN | AM_HAL_GPIO_INPEN)
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#define AM_HAL_GPIO_3STATE \
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(AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_3STATE)
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//*****************************************************************************
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//
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// PADREG helper macros.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_PADREG(n) \
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(AM_REG_GPIOn(0) + AM_REG_GPIO_PADREGA_O + (n & 0xFC))
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#define AM_HAL_GPIO_PADREG_S(n) \
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(((uint32_t)(n) % 4) << 3)
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#define AM_HAL_GPIO_PADREG_M(n) \
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((uint32_t) 0xFF << AM_HAL_GPIO_PADREG_S(n))
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#define AM_HAL_GPIO_PADREG_FIELD(n, configval) \
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(((uint32_t)(configval) & CFGVAL_PADREG_M) << AM_HAL_GPIO_PADREG_S(n))
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#define AM_HAL_GPIO_PADREG_W(n, configval) \
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AM_REGVAL(AM_HAL_GPIO_PADREG(n)) = \
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(AM_HAL_GPIO_PADREG_FIELD(n, configval) | \
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(AM_REGVAL(AM_HAL_GPIO_PADREG(n)) & ~AM_HAL_GPIO_PADREG_M(n)))
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#define AM_HAL_GPIO_PADREG_R(n) \
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((AM_REGVAL(AM_HAL_GPIO_PADREG(n)) & AM_HAL_GPIO_PADREG_M(n)) >> \
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AM_HAL_GPIO_PADREG_S(n))
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//*****************************************************************************
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//
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// ALTPADCFG helper macros.
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// The ALTPADCFG bits are located in [23:16] of the configval.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_ALTPADREG(n) \
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(AM_REG_GPIOn(0) + AM_REG_GPIO_ALTPADCFGA_O + (n & 0xFC))
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#define AM_HAL_GPIO_ALTPADREG_S(n) \
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(((uint32_t)(n) % 4) << 3)
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#define AM_HAL_GPIO_ALTPADREG_M(n) \
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((uint32_t) 0xFF << AM_HAL_GPIO_ALTPADREG_S(n))
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#define AM_HAL_GPIO_ALTPADREG_FIELD(n, configval) \
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(CFGVAL_ALTPAD_X(configval) << AM_HAL_GPIO_ALTPADREG_S(n))
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#define AM_HAL_GPIO_ALTPADREG_W(n, configval) \
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AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) = \
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(AM_HAL_GPIO_ALTPADREG_FIELD(n, configval) | \
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(AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) & ~AM_HAL_GPIO_ALTPADREG_M(n)))
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#define AM_HAL_GPIO_ALTPADREG_R(n) \
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((AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) & AM_HAL_GPIO_ALTPADREG_M(n)) >> \
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AM_HAL_GPIO_ALTPADREG_S(n))
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//*****************************************************************************
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//
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// CFG helper macros.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_CFG(n) \
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(AM_REG_GPIOn(0) + AM_REG_GPIO_CFGA_O + ((n & 0xF8) >> 1))
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#define AM_HAL_GPIO_CFG_S(n) \
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(((uint32_t)(n) % 8) << 2)
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#define AM_HAL_GPIO_CFG_M(n) \
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((uint32_t) 0x7 << AM_HAL_GPIO_CFG_S(n))
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#define AM_HAL_GPIO_CFG_FIELD(n, configval) \
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((((uint32_t)(configval) & 0x700) >> 8) << AM_HAL_GPIO_CFG_S(n))
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#define AM_HAL_GPIO_CFG_W(n, configval) \
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AM_REGVAL(AM_HAL_GPIO_CFG(n)) = \
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(AM_HAL_GPIO_CFG_FIELD(n, configval) | \
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(AM_REGVAL(AM_HAL_GPIO_CFG(n)) & ~AM_HAL_GPIO_CFG_M(n)))
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#define AM_HAL_GPIO_CFG_R(n) \
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((AM_REGVAL(AM_HAL_GPIO_CFG(n)) & AM_HAL_GPIO_CFG_M(n)) >> \
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AM_HAL_GPIO_CFG_S(n))
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//*****************************************************************************
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//
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// Polarity helper macros.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_POL_S(n) \
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((((uint32_t)(n) % 8) << 2) + 3)
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#define AM_HAL_GPIO_POL_M(n) \
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((uint32_t) 0x1 << AM_HAL_GPIO_POL_S(n))
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#define AM_HAL_GPIO_POL_FIELD(n, polarity) \
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(((uint32_t)(polarity) & 0x1) << AM_HAL_GPIO_POL_S(n))
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#define AM_HAL_GPIO_POL_W(n, polarity) \
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AM_REGVAL(AM_HAL_GPIO_CFG(n)) = \
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(AM_HAL_GPIO_POL_FIELD(n, polarity) | \
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(AM_REGVAL(AM_HAL_GPIO_CFG(n)) & ~AM_HAL_GPIO_POL_M(n)))
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//*****************************************************************************
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//
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// RD helper macros.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_RD_REG(n) \
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(AM_REG_GPIOn(0) + AM_REG_GPIO_RDA_O + (((uint32_t)(n) & 0x20) >> 3))
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#define AM_HAL_GPIO_RD_S(n) \
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((uint32_t)(n) % 32)
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#define AM_HAL_GPIO_RD_M(n) \
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((uint32_t) 0x1 << AM_HAL_GPIO_RD_S(n))
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#define AM_HAL_GPIO_RD(n) \
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AM_REGVAL(AM_HAL_GPIO_RD_REG(n))
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//*****************************************************************************
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//
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// WT helper macros.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_WT_REG(n) \
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(AM_REG_GPIOn(0) + AM_REG_GPIO_WTA_O + (((uint32_t)(n) & 0x20) >> 3))
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#define AM_HAL_GPIO_WT_S(n) \
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((uint32_t)(n) % 32)
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#define AM_HAL_GPIO_WT_M(n) \
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((uint32_t) 0x1 << AM_HAL_GPIO_WT_S(n))
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#define AM_HAL_GPIO_WT(n) \
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AM_REGVAL(AM_HAL_GPIO_WT_REG(n))
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//*****************************************************************************
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//
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// WTS helper macros.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_WTS_REG(n) \
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(AM_REG_GPIOn(0) + AM_REG_GPIO_WTSA_O + (((uint32_t)(n) & 0x20) >> 3))
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#define AM_HAL_GPIO_WTS_S(n) \
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((uint32_t)(n) % 32)
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#define AM_HAL_GPIO_WTS_M(n) \
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((uint32_t) 0x1 << AM_HAL_GPIO_WTS_S(n))
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#define AM_HAL_GPIO_WTS(n) \
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AM_REGVAL(AM_HAL_GPIO_WTS_REG(n))
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//*****************************************************************************
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//
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// WTC helper macros.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_WTC_REG(n) \
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(AM_REG_GPIOn(0) + AM_REG_GPIO_WTCA_O + (((uint32_t)(n) & 0x20) >> 3))
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#define AM_HAL_GPIO_WTC_S(n) \
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((uint32_t)(n) % 32)
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#define AM_HAL_GPIO_WTC_M(n) \
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((uint32_t) 0x1 << AM_HAL_GPIO_WTC_S(n))
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#define AM_HAL_GPIO_WTC(n) \
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AM_REGVAL(AM_HAL_GPIO_WTC_REG(n))
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//*****************************************************************************
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//
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// EN helper macros.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_EN_REG(n) \
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(AM_REG_GPIOn(0) + AM_REG_GPIO_ENA_O + (((uint32_t)(n) & 0x20) >> 3))
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#define AM_HAL_GPIO_EN_S(n) \
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((uint32_t)(n) % 32)
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#define AM_HAL_GPIO_EN_M(n) \
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((uint32_t) 0x1 << AM_HAL_GPIO_EN_S(n))
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#define AM_HAL_GPIO_EN(n) \
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AM_REGVAL(AM_HAL_GPIO_EN_REG(n))
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//*****************************************************************************
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//
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// ENS helper macros.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_ENS_REG(n) \
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(AM_REG_GPIOn(0) + AM_REG_GPIO_ENSA_O + (((uint32_t)(n) & 0x20) >> 3))
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#define AM_HAL_GPIO_ENS_S(n) \
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((uint32_t)(n) % 32)
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#define AM_HAL_GPIO_ENS_M(n) \
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((uint32_t) 0x1 << AM_HAL_GPIO_ENS_S(n))
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#define AM_HAL_GPIO_ENS(n) \
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AM_REGVAL(AM_HAL_GPIO_ENS_REG(n))
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//*****************************************************************************
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//
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// ENC helper macros.
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//
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//*****************************************************************************
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#define AM_HAL_GPIO_ENC_REG(n) \
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(AM_REG_GPIOn(0) + AM_REG_GPIO_ENCA_O + (((uint32_t)(n) & 0x20) >> 3))
|
|
|
|
#define AM_HAL_GPIO_ENC_S(n) \
|
|
((uint32_t)(n) % 32)
|
|
|
|
#define AM_HAL_GPIO_ENC_M(n) \
|
|
((uint32_t) 0x1 << AM_HAL_GPIO_ENC_S(n))
|
|
|
|
#define AM_HAL_GPIO_ENC(n) \
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|
AM_REGVAL(AM_HAL_GPIO_ENC_REG(n))
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Configure the GPIO PAD MUX & GPIO PIN Configurations
|
|
//!
|
|
//! @param ui32PinNumber - GPIO pin number.
|
|
//! @param ui32Config - Configuration options.
|
|
//!
|
|
//! This function applies the settings for a single GPIO. For a list of valid
|
|
//! options please see the top of this file (am_hal_gpio.h) and am_hal_pin.h.
|
|
//!
|
|
//! Usage examples:
|
|
//! am_hal_gpio_pin_config(11, AM_HAL_GPIO_INPUT);
|
|
//! am_hal_gpio_pin_config(10, AM_HAL_GPIO_OUTPUT);
|
|
//! am_hal_gpio_pin_config(14, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_SLEWRATE);
|
|
//! am_hal_gpio_pin_config(15, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_HIGHDRIVESTR);
|
|
//
|
|
//*****************************************************************************
|
|
#define am_hal_gpio_pin_config(ui32PinNumber, ui32Config) \
|
|
if ( (uint32_t)(ui32PinNumber) < AM_HAL_GPIO_MAX_PADS ) \
|
|
{ \
|
|
AM_CRITICAL_BEGIN_ASM \
|
|
\
|
|
AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; \
|
|
\
|
|
AM_HAL_GPIO_CFG_W(ui32PinNumber, ui32Config); \
|
|
AM_HAL_GPIO_PADREG_W(ui32PinNumber, ui32Config); \
|
|
AM_HAL_GPIO_ALTPADREG_W(ui32PinNumber, ui32Config); \
|
|
\
|
|
AM_REGn(GPIO, 0, PADKEY) = 0; \
|
|
\
|
|
AM_CRITICAL_END_ASM \
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Set the state of one GPIO polarity bit.
|
|
//!
|
|
//! @param ui32BitNum - GPIO number.
|
|
//! @param ui32Polarity - Desired state.
|
|
//!
|
|
//! This function sets the state of one GPIO polarity bit to a supplied value.
|
|
//! The ui32Polarity parameter should be one of the following values:
|
|
//!
|
|
//! AM_HAL_GPIO_FALLING
|
|
//! AM_HAL_GPIO_RISING
|
|
//!
|
|
//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
#define am_hal_gpio_int_polarity_bit_set(ui32BitNum, ui32Polarity) \
|
|
if ( (uint32_t)(ui32BitNum) < AM_HAL_GPIO_MAX_PADS ) \
|
|
{ \
|
|
AM_CRITICAL_BEGIN_ASM \
|
|
\
|
|
AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; \
|
|
AM_HAL_GPIO_POL_W(ui32BitNum, ui32Polarity); \
|
|
AM_REGn(GPIO, 0, PADKEY) = 0; \
|
|
\
|
|
AM_CRITICAL_END_ASM \
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Get the state of one GPIO from the INPUT READ REGISTER.
|
|
//!
|
|
//! @param ui32BitNum - GPIO number.
|
|
//!
|
|
//! This function retrieves the state of one GPIO from the INPUT READ
|
|
//! REGISTER.
|
|
//!
|
|
//! @return the state for the requested GPIO.
|
|
//
|
|
//*****************************************************************************
|
|
#define am_hal_gpio_input_bit_read(ui32BitNum) \
|
|
((AM_HAL_GPIO_RD(ui32BitNum) & AM_HAL_GPIO_RD_M(ui32BitNum)) != 0)
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Get the state of one GPIO in the DATA OUTPUT REGISTER
|
|
//!
|
|
//! @param ui32BitNum - GPIO number.
|
|
//!
|
|
//! This function retrieves the state of one GPIO in the DATA OUTPUT REGISTER.
|
|
//!
|
|
//! @return the state for the requested GPIO or -1 for error.
|
|
//
|
|
//*****************************************************************************
|
|
#define am_hal_gpio_out_bit_read(ui32BitNum) \
|
|
((AM_HAL_GPIO_WT(ui32BitNum) & AM_HAL_GPIO_WT_M(ui32BitNum)) != 0)
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Set the output state high for one GPIO.
|
|
//!
|
|
//! @param ui32BitNum - GPIO number.
|
|
//!
|
|
//! This function sets the output state to high for one GPIO.
|
|
//!
|
|
//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
#define am_hal_gpio_out_bit_set(ui32BitNum) \
|
|
AM_HAL_GPIO_WTS(ui32BitNum) = AM_HAL_GPIO_WTS_M(ui32BitNum)
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Sets the output state to low for one GPIO.
|
|
//!
|
|
//! @param ui32BitNum - GPIO number.
|
|
//!
|
|
//! This function sets the output state to low for one GPIO.
|
|
//!
|
|
//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
#define am_hal_gpio_out_bit_clear(ui32BitNum) \
|
|
AM_HAL_GPIO_WTC(ui32BitNum) = AM_HAL_GPIO_WTC_M(ui32BitNum)
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Sets the output state to ui32Value for one GPIO.
|
|
//!
|
|
//! @param ui32BitNum - GPIO number.
|
|
//! @param ui32Value - Desired output state.
|
|
//!
|
|
//! This function sets the output state to ui32Value for one GPIO.
|
|
//!
|
|
//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
#define am_hal_gpio_out_bit_replace(ui32BitNum, ui32Value) \
|
|
if ( ui32Value ) \
|
|
{ \
|
|
AM_HAL_GPIO_WTS(ui32BitNum) = AM_HAL_GPIO_WTS_M(ui32BitNum); \
|
|
} \
|
|
else \
|
|
{ \
|
|
AM_HAL_GPIO_WTC(ui32BitNum) = AM_HAL_GPIO_WTC_M(ui32BitNum); \
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Toggle the output state of one GPIO.
|
|
//!
|
|
//! @param ui32BitNum - GPIO number.
|
|
//!
|
|
//! This function toggles the output state of one GPIO.
|
|
//!
|
|
//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
#define am_hal_gpio_out_bit_toggle(ui32BitNum) \
|
|
if ( 1 ) \
|
|
{ \
|
|
AM_CRITICAL_BEGIN_ASM \
|
|
AM_HAL_GPIO_WT(ui32BitNum) ^= AM_HAL_GPIO_WT_M(ui32BitNum); \
|
|
AM_CRITICAL_END_ASM \
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Sets the output enable for one GPIO.
|
|
//!
|
|
//! @param ui32BitNum - GPIO number.
|
|
//!
|
|
//! This function sets the output enable for one GPIO.
|
|
//!
|
|
//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
#define am_hal_gpio_out_enable_bit_set(ui32BitNum) \
|
|
AM_HAL_GPIO_ENS(ui32BitNum) = AM_HAL_GPIO_ENS_M(ui32BitNum)
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Clears the output enable for one GPIO.
|
|
//!
|
|
//! @param ui32BitNum - GPIO number.
|
|
//!
|
|
//! This function clears the output enable for one GPIO.
|
|
//!
|
|
//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
#define am_hal_gpio_out_enable_bit_clear(ui32BitNum) \
|
|
AM_HAL_GPIO_ENC(ui32BitNum) = AM_HAL_GPIO_ENC_M(ui32BitNum)
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Function pointer type for GPIO interrupt handlers.
|
|
//
|
|
//*****************************************************************************
|
|
typedef void (*am_hal_gpio_handler_t)(void);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// External function prototypes
|
|
//
|
|
//*****************************************************************************
|
|
#ifdef __cplusplus
|
|
extern "C"
|
|
{
|
|
#endif
|
|
|
|
extern uint32_t am_hal_gpio_pin_config_read(uint32_t ui32PinNumber);
|
|
extern uint64_t am_hal_gpio_input_read(void);
|
|
extern uint64_t am_hal_gpio_out_read(void);
|
|
extern uint32_t am_hal_gpio_out_enable_bit_get(uint32_t ui32BitNum);
|
|
extern uint64_t am_hal_gpio_out_enable_get(void);
|
|
extern void am_hal_gpio_int_enable(uint64_t ui64InterruptMask);
|
|
extern uint64_t am_hal_gpio_int_enable_get(void);
|
|
extern void am_hal_gpio_int_disable(uint64_t ui64InterruptMask);
|
|
extern void am_hal_gpio_int_clear(uint64_t ui64InterruptMask);
|
|
extern void am_hal_gpio_int_set(uint64_t ui64InterruptMask);
|
|
extern uint64_t am_hal_gpio_int_status_get(bool bEnabledOnly);
|
|
extern void am_hal_gpio_int_service(uint64_t ui64Status);
|
|
extern void am_hal_gpio_int_register(uint32_t ui32GPIONumber,
|
|
am_hal_gpio_handler_t pfnHandler);
|
|
|
|
extern bool am_hal_gpio_int_polarity_bit_get(uint32_t ui32BitNum);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // AM_HAL_GPIO_H
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// End Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|