552 lines
22 KiB
Plaintext
552 lines
22 KiB
Plaintext
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ARM Macro Assembler Page 1
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1 00000000 ;/*
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2 00000000 ; * File : context_rvds.S
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3 00000000 ; * This file is part of RT-Thread RTOS
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4 00000000 ; * COPYRIGHT (C) 2009, RT-Thread Development Team
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5 00000000 ; *
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6 00000000 ; * The license and distribution terms for this file may
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be
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7 00000000 ; * found in the file LICENSE in this distribution or at
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8 00000000 ; * http://www.rt-thread.org/license/LICENSE
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9 00000000 ; *
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10 00000000 ; * Change Logs:
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11 00000000 ; * Date Author Notes
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12 00000000 ; * 2009-01-17 Bernard first version.
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13 00000000 ; * 2012-01-01 aozima support context switch l
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oad/store FPU register.
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14 00000000 ; * 2013-06-18 aozima add restore MSP feature.
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15 00000000 ; * 2013-06-23 aozima support lazy stack optim
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ized.
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16 00000000 ; */
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17 00000000
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18 00000000 ;/**
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19 00000000 ; * @addtogroup cortex-m4
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20 00000000 ; */
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21 00000000 ;/*@{*/
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22 00000000
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23 00000000 E000ED08
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SCB_VTOR
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EQU 0xE000ED08 ; Vector Table Offs
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et Register
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24 00000000 E000ED04
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NVIC_INT_CTRL
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EQU 0xE000ED04 ; interrupt control
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state register
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25 00000000 E000ED20
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NVIC_SYSPRI2
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EQU 0xE000ED20 ; system priority r
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egister (2)
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26 00000000 00FF0000
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NVIC_PENDSV_PRI
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EQU 0x00FF0000 ; PendSV priority v
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alue (lowest)
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27 00000000 10000000
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NVIC_PENDSVSET
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EQU 0x10000000 ; value to trigger
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PendSV exception
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28 00000000
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29 00000000 AREA |.text|, CODE, READONLY, ALIGN=
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2
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30 00000000 THUMB
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31 00000000 REQUIRE8
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32 00000000 PRESERVE8
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33 00000000
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34 00000000 IMPORT rt_thread_switch_interrupt_flag
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35 00000000 IMPORT rt_interrupt_from_thread
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36 00000000 IMPORT rt_interrupt_to_thread
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37 00000000
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38 00000000 ;/*
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ARM Macro Assembler Page 2
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39 00000000 ; * rt_base_t rt_hw_interrupt_disable();
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40 00000000 ; */
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41 00000000 rt_hw_interrupt_disable
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PROC
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42 00000000 EXPORT rt_hw_interrupt_disable
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43 00000000 F3EF 8010 MRS r0, PRIMASK
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44 00000004 B672 CPSID I
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45 00000006 4770 BX LR
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46 00000008 ENDP
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47 00000008
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48 00000008 ;/*
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49 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level);
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50 00000008 ; */
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51 00000008 rt_hw_interrupt_enable
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PROC
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52 00000008 EXPORT rt_hw_interrupt_enable
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53 00000008 F380 8810 MSR PRIMASK, r0
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54 0000000C 4770 BX LR
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55 0000000E ENDP
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56 0000000E
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57 0000000E ;/*
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58 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32
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to);
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59 0000000E ; * r0 --> from
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60 0000000E ; * r1 --> to
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61 0000000E ; */
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62 0000000E rt_hw_context_switch_interrupt
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63 0000000E EXPORT rt_hw_context_switch_interrupt
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64 0000000E rt_hw_context_switch
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PROC
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65 0000000E EXPORT rt_hw_context_switch
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66 0000000E
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67 0000000E ; set rt_thread_switch_interrupt_flag to 1
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68 0000000E 4A3A LDR r2, =rt_thread_switch_interrupt
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_flag
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69 00000010 6813 LDR r3, [r2]
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70 00000012 2B01 CMP r3, #1
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71 00000014 D004 BEQ _reswitch
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72 00000016 F04F 0301 MOV r3, #1
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73 0000001A 6013 STR r3, [r2]
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74 0000001C
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75 0000001C 4A37 LDR r2, =rt_interrupt_from_thread ;
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set rt_interrupt_f
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rom_thread
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76 0000001E 6010 STR r0, [r2]
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77 00000020
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78 00000020 _reswitch
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79 00000020 4A37 LDR r2, =rt_interrupt_to_thread ; s
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et rt_interrupt_to_
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thread
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80 00000022 6011 STR r1, [r2]
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81 00000024
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82 00000024 4837 LDR r0, =NVIC_INT_CTRL ; trigger th
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e PendSV exception
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(causes context swi
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tch)
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83 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET
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84 0000002A 6001 STR r1, [r0]
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85 0000002C 4770 BX LR
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ARM Macro Assembler Page 3
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86 0000002E ENDP
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87 0000002E
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88 0000002E ; r0 --> switch from thread stack
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89 0000002E ; r1 --> switch to thread stack
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90 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from
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] stack
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91 0000002E PendSV_Handler
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PROC
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92 0000002E EXPORT PendSV_Handler
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93 0000002E
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94 0000002E ; disable interrupt to protect context switch
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95 0000002E F3EF 8210 MRS r2, PRIMASK
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96 00000032 B672 CPSID I
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97 00000034
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98 00000034 ; get rt_thread_switch_interrupt_flag
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99 00000034 4830 LDR r0, =rt_thread_switch_interrupt
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_flag
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100 00000036 6801 LDR r1, [r0]
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101 00000038 B351 CBZ r1, pendsv_exit ; pendsv alread
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y handled
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102 0000003A
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103 0000003A ; clear rt_thread_switch_interrupt_flag to 0
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104 0000003A F04F 0100 MOV r1, #0x00
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105 0000003E 6001 STR r1, [r0]
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106 00000040
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107 00000040 482E LDR r0, =rt_interrupt_from_thread
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108 00000042 6801 LDR r1, [r0]
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109 00000044 B191 CBZ r1, switch_to_thread ; skip reg
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ister save at the f
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irst time
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110 00000046
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111 00000046 F3EF 8109 MRS r1, psp ; get from thread s
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tack pointer
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112 0000004A
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113 0000004A IF {FPU} != "SoftVFP"
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114 0000004A F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4]
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)
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115 0000004E BF08 ED21
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8B10 VSTMFDEQ r1!, {d8 - d15} ; push FPU regi
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ster s16~s31
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116 00000054 ENDIF
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117 00000054
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118 00000054 E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11
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register
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119 00000058
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120 00000058 IF {FPU} != "SoftVFP"
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121 00000058 F04F 0400 MOV r4, #0x00 ; flag = 0
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122 0000005C
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123 0000005C F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4]
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)
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124 00000060 BF08 2401 MOVEQ r4, #0x01 ; flag = 1
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125 00000064
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126 00000064 F841 4D04 STMFD r1!, {r4} ; push flag
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127 00000068 ENDIF
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128 00000068
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129 00000068 6800 LDR r0, [r0]
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130 0000006A 6001 STR r1, [r0] ; update from threa
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d stack pointer
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131 0000006C
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ARM Macro Assembler Page 4
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132 0000006C switch_to_thread
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133 0000006C 4924 LDR r1, =rt_interrupt_to_thread
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134 0000006E 6809 LDR r1, [r1]
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135 00000070 6809 LDR r1, [r1] ; load thread stack
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pointer
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136 00000072
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137 00000072 IF {FPU} != "SoftVFP"
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138 00000072 C908 LDMFD r1!, {r3} ; pop flag
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139 00000074 ENDIF
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140 00000074
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141 00000074 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11
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register
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142 00000078
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143 00000078 IF {FPU} != "SoftVFP"
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144 00000078 2B00 CMP r3, #0 ; if(flag_r3 != 0)
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145 0000007A BF18 ECB1
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8B10 VLDMFDNE r1!, {d8 - d15} ; pop FPU regis
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ter s16~s31
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146 00000080 ENDIF
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147 00000080
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148 00000080 F381 8809 MSR psp, r1 ; update stack poin
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ter
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149 00000084
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150 00000084 IF {FPU} != "SoftVFP"
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151 00000084 F04E 0E10 ORR lr, lr, #0x10 ; lr |= (1 << 4)
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, clean FPCA.
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152 00000088 2B00 CMP r3, #0 ; if(flag_r3 != 0)
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153 0000008A BF18 F02E
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0E10 BICNE lr, lr, #0x10 ; lr &= ~(1 << 4)
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, set FPCA.
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154 00000090 ENDIF
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155 00000090
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156 00000090 pendsv_exit
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157 00000090 ; restore interrupt
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158 00000090 F382 8810 MSR PRIMASK, r2
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159 00000094
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160 00000094 F04E 0E04 ORR lr, lr, #0x04
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161 00000098 4770 BX lr
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162 0000009A ENDP
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163 0000009A
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164 0000009A ;/*
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165 0000009A ; * void rt_hw_context_switch_to(rt_uint32 to);
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166 0000009A ; * r0 --> to
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167 0000009A ; * this fucntion is used to perform the first thread sw
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itch
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168 0000009A ; */
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169 0000009A rt_hw_context_switch_to
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PROC
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170 0000009A EXPORT rt_hw_context_switch_to
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171 0000009A ; set to thread
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172 0000009A 4919 LDR r1, =rt_interrupt_to_thread
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173 0000009C 6008 STR r0, [r1]
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174 0000009E
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175 0000009E IF {FPU} != "SoftVFP"
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176 0000009E ; CLEAR CONTROL.FPCA
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177 0000009E F3EF 8214 MRS r2, CONTROL ; read
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178 000000A2 F022 0204 BIC r2, #0x04 ; modify
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179 000000A6 F382 8814 MSR CONTROL, r2 ; write-back
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180 000000AA ENDIF
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ARM Macro Assembler Page 5
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181 000000AA
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182 000000AA ; set from thread to 0
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183 000000AA 4914 LDR r1, =rt_interrupt_from_thread
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184 000000AC F04F 0000 MOV r0, #0x0
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185 000000B0 6008 STR r0, [r1]
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186 000000B2
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187 000000B2 ; set interrupt flag to 1
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188 000000B2 4911 LDR r1, =rt_thread_switch_interrupt
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_flag
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189 000000B4 F04F 0001 MOV r0, #1
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190 000000B8 6008 STR r0, [r1]
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191 000000BA
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192 000000BA ; set the PendSV exception priority
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193 000000BA 4813 LDR r0, =NVIC_SYSPRI2
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194 000000BC F44F 017F LDR r1, =NVIC_PENDSV_PRI
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195 000000C0 F8D0 2000 LDR.W r2, [r0,#0x00] ; read
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196 000000C4 EA41 0102 ORR r1,r1,r2 ; modify
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197 000000C8 6001 STR r1, [r0] ; write-back
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198 000000CA
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199 000000CA ; trigger the PendSV exception (causes context switch)
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200 000000CA 480E LDR r0, =NVIC_INT_CTRL
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201 000000CC F04F 5180 LDR r1, =NVIC_PENDSVSET
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202 000000D0 6001 STR r1, [r0]
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203 000000D2
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204 000000D2 ; restore MSP
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205 000000D2 480E LDR r0, =SCB_VTOR
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206 000000D4 6800 LDR r0, [r0]
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207 000000D6 6800 LDR r0, [r0]
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208 000000D8 F380 8808 MSR msp, r0
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209 000000DC
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210 000000DC ; enable interrupts at processor level
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211 000000DC B661 CPSIE F
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212 000000DE B662 CPSIE I
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213 000000E0
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214 000000E0 ; never reach here!
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215 000000E0 ENDP
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216 000000E0
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217 000000E0 ; compatible with old version
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218 000000E0 rt_hw_interrupt_thread_switch
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PROC
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219 000000E0 EXPORT rt_hw_interrupt_thread_switch
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220 000000E0 4770 BX lr
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221 000000E2 ENDP
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222 000000E2
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223 000000E2 IMPORT rt_hw_hard_fault_exception
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224 000000E2 EXPORT HardFault_Handler
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225 000000E2 HardFault_Handler
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PROC
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226 000000E2
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227 000000E2 ; get current context
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228 000000E2 F3EF 8009 MRS r0, psp ; get fault thread
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stack pointer
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229 000000E6 B500 PUSH {lr}
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230 000000E8 F7FF FFFE BL rt_hw_hard_fault_exception
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231 000000EC F85D EB04 POP {lr}
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232 000000F0
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233 000000F0 F04E 0E04 ORR lr, lr, #0x04
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234 000000F4 4770 BX lr
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235 000000F6 ENDP
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ARM Macro Assembler Page 6
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236 000000F6
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237 000000F6 00 00 ALIGN 4
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238 000000F8
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239 000000F8 END
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00000000
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00000000
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00000000
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E000ED04
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E000ED20
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E000ED08
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Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp --apcs=int
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erwork --depend=.\build\context_rvds.d -o.\build\context_rvds.o -IC:\Users\zylw
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w\Documents\Study\CodeHub\rt-thread\bsp\tm4c129x-dk\RTE -IC:\Software\Keil\ARM\
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PACK\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C129 -IC:\Software\Keil\ARM\CMSIS\In
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clude --predefine="__UVISION_VERSION SETA 521" --predefine="TM4C129XNCZAD SETA
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1" --list=.\context_rvds.lst ../../libcpu/arm/cortex-m4/context_rvds.S
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ARM Macro Assembler Page 1 Alphabetic symbol ordering
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Relocatable symbols
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.text 00000000
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Symbol: .text
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Definitions
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At line 29 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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None
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Comment: .text unused
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HardFault_Handler 000000E2
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Symbol: HardFault_Handler
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Definitions
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At line 225 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 224 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: HardFault_Handler used once
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PendSV_Handler 0000002E
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Symbol: PendSV_Handler
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Definitions
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At line 91 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 92 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: PendSV_Handler used once
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_reswitch 00000020
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Symbol: _reswitch
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Definitions
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At line 78 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 71 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: _reswitch used once
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pendsv_exit 00000090
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Symbol: pendsv_exit
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Definitions
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At line 156 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 101 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: pendsv_exit used once
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rt_hw_context_switch 0000000E
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Symbol: rt_hw_context_switch
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Definitions
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At line 64 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 65 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: rt_hw_context_switch used once
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rt_hw_context_switch_interrupt 0000000E
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Symbol: rt_hw_context_switch_interrupt
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Definitions
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At line 62 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 63 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: rt_hw_context_switch_interrupt used once
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rt_hw_context_switch_to 0000009A
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Symbol: rt_hw_context_switch_to
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ARM Macro Assembler Page 2 Alphabetic symbol ordering
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Relocatable symbols
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Definitions
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At line 169 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 170 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: rt_hw_context_switch_to used once
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rt_hw_interrupt_disable 00000000
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Symbol: rt_hw_interrupt_disable
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Definitions
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At line 41 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 42 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: rt_hw_interrupt_disable used once
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rt_hw_interrupt_enable 00000008
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Symbol: rt_hw_interrupt_enable
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Definitions
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At line 51 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 52 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: rt_hw_interrupt_enable used once
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rt_hw_interrupt_thread_switch 000000E0
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Symbol: rt_hw_interrupt_thread_switch
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Definitions
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At line 218 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 219 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: rt_hw_interrupt_thread_switch used once
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switch_to_thread 0000006C
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Symbol: switch_to_thread
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Definitions
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At line 132 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 109 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: switch_to_thread used once
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12 symbols
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ARM Macro Assembler Page 1 Alphabetic symbol ordering
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Absolute symbols
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NVIC_INT_CTRL E000ED04
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Symbol: NVIC_INT_CTRL
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Definitions
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At line 24 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 82 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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At line 200 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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NVIC_PENDSVSET 10000000
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Symbol: NVIC_PENDSVSET
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Definitions
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At line 27 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 83 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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At line 201 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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NVIC_PENDSV_PRI 00FF0000
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Symbol: NVIC_PENDSV_PRI
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Definitions
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At line 26 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 194 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: NVIC_PENDSV_PRI used once
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NVIC_SYSPRI2 E000ED20
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Symbol: NVIC_SYSPRI2
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Definitions
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At line 25 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 193 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: NVIC_SYSPRI2 used once
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SCB_VTOR E000ED08
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Symbol: SCB_VTOR
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Definitions
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At line 23 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 205 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: SCB_VTOR used once
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5 symbols
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ARM Macro Assembler Page 1 Alphabetic symbol ordering
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External symbols
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rt_hw_hard_fault_exception 00000000
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Symbol: rt_hw_hard_fault_exception
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Definitions
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At line 223 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 230 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Comment: rt_hw_hard_fault_exception used once
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rt_interrupt_from_thread 00000000
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Symbol: rt_interrupt_from_thread
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Definitions
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At line 35 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 75 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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At line 107 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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At line 183 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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rt_interrupt_to_thread 00000000
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Symbol: rt_interrupt_to_thread
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Definitions
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At line 36 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 79 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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At line 133 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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At line 172 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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rt_thread_switch_interrupt_flag 00000000
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Symbol: rt_thread_switch_interrupt_flag
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Definitions
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At line 34 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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Uses
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At line 68 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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At line 99 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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At line 188 in file ../../libcpu/arm/cortex-m4/context_rvds.S
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4 symbols
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356 symbols in table
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