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2322f0154e
Confirmed with milkv, only the sd card version is sold by default for duo in the market. The spi pins are provided through stamp holes, so that users can solder the corresponding components on their baseboard during secondary development. In order to simplify maintenance work, the mainline will only support the sd-card version and no longer support spinor/spinand. Updated config files the same in this patch. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
279 lines
6.8 KiB
C
279 lines
6.8 KiB
C
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024/02/22 flyingcys first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "drv_adc.h"
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#include "drv_pinmux.h"
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#include "drv_ioremap.h"
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#define DBG_LEVEL DBG_LOG
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#include <rtdbg.h>
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#define LOG_TAG "DRV.ADC"
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rt_inline void cvi_set_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
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{
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value |= mmio_read_32(reg_base + SARADC_CTRL_OFFSET);
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mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value);
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}
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rt_inline void cvi_reset_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
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{
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value = mmio_read_32(reg_base + SARADC_CTRL_OFFSET) & ~value;
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mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value);
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}
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rt_inline rt_uint32_t cvi_get_saradc_status(unsigned long reg_base)
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{
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return((rt_uint32_t)mmio_read_32(reg_base + SARADC_STATUS_OFFSET));
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}
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rt_inline void cvi_set_cyc(unsigned long reg_base)
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{
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rt_uint32_t value;
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value = mmio_read_32(reg_base + SARADC_CYC_SET_OFFSET);
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value &= ~SARADC_CYC_CLKDIV_DIV_16;
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mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
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value |= SARADC_CYC_CLKDIV_DIV_16; //set saradc clock cycle=840ns
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mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
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}
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rt_inline void cvi_do_calibration(unsigned long reg_base)
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{
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rt_uint32_t val;
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val = mmio_read_32(reg_base + SARADC_TEST_OFFSET);
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val |= 1 << SARADC_TEST_VREFSEL_BIT;
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mmio_write_32(reg_base + SARADC_TEST_OFFSET, val);
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val = mmio_read_32(reg_base + SARADC_TRIM_OFFSET);
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val |= 0x4;
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mmio_write_32(reg_base + SARADC_TRIM_OFFSET, val);
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}
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struct cvi_adc_dev
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{
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struct rt_adc_device device;
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const char *name;
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rt_ubase_t base;
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};
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static struct cvi_adc_dev adc_dev_config[] =
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{
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#ifdef BSP_USING_ADC_ACTIVE
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{
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.name = "adc1",
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.base = SARADC_BASE
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},
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#endif /* BSP_USING_ADC_ACTIVE */
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#ifdef BSP_USING_ADC_NODIE
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{
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.name = "adc2",
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.base = RTC_ADC_BASE
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},
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#endif /* BSP_USING_ADC_NODIE */
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};
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static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
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{
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struct cvi_adc_dev *adc_dev = (struct cvi_adc_dev *)device->parent.user_data;
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uint32_t value;
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RT_ASSERT(adc_dev != RT_NULL);
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if (channel > SARADC_CH_MAX)
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return -RT_EINVAL;
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if (enabled)
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{
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//set channel
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cvi_set_saradc_ctrl(adc_dev->base, (rt_uint32_t)channel << (SARADC_CTRL_SEL_POS + 1));
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//set saradc clock cycle
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cvi_set_cyc(adc_dev->base);
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//start
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cvi_set_saradc_ctrl(adc_dev->base, SARADC_CTRL_START);
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LOG_D("enable saradc...");
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}
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else
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{
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cvi_reset_saradc_ctrl(adc_dev->base, (rt_uint32_t)channel << (SARADC_CTRL_SEL_POS + 1));
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LOG_D("disable saradc...");
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}
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return RT_EOK;
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}
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static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
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{
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struct cvi_adc_dev *adc_dev = (struct cvi_adc_dev *)device->parent.user_data;
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rt_uint32_t result;
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rt_uint32_t cnt = 0;
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RT_ASSERT(adc_dev != RT_NULL);
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if (channel > SARADC_CH_MAX)
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return -RT_EINVAL;
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while (cvi_get_saradc_status(adc_dev->base) & SARADC_STATUS_BUSY)
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{
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rt_thread_delay(10);
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LOG_D("wait saradc ready");
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cnt ++;
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if (cnt > 100)
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return -RT_ETIMEOUT;
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}
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result = mmio_read_32(adc_dev->base + SARADC_RESULT(channel - 1));
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if (result & SARADC_RESULT_VALID)
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{
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*value = result & SARADC_RESULT_MASK;
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LOG_D("saradc channel %d value: %04x", channel, *value);
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}
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else
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{
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LOG_E("saradc channel %d read failed. result:0x%04x", channel, result);
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return -RT_ERROR;
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}
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return RT_EOK;
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}
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static const struct rt_adc_ops _adc_ops =
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{
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.enabled = _adc_enabled,
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.convert = _adc_convert,
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};
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#if defined(BOARD_TYPE_MILKV_DUO)
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/*
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* cv180xb supports
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* - adc1 & adc2 for active domain
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* - adc3 for no-die domain
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*/
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#ifdef BSP_USING_ADC_ACTIVE
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static const char *pinname_whitelist_adc1_active[] = {
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"ADC1",
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NULL,
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};
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static const char *pinname_whitelist_adc2_active[] = {
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NULL,
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};
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static const char *pinname_whitelist_adc3_active[] = {
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NULL,
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};
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#endif
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#ifdef BSP_USING_ADC_NODIE
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static const char *pinname_whitelist_adc1_nodie[] = {
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"PWR_GPIO2",
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NULL,
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};
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static const char *pinname_whitelist_adc2_nodie[] = {
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"PWR_GPIO1",
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NULL,
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};
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static const char *pinname_whitelist_adc3_nodie[] = {
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"PWR_VBAT_DET",
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NULL,
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};
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#endif
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#elif defined(BOARD_TYPE_MILKV_DUO256M)
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/*
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* sg2002 supports
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* - adc1 for active domain
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* - adc1/adc2/adc3 for no-die domain
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*/
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#ifdef BSP_USING_ADC_ACTIVE
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static const char *pinname_whitelist_adc1_active[] = {
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"ADC1",
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NULL,
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};
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static const char *pinname_whitelist_adc2_active[] = {
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NULL,
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};
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static const char *pinname_whitelist_adc3_active[] = {
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NULL,
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};
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#endif
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#ifdef BSP_USING_ADC_NODIE
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static const char *pinname_whitelist_adc1_nodie[] = {
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"PWR_GPIO2",
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NULL,
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};
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static const char *pinname_whitelist_adc2_nodie[] = {
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"PWR_GPIO1",
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NULL,
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};
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static const char *pinname_whitelist_adc3_nodie[] = {
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"PWR_VBAT_DET",
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NULL,
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};
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#endif
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#else
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#error "Unsupported board type!"
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#endif
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static void rt_hw_adc_pinmux_config()
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{
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#ifdef BSP_USING_ADC_ACTIVE
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pinmux_config(BSP_ACTIVE_ADC1_PINNAME, XGPIOB_3, pinname_whitelist_adc1_active);
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pinmux_config(BSP_ACTIVE_ADC2_PINNAME, XGPIOB_6, pinname_whitelist_adc2_active);
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/* cv1800b & sg2002 don't support ADC3 either in active domain */
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#endif
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#ifdef BSP_USING_ADC_NODIE
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pinmux_config(BSP_NODIE_ADC1_PINNAME, PWR_GPIO_2, pinname_whitelist_adc1_nodie);
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pinmux_config(BSP_NODIE_ADC2_PINNAME, PWR_GPIO_1, pinname_whitelist_adc2_nodie);
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pinmux_config(BSP_NODIE_ADC3_PINNAME, PWR_VBAT_DET, pinname_whitelist_adc3_nodie);
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#endif
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}
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int rt_hw_adc_init(void)
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{
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rt_uint8_t i;
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for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++)
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{
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if (!rt_strcmp(adc_dev_config[i].name, "adc1"))
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{
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adc_dev_config[i].base = (rt_ubase_t)DRV_IOREMAP(SARADC_BASE, 0x10000);
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}
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else if (!rt_strcmp(adc_dev_config[i].name, "adc2"))
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{
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adc_dev_config[i].base = (rt_ubase_t)DRV_IOREMAP(RTC_ADC_BASE, 0x1000);
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}
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}
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rt_hw_adc_pinmux_config();
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for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++)
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{
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cvi_do_calibration(adc_dev_config[i].base);
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if (rt_hw_adc_register(&adc_dev_config[i].device, adc_dev_config[i].name, &_adc_ops, &adc_dev_config[i]) != RT_EOK)
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{
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LOG_E("%s register failed!", adc_dev_config[i].name);
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return -RT_ERROR;
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}
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}
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return RT_EOK;
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}
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INIT_DEVICE_EXPORT(rt_hw_adc_init);
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