3627 lines
153 KiB
C
3627 lines
153 KiB
C
#ifndef __SWM320_H__
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#define __SWM320_H__
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M0 Processor Exceptions Numbers **********************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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/****** Cortex-M4 specific Interrupt Numbers ************************************************/
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GPIOA0_IRQn = 0,
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GPIOA1_IRQn = 1,
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GPIOA2_IRQn = 2,
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GPIOA3_IRQn = 3,
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GPIOA4_IRQn = 4,
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GPIOA5_IRQn = 5,
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GPIOA6_IRQn = 6,
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GPIOA7_IRQn = 7,
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GPIOB0_IRQn = 8,
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GPIOB1_IRQn = 9,
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GPIOB2_IRQn = 10,
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GPIOB3_IRQn = 11,
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GPIOB4_IRQn = 12,
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GPIOB5_IRQn = 13,
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GPIOB6_IRQn = 14,
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GPIOB7_IRQn = 15,
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GPIOC0_IRQn = 16,
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GPIOC1_IRQn = 17,
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GPIOC2_IRQn = 18,
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GPIOC3_IRQn = 19,
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GPIOC4_IRQn = 20,
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GPIOC5_IRQn = 21,
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GPIOC6_IRQn = 22,
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GPIOC7_IRQn = 23,
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GPIOM0_IRQn = 24,
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GPIOM1_IRQn = 25,
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GPIOM2_IRQn = 26,
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GPIOM3_IRQn = 27,
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GPIOM4_IRQn = 28,
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GPIOM5_IRQn = 29,
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GPIOM6_IRQn = 30,
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GPIOM7_IRQn = 31,
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DMA_IRQn = 32,
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LCD_IRQn = 33,
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NORFLC_IRQn = 34,
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CAN_IRQn = 35,
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PULSE_IRQn = 36,
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WDT_IRQn = 37,
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PWM_IRQn = 38,
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UART0_IRQn = 39,
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UART1_IRQn = 40,
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UART2_IRQn = 41,
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UART3_IRQn = 42,
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UART4_IRQn = 43,
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I2C0_IRQn = 44,
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I2C1_IRQn = 45,
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SPI0_IRQn = 46,
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ADC0_IRQn = 47,
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RTC_IRQn = 48,
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BOD_IRQn = 49,
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SDIO_IRQn = 50,
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GPIOA_IRQn = 51,
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GPIOB_IRQn = 52,
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GPIOC_IRQn = 53,
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GPIOM_IRQn = 54,
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GPION_IRQn = 55,
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GPIOP_IRQn = 56,
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ADC1_IRQn = 57,
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FPU_IRQn = 58,
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SPI1_IRQn = 59,
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TIMR0_IRQn = 60,
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TIMR1_IRQn = 61,
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TIMR2_IRQn = 62,
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TIMR3_IRQn = 63,
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TIMR4_IRQn = 64,
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TIMR5_IRQn = 65,
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M0 Processor and Core Peripherals */
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#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 1 /*!< SWM320 provides an MPU */
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#define __NVIC_PRIO_BITS 3 /*!< SWM320 uses 3 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 0 /*!< FPU present */
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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#include <stdio.h>
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#include "core_cm4.h" /* Cortex-M0 processor and core peripherals */
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#include "system_SWM320.h"
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/******************************************************************************/
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/* Device Specific Peripheral registers structures */
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/******************************************************************************/
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typedef struct {
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__IO uint32_t CLKSEL; //Clock Select
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__IO uint32_t CLKDIV;
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__IO uint32_t CLKEN; //Clock Enable
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__IO uint32_t SLEEP;
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uint32_t RESERVED0[6];
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__IO uint32_t RTCBKP_ISO; //[0] 1 RTC<54><43><EFBFBD>ݵ<EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD>ڸ<EFBFBD><DAB8><EFBFBD>״̬ 0 RTC<54><43><EFBFBD>ݵ<EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>ɷ<EFBFBD><C9B7><EFBFBD>
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__IO uint32_t RTCWKEN; //[0] 1 ʹ<><CAB9>RTC<54><43><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD>
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uint32_t RESERVED[52+64];
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__IO uint32_t PAWKEN; //Port A Wakeup Enable
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__IO uint32_t PBWKEN;
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__IO uint32_t PCWKEN;
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uint32_t RESERVED2[1+4];
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__IO uint32_t PAWKSR; //Port A Wakeup Status Register<65><72>д1<D0B4><31><EFBFBD><EFBFBD>
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__IO uint32_t PBWKSR;
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__IO uint32_t PCWKSR;
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uint32_t RESERVED3[64-10];
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__IO uint32_t RSTCR; //Reset Control Register
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__IO uint32_t RSTSR; //Reset Status Register
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uint32_t RESERVED4[61+64];
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__IO uint32_t BKP[3]; //<2F><><EFBFBD>ݱ<EFBFBD><DDB1>ݼĴ<DDBC><C4B4><EFBFBD>
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//RTC Power Domain: 0x4001E000
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uint32_t RESERVED5[(0x4001E000-0x40000508)/4-1];
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__IO uint32_t RTCBKP[8]; //RTC<54><43>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1>ݼĴ<DDBC><C4B4><EFBFBD>
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__IO uint32_t LRCCR; //Low speed RC Control Register
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__IO uint32_t LRCTRIM0; //Low speed RC Trim
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__IO uint32_t LRCTRIM1;
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uint32_t RESERVED6;
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__IO uint32_t RTCLDOTRIM; //RTC Power Domain LDO Trim
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//Analog Control: 0x40031000
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uint32_t RESERVED7[(0x40031000-0x4001E030)/4-1];
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__IO uint32_t HRCCR; //High speed RC Control Register
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uint32_t RESERVED8[7];
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__IO uint32_t XTALCR;
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__IO uint32_t PLLCR;
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__IO uint32_t PLLDIV;
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__IO uint32_t PLLSET;
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__IO uint32_t PLLLOCK; //[0] 1 PLL<4C><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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__IO uint32_t BODIE;
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__IO uint32_t BODIF;
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__IO uint32_t ADC1IN7;
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} SYS_TypeDef;
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#define SYS_CLKSEL_LFCK_Pos 0 //Low Frequency Clock Source 0 LRC 1 PLL
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#define SYS_CLKSEL_LFCK_Msk (0x01 << SYS_CLKSEL_LFCK_Pos)
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#define SYS_CLKSEL_HFCK_Pos 1 //High Frequency Clock Source 0 HRC 1 XTAL
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#define SYS_CLKSEL_HFCK_Msk (0x01 << SYS_CLKSEL_HFCK_Pos)
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#define SYS_CLKSEL_SYS_Pos 2 //ϵͳʱ<CDB3><CAB1>ѡ<EFBFBD><D1A1> 0 LFCK 1 HFCK
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#define SYS_CLKSEL_SYS_Msk (0x01 << SYS_CLKSEL_SYS_Pos)
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#define SYS_CLKDIV_SYS_Pos 0 //ϵͳʱ<CDB3>ӷ<EFBFBD>Ƶ 0 1<><31>Ƶ 1 2<><32>Ƶ
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#define SYS_CLKDIV_SYS_Msk (0x01 << SYS_CLKDIV_SYS_Pos)
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#define SYS_CLKDIV_PWM_Pos 1 //PWM ʱ<>ӷ<EFBFBD>Ƶ 0 1<><31>Ƶ 1 8<><38>Ƶ
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#define SYS_CLKDIV_PWM_Msk (0x01 << SYS_CLKDIV_PWM_Pos)
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#define SYS_CLKDIV_SDRAM_Pos 2 //SDRAMʱ<4D>ӷ<EFBFBD>Ƶ 0 1<><31>Ƶ 1 2<><32>Ƶ 2 4<><34>Ƶ
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#define SYS_CLKDIV_SDRAM_Msk (0x03 << SYS_CLKDIV_SDRAM_Pos)
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#define SYS_CLKDIV_SDIO_Pos 4 //SDIOʱ<4F>ӷ<EFBFBD>Ƶ 0 1<><31>Ƶ 1 2<><32>Ƶ 2 4<><34>Ƶ 3 8<><38>Ƶ
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#define SYS_CLKDIV_SDIO_Msk (0x03 << SYS_CLKDIV_SDIO_Pos)
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#define SYS_CLKEN_GPIOA_Pos 0
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#define SYS_CLKEN_GPIOA_Msk (0x01 << SYS_CLKEN_GPIOA_Pos)
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#define SYS_CLKEN_GPIOB_Pos 1
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#define SYS_CLKEN_GPIOB_Msk (0x01 << SYS_CLKEN_GPIOB_Pos)
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#define SYS_CLKEN_GPIOC_Pos 2
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#define SYS_CLKEN_GPIOC_Msk (0x01 << SYS_CLKEN_GPIOC_Pos)
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#define SYS_CLKEN_GPIOM_Pos 4
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#define SYS_CLKEN_GPIOM_Msk (0x01 << SYS_CLKEN_GPIOM_Pos)
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#define SYS_CLKEN_GPION_Pos 5
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#define SYS_CLKEN_GPION_Msk (0x01 << SYS_CLKEN_GPION_Pos)
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#define SYS_CLKEN_TIMR_Pos 6
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#define SYS_CLKEN_TIMR_Msk (0x01 << SYS_CLKEN_TIMR_Pos)
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#define SYS_CLKEN_WDT_Pos 7
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#define SYS_CLKEN_WDT_Msk (0x01 << SYS_CLKEN_WDT_Pos)
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#define SYS_CLKEN_ADC0_Pos 8
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#define SYS_CLKEN_ADC0_Msk (0x01 << SYS_CLKEN_ADC0_Pos)
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#define SYS_CLKEN_PWM_Pos 9
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#define SYS_CLKEN_PWM_Msk (0x01 << SYS_CLKEN_PWM_Pos)
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#define SYS_CLKEN_RTC_Pos 10
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#define SYS_CLKEN_RTC_Msk (0x01 << SYS_CLKEN_RTC_Pos)
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#define SYS_CLKEN_UART0_Pos 11
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#define SYS_CLKEN_UART0_Msk (0x01 << SYS_CLKEN_UART0_Pos)
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#define SYS_CLKEN_UART1_Pos 12
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#define SYS_CLKEN_UART1_Msk (0x01 << SYS_CLKEN_UART1_Pos)
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#define SYS_CLKEN_UART2_Pos 13
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#define SYS_CLKEN_UART2_Msk (0x01 << SYS_CLKEN_UART2_Pos)
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#define SYS_CLKEN_UART3_Pos 14
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#define SYS_CLKEN_UART3_Msk (0x01 << SYS_CLKEN_UART3_Pos)
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#define SYS_CLKEN_UART4_Pos 15
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#define SYS_CLKEN_UART4_Msk (0x01 << SYS_CLKEN_UART4_Pos)
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#define SYS_CLKEN_SPI0_Pos 16
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#define SYS_CLKEN_SPI0_Msk (0x01 << SYS_CLKEN_SPI0_Pos)
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#define SYS_CLKEN_I2C0_Pos 17
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#define SYS_CLKEN_I2C0_Msk (0x01 << SYS_CLKEN_I2C0_Pos)
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#define SYS_CLKEN_I2C1_Pos 18
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#define SYS_CLKEN_I2C1_Msk (0x01 << SYS_CLKEN_I2C1_Pos)
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#define SYS_CLKEN_I2C2_Pos 19
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#define SYS_CLKEN_I2C2_Msk (0x01 << SYS_CLKEN_I2C2_Pos)
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#define SYS_CLKEN_LCD_Pos 20
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#define SYS_CLKEN_LCD_Msk (0x01 << SYS_CLKEN_LCD_Pos)
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#define SYS_CLKEN_GPIOP_Pos 21
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#define SYS_CLKEN_GPIOP_Msk (0x01 << SYS_CLKEN_GPIOP_Pos)
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#define SYS_CLKEN_ANAC_Pos 22 //ģ<><C4A3><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD>Ԫʱ<D4AA><CAB1>ʹ<EFBFBD><CAB9>
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#define SYS_CLKEN_ANAC_Msk (0x01 << SYS_CLKEN_ANAC_Pos)
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#define SYS_CLKEN_CRC_Pos 23
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#define SYS_CLKEN_CRC_Msk (0x01 << SYS_CLKEN_CRC_Pos)
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#define SYS_CLKEN_RTCBKP_Pos 24
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#define SYS_CLKEN_RTCBKP_Msk (0x01 << SYS_CLKEN_RTCBKP_Pos)
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#define SYS_CLKEN_CAN_Pos 25
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#define SYS_CLKEN_CAN_Msk (0x01 << SYS_CLKEN_CAN_Pos)
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#define SYS_CLKEN_SDRAM_Pos 26
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#define SYS_CLKEN_SDRAM_Msk (0x01 << SYS_CLKEN_SDRAM_Pos)
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#define SYS_CLKEN_NORFL_Pos 27 //NOR Flash
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#define SYS_CLKEN_NORFL_Msk (0x01 << SYS_CLKEN_NORFL_Pos)
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#define SYS_CLKEN_RAMC_Pos 28
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#define SYS_CLKEN_RAMC_Msk (0x01 << SYS_CLKEN_RAMC_Pos)
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#define SYS_CLKEN_SDIO_Pos 29
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#define SYS_CLKEN_SDIO_Msk (0x01 << SYS_CLKEN_SDIO_Pos)
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#define SYS_CLKEN_ADC1_Pos 30
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#define SYS_CLKEN_ADC1_Msk (0x01 << SYS_CLKEN_ADC1_Pos)
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#define SYS_CLKEN_ALIVE_Pos 31 //CHIPALIVE<56><45>Դ<EFBFBD><D4B4>ϵͳʱ<CDB3><CAB1>ʹ<EFBFBD><CAB9>
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#define SYS_CLKEN_ALIVE_Msk (0x01 << SYS_CLKEN_ALIVE_Pos)
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#define SYS_SLEEP_SLEEP_Pos 0 //<2F><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>1<EFBFBD><31><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SLEEPģʽ
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#define SYS_SLEEP_SLEEP_Msk (0x01 << SYS_SLEEP_SLEEP_Pos)
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#define SYS_SLEEP_DEEP_Pos 1 //<2F><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>1<EFBFBD><31><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>STOP SLEEPģʽ
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#define SYS_SLEEP_DEEP_Msk (0x01 << SYS_SLEEP_DEEP_Pos)
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#define SYS_RSTCR_SYS_Pos 0 //д1<D0B4><31><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_SYS_Msk (0x01 << SYS_RSTCR_SYS_Pos)
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#define SYS_RSTCR_FLASH_Pos 1 //д1<D0B4><31>FLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>θ<EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_FLASH_Msk (0x01 << SYS_RSTCR_FLASH_Pos)
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#define SYS_RSTCR_PWM_Pos 2 //д1<D0B4><31>PWM<57><4D><EFBFBD><EFBFBD>һ<EFBFBD>θ<EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_PWM_Msk (0x01 << SYS_RSTCR_PWM_Pos)
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#define SYS_RSTCR_CPU_Pos 3 //д1<D0B4><31>CPU<50><55><EFBFBD><EFBFBD>һ<EFBFBD>θ<EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_CPU_Msk (0x01 << SYS_RSTCR_CPU_Pos)
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#define SYS_RSTCR_DMA_Pos 4 //д1<D0B4><31>DMA<4D><41><EFBFBD><EFBFBD>һ<EFBFBD>θ<EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_DMA_Msk (0x01 << SYS_RSTCR_DMA_Pos)
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#define SYS_RSTCR_NORFLASH_Pos 5 //д1<D0B4><31>NOR Flash<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>θ<EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_NORFLASH_Msk (0x01 << SYS_RSTCR_NORFLASH_Pos)
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#define SYS_RSTCR_SRAM_Pos 6 //д1<D0B4><31>SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>θ<EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_SRAM_Msk (0x01 << SYS_RSTCR_SRAM_Pos)
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#define SYS_RSTCR_SDRAM_Pos 7 //д1<D0B4><31>SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>θ<EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_SDRAM_Msk (0x01 << SYS_RSTCR_SDRAM_Pos)
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#define SYS_RSTCR_SDIO_Pos 8 //д1<D0B4><31>SDIO<49><4F><EFBFBD><EFBFBD>һ<EFBFBD>θ<EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_SDIO_Msk (0x01 << SYS_RSTCR_SDIO_Pos)
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#define SYS_RSTCR_LCD_Pos 9 //д1<D0B4><31>LCD<43><44><EFBFBD><EFBFBD>һ<EFBFBD>θ<EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_LCD_Msk (0x01 << SYS_RSTCR_LCD_Pos)
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#define SYS_RSTCR_CAN_Pos 10 //д1<D0B4><31>CAN<41><4E><EFBFBD><EFBFBD>һ<EFBFBD>θ<EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
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#define SYS_RSTCR_CAN_Msk (0x01 << SYS_RSTCR_CAN_Pos)
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#define SYS_RSTSR_POR_Pos 0 //1 <20><><EFBFBD>ֹ<EFBFBD>POR<4F><52>λ<EFBFBD><CEBB>д1<D0B4><31><EFBFBD><EFBFBD>
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#define SYS_RSTSR_POR_Msk (0x01 << SYS_RSTSR_POR_Pos)
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#define SYS_RSTSR_BOD_Pos 1 //1 <20><><EFBFBD>ֹ<EFBFBD>BOD<4F><44>λ<EFBFBD><CEBB>д1<D0B4><31><EFBFBD><EFBFBD>
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#define SYS_RSTSR_BOD_Msk (0x01 << SYS_RSTSR_BOD_Pos)
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#define SYS_RSTSR_PIN_Pos 2 //1 <20><><EFBFBD>ֹ<EFBFBD><D6B9>ⲿ<EFBFBD><E2B2BF><EFBFBD>Ÿ<EFBFBD>λ<EFBFBD><CEBB>д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define SYS_RSTSR_PIN_Msk (0x01 << SYS_RSTSR_PIN_Pos)
|
||
#define SYS_RSTSR_WDT_Pos 3 //1 <20><><EFBFBD>ֹ<EFBFBD>WDT<44><54>λ<EFBFBD><CEBB>д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define SYS_RSTSR_WDT_Msk (0x01 << SYS_RSTSR_WDT_Pos)
|
||
#define SYS_RSTSR_SWRST_Pos 4 //Software Reset, 1 <20><><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define SYS_RSTSR_SWRST_Msk (0x01 << SYS_RSTSR_SWRST_Pos)
|
||
|
||
#define SYS_LRCCR_OFF_Pos 0 //Low Speed RC Off
|
||
#define SYS_LRCCR_OFF_Msk (0x01 << SYS_LRCCR_OFF_Pos)
|
||
|
||
#define SYS_LRCTRIM0_R_Pos 0 //LRC<52>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD>λ
|
||
#define SYS_LRCTRIM0_R_Msk (0x7FFF << SYS_LRCTRIM0_R_Pos)
|
||
#define SYS_LRCTRIM0_M_Pos 15 //LRC<52>е<EFBFBD><D0B5><EFBFBD><EFBFBD><EFBFBD>λ
|
||
#define SYS_LRCTRIM0_M_Msk (0x3F << SYS_LRCTRIM2_M_Pos)
|
||
#define SYS_LRCTRIM0_F_Pos 21 //LRCϸ<43><CFB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
|
||
#define SYS_LRCTRIM0_F_Msk (0x7FF << SYS_LRCTRIM0_F_Pos)
|
||
|
||
#define SYS_LRCTRIM1_U_Pos 0 //LRC U<><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
|
||
#define SYS_LRCTRIM1_U_Msk (0x7FFF << SYS_LRCTRIM1_U_Pos)
|
||
|
||
|
||
#define SYS_HRCCR_DBL_Pos 0 //Double Frequency 0 20MHz 1 40MHz
|
||
#define SYS_HRCCR_DBL_Msk (0x01 << SYS_HRCCR_DBL_Pos)
|
||
#define SYS_HRCCR_OFF_Pos 1 //High speed RC Off
|
||
#define SYS_HRCCR_OFF_Msk (0x01 << SYS_HRCCR_OFF_Pos)
|
||
|
||
#define SYS_XTALCR_EN_Pos 0
|
||
#define SYS_XTALCR_EN_Msk (0x01 << SYS_XTALCR_EN_Pos)
|
||
|
||
#define SYS_PLLCR_OUTEN_Pos 0 //ֻ<><D6BB>LOCK<43><4B><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define SYS_PLLCR_OUTEN_Msk (0x01 << SYS_PLLCR_OUTEN_Pos)
|
||
#define SYS_PLLCR_INSEL_Pos 1 //0 XTAL 1 HRC
|
||
#define SYS_PLLCR_INSEL_Msk (0x01 << SYS_PLLCR_INSEL_Pos)
|
||
#define SYS_PLLCR_OFF_Pos 2
|
||
#define SYS_PLLCR_OFF_Msk (0x01 << SYS_PLLCR_OFF_Pos)
|
||
|
||
#define SYS_PLLDIV_FBDIV_Pos 0 //PLL FeedBack<63><6B>Ƶ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
|
||
//VCO<43><4F><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> = PLL<4C><4C><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1> / INDIV * 4 * FBDIV
|
||
//PLL<4C><4C><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> = PLL<4C><4C><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1> / INDIV * 4 * FBDIV / OUTDIV = VCO<43><4F><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> / OUTDIV
|
||
#define SYS_PLLDIV_FBDIV_Msk (0x1FF << SYS_PLLDIV_FBDIV_Pos)
|
||
#define SYS_PLLDIV_ADDIV_Pos 9 //ADCʱ<43>ӻ<EFBFBD><D3BB><EFBFBD><EFBFBD><EFBFBD>VCO<43><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ʱ<EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD>ADDIV<49><56>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ΪADC<44><43>ת<EFBFBD><D7AA>ʱ<EFBFBD><CAB1>
|
||
#define SYS_PLLDIV_ADDIV_Msk (0x1F << SYS_PLLDIV_ADDIV_Pos)
|
||
#define SYS_PLLDIV_ADVCO_Pos 14 //0 VCO<43><4F><EFBFBD><EFBFBD>16<31><36>Ƶ<EFBFBD><C6B5>ΪADCʱ<43>ӻ<EFBFBD> 1 VCO<43><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>32<33><32>Ƶ<EFBFBD><C6B5>ΪADCʱ<43>ӻ<EFBFBD> 2 VCO<43><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>64<36><34>Ƶ<EFBFBD><C6B5>ΪADCʱ<43>ӻ<EFBFBD>
|
||
#define SYS_PLLDIV_ADVCO_Msk (0x03 << SYS_PLLDIV_ADVCO_Pos)
|
||
#define SYS_PLLDIV_INDIV_Pos 16 //PLL <20><><EFBFBD><EFBFBD>Դʱ<D4B4>ӷ<EFBFBD>Ƶ
|
||
#define SYS_PLLDIV_INDIV_Msk (0x1F << SYS_PLLDIV_INDIV_Pos)
|
||
#define SYS_PLLDIV_OUTDIV_Pos 24 //PLL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5>0 8<><38>Ƶ 1 4<><34>Ƶ 0 2<><32>Ƶ
|
||
#define SYS_PLLDIV_OUTDIV_Msk (0x03 << SYS_PLLDIV_OUTDIV_Pos)
|
||
|
||
#define SYS_PLLSET_LPFBW_Pos 0 //PLL Low Pass Filter Bandwidth
|
||
#define SYS_PLLSET_LPFBW_Msk (0x0F << SYS_PLLSET_LPFBW_Pos)
|
||
#define SYS_PLLSET_BIASADJ_Pos 4 //PLL Current Bias Adjustment
|
||
#define SYS_PLLSET_BIASADJ_Msk (0x03 << SYS_PLLSET_BIASADJ_Pos)
|
||
#define SYS_PLLSET_REFVSEL_Pos 6 //PLL Reference Voltage Select
|
||
#define SYS_PLLSET_REFVSEL_Msk (0x03 << SYS_PLLSET_REFVSEL_Pos)
|
||
#define SYS_PLLSET_CHPADJL_Pos 8 //PLL charge pump LSB current Adjustment
|
||
#define SYS_PLLSET_CHPADJL_Msk (0x07 << SYS_PLLSET_CHPADJL_Pos)
|
||
#define SYS_PLLSET_CHPADJM_Pos 11 //PLL charge pump MSB current Adjustment
|
||
#define SYS_PLLSET_CHPADJM_Msk (0x03 << SYS_PLLSET_CHPADJM_Pos)
|
||
|
||
#define SYS_BODIE_2V2_Pos 1 //BOD 2.2V<EFBFBD>ȼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʹ<EFBFBD><EFBFBD>
|
||
#define SYS_BODIE_2V2_Msk (0x01 << SYS_BODIE_2V2_Pos)
|
||
|
||
#define SYS_BODIF_2V2_Pos 1 //BOD 2.2V<EFBFBD>ȼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>״̬<EFBFBD><EFBFBD>д1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define SYS_BODIF_2V2_Msk (0x01 << SYS_BODIF_2V2_Pos)
|
||
|
||
#define SYS_ADC1IN7_SEL_Pos 0 //ADC1ģ<31><C4A3>ģ<EFBFBD><C4A3>ͨ<EFBFBD><CDA8>7<EFBFBD><37>1 <20>¶ȴ<C2B6><C8B4><EFBFBD><EFBFBD><EFBFBD> 2 <20><><EFBFBD>ص<EFBFBD>ѹ 3 RTC<54><43>Դ<EFBFBD><D4B4>BG 4 <20><><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>BG 5 PDM33
|
||
#define SYS_ADC1IN7_SEL_Msk (0x0F << SYS_ADC1IN7_SEL_Pos)
|
||
#define SYS_ADC1IN7_IOON_Pos 4 //ADC1ģ<31><C4A3>ģ<EFBFBD><C4A3>ͨ<EFBFBD><CDA8>7<EFBFBD><37><EFBFBD><EFBFBD>IO<49><4F><EFBFBD><EFBFBD>
|
||
#define SYS_ADC1IN7_IOON_Msk (0x01 << SYS_ADC1IN7_IOON_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t PORTA_SEL; //<2F><>PORTA_SEL[2n+2:2n]<5D><><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>PORTA.PINn<4E><6E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ó<EFBFBD>GPIO<49><4F>ģ<EFBFBD>⡢<EFBFBD><E2A1A2><EFBFBD>ֵȹ<D6B5><C8B9><EFBFBD>
|
||
//<2F><><EFBFBD><EFBFBD>ֵΪPORTA_PINn_FUNMUXʱ<58><CAB1>PORTA.PINn<4E><6E><EFBFBD>ſ<EFBFBD>ͨ<EFBFBD><CDA8>PORTA_MUX<55>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
__IO uint32_t PORTB_SEL;
|
||
|
||
__IO uint32_t PORTC_SEL;
|
||
|
||
uint32_t RESERVED[5];
|
||
|
||
__IO uint32_t PORTM_SEL0;
|
||
|
||
__IO uint32_t PORTM_SEL1;
|
||
|
||
uint32_t RESERVED2[2];
|
||
|
||
__IO uint32_t PORTN_SEL0;
|
||
|
||
__IO uint32_t PORTN_SEL1;
|
||
|
||
uint32_t RESERVED3[2];
|
||
|
||
__IO uint32_t PORTP_SEL0;
|
||
|
||
__IO uint32_t PORTP_SEL1;
|
||
|
||
uint32_t RESERVED4[46];
|
||
|
||
__IO uint32_t PORTA_MUX0;
|
||
|
||
__IO uint32_t PORTA_MUX1;
|
||
|
||
uint32_t RESERVED5[2];
|
||
|
||
__IO uint32_t PORTB_MUX0;
|
||
|
||
__IO uint32_t PORTB_MUX1;
|
||
|
||
uint32_t RESERVED6[2];
|
||
|
||
__IO uint32_t PORTC_MUX0;
|
||
|
||
__IO uint32_t PORTC_MUX1;
|
||
|
||
uint32_t RESERVED7[14];
|
||
|
||
__IO uint32_t PORTM_MUX0;
|
||
|
||
__IO uint32_t PORTM_MUX1;
|
||
|
||
__IO uint32_t PORTM_MUX2;
|
||
|
||
__IO uint32_t PORTM_MUX3;
|
||
|
||
__IO uint32_t PORTN_MUX0;
|
||
|
||
__IO uint32_t PORTN_MUX1;
|
||
|
||
__IO uint32_t PORTN_MUX2;
|
||
|
||
uint32_t RESERVED8;
|
||
|
||
__IO uint32_t PORTP_MUX0;
|
||
|
||
__IO uint32_t PORTP_MUX1;
|
||
|
||
__IO uint32_t PORTP_MUX2;
|
||
|
||
__IO uint32_t PORTP_MUX3;
|
||
|
||
uint32_t RESERVED9[28];
|
||
|
||
__IO uint32_t PORTA_PULLU; //<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
|
||
|
||
uint32_t RESERVED10[3];
|
||
|
||
__IO uint32_t PORTC_PULLU;
|
||
|
||
uint32_t RESERVED11[3];
|
||
|
||
__IO uint32_t PORTM_PULLU;
|
||
|
||
uint32_t RESERVED12[3];
|
||
|
||
__IO uint32_t PORTP_PULLU;
|
||
|
||
uint32_t RESERVED13[51];
|
||
|
||
__IO uint32_t PORTB_PULLD; //<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
|
||
|
||
uint32_t RESERVED14[3];
|
||
|
||
__IO uint32_t PORTD_PULLD;
|
||
|
||
uint32_t RESERVED15[3];
|
||
|
||
__IO uint32_t PORTN_PULLD;
|
||
|
||
uint32_t RESERVED16[135];
|
||
|
||
__IO uint32_t PORTM_DRIVS; //<2F><><EFBFBD><EFBFBD>ǿ<EFBFBD><C7BF>
|
||
|
||
uint32_t RESERVED17[3];
|
||
|
||
__IO uint32_t PORTN_DRIVS;
|
||
|
||
uint32_t RESERVED18[3];
|
||
|
||
__IO uint32_t PORTP_DRIVS;
|
||
|
||
uint32_t RESERVED19[39];
|
||
|
||
__IO uint32_t PORTA_INEN; //<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
|
||
|
||
uint32_t RESERVED20[3];
|
||
|
||
__IO uint32_t PORTB_INEN;
|
||
|
||
uint32_t RESERVED21[3];
|
||
|
||
__IO uint32_t PORTC_INEN;
|
||
|
||
uint32_t RESERVED22[7];
|
||
|
||
__IO uint32_t PORTM_INEN;
|
||
|
||
uint32_t RESERVED23[3];
|
||
|
||
__IO uint32_t PORTN_INEN;
|
||
|
||
uint32_t RESERVED24[3];
|
||
|
||
__IO uint32_t PORTP_INEN;
|
||
} PORT_TypeDef;
|
||
|
||
|
||
#define PORT_PORTA_PULLU_PIN0_Pos 0
|
||
#define PORT_PORTA_PULLU_PIN0_Msk (0x01 << PORT_PORTA_PULLU_PIN0_Pos)
|
||
#define PORT_PORTA_PULLU_PIN1_Pos 1
|
||
#define PORT_PORTA_PULLU_PIN1_Msk (0x01 << PORT_PORTA_PULLU_PIN1_Pos)
|
||
#define PORT_PORTA_PULLU_PIN2_Pos 2
|
||
#define PORT_PORTA_PULLU_PIN2_Msk (0x01 << PORT_PORTA_PULLU_PIN2_Pos)
|
||
#define PORT_PORTA_PULLU_PIN3_Pos 3
|
||
#define PORT_PORTA_PULLU_PIN3_Msk (0x01 << PORT_PORTA_PULLU_PIN3_Pos)
|
||
#define PORT_PORTA_PULLU_PIN4_Pos 4
|
||
#define PORT_PORTA_PULLU_PIN4_Msk (0x01 << PORT_PORTA_PULLU_PIN4_Pos)
|
||
#define PORT_PORTA_PULLU_PIN5_Pos 5
|
||
#define PORT_PORTA_PULLU_PIN5_Msk (0x01 << PORT_PORTA_PULLU_PIN5_Pos)
|
||
#define PORT_PORTA_PULLU_PIN6_Pos 6
|
||
#define PORT_PORTA_PULLU_PIN6_Msk (0x01 << PORT_PORTA_PULLU_PIN6_Pos)
|
||
#define PORT_PORTA_PULLU_PIN7_Pos 7
|
||
#define PORT_PORTA_PULLU_PIN7_Msk (0x01 << PORT_PORTA_PULLU_PIN7_Pos)
|
||
#define PORT_PORTA_PULLU_PIN8_Pos 8
|
||
#define PORT_PORTA_PULLU_PIN8_Msk (0x01 << PORT_PORTA_PULLU_PIN8_Pos)
|
||
#define PORT_PORTA_PULLU_PIN9_Pos 9
|
||
#define PORT_PORTA_PULLU_PIN9_Msk (0x01 << PORT_PORTA_PULLU_PIN9_Pos)
|
||
#define PORT_PORTA_PULLU_PIN10_Pos 10
|
||
#define PORT_PORTA_PULLU_PIN10_Msk (0x01 << PORT_PORTA_PULLU_PIN10_Pos)
|
||
#define PORT_PORTA_PULLU_PIN11_Pos 11
|
||
#define PORT_PORTA_PULLU_PIN11_Msk (0x01 << PORT_PORTA_PULLU_PIN11_Pos)
|
||
#define PORT_PORTA_PULLU_PIN12_Pos 12
|
||
#define PORT_PORTA_PULLU_PIN12_Msk (0x01 << PORT_PORTA_PULLU_PIN12_Pos)
|
||
#define PORT_PORTA_PULLU_PIN13_Pos 13
|
||
#define PORT_PORTA_PULLU_PIN13_Msk (0x01 << PORT_PORTA_PULLU_PIN13_Pos)
|
||
#define PORT_PORTA_PULLU_PIN14_Pos 14
|
||
#define PORT_PORTA_PULLU_PIN14_Msk (0x01 << PORT_PORTA_PULLU_PIN14_Pos)
|
||
#define PORT_PORTA_PULLU_PIN15_Pos 15
|
||
#define PORT_PORTA_PULLU_PIN15_Msk (0x01 << PORT_PORTA_PULLU_PIN15_Pos)
|
||
|
||
#define PORT_PORTC_PULLU_PIN0_Pos 0
|
||
#define PORT_PORTC_PULLU_PIN0_Msk (0x01 << PORT_PORTC_PULLU_PIN0_Pos)
|
||
#define PORT_PORTC_PULLU_PIN1_Pos 1
|
||
#define PORT_PORTC_PULLU_PIN1_Msk (0x01 << PORT_PORTC_PULLU_PIN1_Pos)
|
||
#define PORT_PORTC_PULLU_PIN2_Pos 2
|
||
#define PORT_PORTC_PULLU_PIN2_Msk (0x01 << PORT_PORTC_PULLU_PIN2_Pos)
|
||
#define PORT_PORTC_PULLU_PIN3_Pos 3
|
||
#define PORT_PORTC_PULLU_PIN3_Msk (0x01 << PORT_PORTC_PULLU_PIN3_Pos)
|
||
#define PORT_PORTC_PULLU_PIN4_Pos 4
|
||
#define PORT_PORTC_PULLU_PIN4_Msk (0x01 << PORT_PORTC_PULLU_PIN4_Pos)
|
||
#define PORT_PORTC_PULLU_PIN5_Pos 5
|
||
#define PORT_PORTC_PULLU_PIN5_Msk (0x01 << PORT_PORTC_PULLU_PIN5_Pos)
|
||
#define PORT_PORTC_PULLU_PIN6_Pos 6
|
||
#define PORT_PORTC_PULLU_PIN6_Msk (0x01 << PORT_PORTC_PULLU_PIN6_Pos)
|
||
#define PORT_PORTC_PULLU_PIN7_Pos 7
|
||
#define PORT_PORTC_PULLU_PIN7_Msk (0x01 << PORT_PORTC_PULLU_PIN7_Pos)
|
||
#define PORT_PORTC_PULLU_PIN8_Pos 8
|
||
#define PORT_PORTC_PULLU_PIN8_Msk (0x01 << PORT_PORTC_PULLU_PIN8_Pos)
|
||
#define PORT_PORTC_PULLU_PIN9_Pos 9
|
||
#define PORT_PORTC_PULLU_PIN9_Msk (0x01 << PORT_PORTC_PULLU_PIN9_Pos)
|
||
#define PORT_PORTC_PULLU_PIN10_Pos 10
|
||
#define PORT_PORTC_PULLU_PIN10_Msk (0x01 << PORT_PORTC_PULLU_PIN10_Pos)
|
||
#define PORT_PORTC_PULLU_PIN11_Pos 11
|
||
#define PORT_PORTC_PULLU_PIN11_Msk (0x01 << PORT_PORTC_PULLU_PIN11_Pos)
|
||
#define PORT_PORTC_PULLU_PIN12_Pos 12
|
||
#define PORT_PORTC_PULLU_PIN12_Msk (0x01 << PORT_PORTC_PULLU_PIN12_Pos)
|
||
#define PORT_PORTC_PULLU_PIN13_Pos 13
|
||
#define PORT_PORTC_PULLU_PIN13_Msk (0x01 << PORT_PORTC_PULLU_PIN13_Pos)
|
||
#define PORT_PORTC_PULLU_PIN14_Pos 14
|
||
#define PORT_PORTC_PULLU_PIN14_Msk (0x01 << PORT_PORTC_PULLU_PIN14_Pos)
|
||
#define PORT_PORTC_PULLU_PIN15_Pos 15
|
||
#define PORT_PORTC_PULLU_PIN15_Msk (0x01 << PORT_PORTC_PULLU_PIN15_Pos)
|
||
|
||
#define PORT_PORTM_PULLU_PIN0_Pos 0
|
||
#define PORT_PORTM_PULLU_PIN0_Msk (0x01 << PORT_PORTM_PULLU_PIN0_Pos)
|
||
#define PORT_PORTM_PULLU_PIN1_Pos 1
|
||
#define PORT_PORTM_PULLU_PIN1_Msk (0x01 << PORT_PORTM_PULLU_PIN1_Pos)
|
||
#define PORT_PORTM_PULLU_PIN2_Pos 2
|
||
#define PORT_PORTM_PULLU_PIN2_Msk (0x01 << PORT_PORTM_PULLU_PIN2_Pos)
|
||
#define PORT_PORTM_PULLU_PIN3_Pos 3
|
||
#define PORT_PORTM_PULLU_PIN3_Msk (0x01 << PORT_PORTM_PULLU_PIN3_Pos)
|
||
#define PORT_PORTM_PULLU_PIN4_Pos 4
|
||
#define PORT_PORTM_PULLU_PIN4_Msk (0x01 << PORT_PORTM_PULLU_PIN4_Pos)
|
||
#define PORT_PORTM_PULLU_PIN5_Pos 5
|
||
#define PORT_PORTM_PULLU_PIN5_Msk (0x01 << PORT_PORTM_PULLU_PIN5_Pos)
|
||
#define PORT_PORTM_PULLU_PIN6_Pos 6
|
||
#define PORT_PORTM_PULLU_PIN6_Msk (0x01 << PORT_PORTM_PULLU_PIN6_Pos)
|
||
#define PORT_PORTM_PULLU_PIN7_Pos 7
|
||
#define PORT_PORTM_PULLU_PIN7_Msk (0x01 << PORT_PORTM_PULLU_PIN7_Pos)
|
||
#define PORT_PORTM_PULLU_PIN8_Pos 8
|
||
#define PORT_PORTM_PULLU_PIN8_Msk (0x01 << PORT_PORTM_PULLU_PIN8_Pos)
|
||
#define PORT_PORTM_PULLU_PIN9_Pos 9
|
||
#define PORT_PORTM_PULLU_PIN9_Msk (0x01 << PORT_PORTM_PULLU_PIN9_Pos)
|
||
#define PORT_PORTM_PULLU_PIN10_Pos 10
|
||
#define PORT_PORTM_PULLU_PIN10_Msk (0x01 << PORT_PORTM_PULLU_PIN10_Pos)
|
||
#define PORT_PORTM_PULLU_PIN11_Pos 11
|
||
#define PORT_PORTM_PULLU_PIN11_Msk (0x01 << PORT_PORTM_PULLU_PIN11_Pos)
|
||
#define PORT_PORTM_PULLU_PIN12_Pos 12
|
||
#define PORT_PORTM_PULLU_PIN12_Msk (0x01 << PORT_PORTM_PULLU_PIN12_Pos)
|
||
#define PORT_PORTM_PULLU_PIN13_Pos 13
|
||
#define PORT_PORTM_PULLU_PIN13_Msk (0x01 << PORT_PORTM_PULLU_PIN13_Pos)
|
||
#define PORT_PORTM_PULLU_PIN14_Pos 14
|
||
#define PORT_PORTM_PULLU_PIN14_Msk (0x01 << PORT_PORTM_PULLU_PIN14_Pos)
|
||
#define PORT_PORTM_PULLU_PIN15_Pos 15
|
||
#define PORT_PORTM_PULLU_PIN15_Msk (0x01 << PORT_PORTM_PULLU_PIN15_Pos)
|
||
#define PORT_PORTM_PULLU_PIN16_Pos 16
|
||
#define PORT_PORTM_PULLU_PIN16_Msk (0x01 << PORT_PORTM_PULLU_PIN16_Pos)
|
||
#define PORT_PORTM_PULLU_PIN17_Pos 17
|
||
#define PORT_PORTM_PULLU_PIN17_Msk (0x01 << PORT_PORTM_PULLU_PIN17_Pos)
|
||
#define PORT_PORTM_PULLU_PIN18_Pos 18
|
||
#define PORT_PORTM_PULLU_PIN18_Msk (0x01 << PORT_PORTM_PULLU_PIN18_Pos)
|
||
#define PORT_PORTM_PULLU_PIN19_Pos 19
|
||
#define PORT_PORTM_PULLU_PIN19_Msk (0x01 << PORT_PORTM_PULLU_PIN19_Pos)
|
||
#define PORT_PORTM_PULLU_PIN20_Pos 20
|
||
#define PORT_PORTM_PULLU_PIN20_Msk (0x01 << PORT_PORTM_PULLU_PIN20_Pos)
|
||
#define PORT_PORTM_PULLU_PIN21_Pos 21
|
||
#define PORT_PORTM_PULLU_PIN21_Msk (0x01 << PORT_PORTM_PULLU_PIN21_Pos)
|
||
#define PORT_PORTM_PULLU_PIN22_Pos 22
|
||
#define PORT_PORTM_PULLU_PIN22_Msk (0x01 << PORT_PORTM_PULLU_PIN22_Pos)
|
||
#define PORT_PORTM_PULLU_PIN23_Pos 23
|
||
#define PORT_PORTM_PULLU_PIN23_Msk (0x01 << PORT_PORTM_PULLU_PIN23_Pos)
|
||
|
||
#define PORT_PORTP_PULLU_PIN0_Pos 0
|
||
#define PORT_PORTP_PULLU_PIN0_Msk (0x01 << PORT_PORTP_PULLU_PIN0_Pos)
|
||
#define PORT_PORTP_PULLU_PIN1_Pos 1
|
||
#define PORT_PORTP_PULLU_PIN1_Msk (0x01 << PORT_PORTP_PULLU_PIN1_Pos)
|
||
#define PORT_PORTP_PULLU_PIN2_Pos 2
|
||
#define PORT_PORTP_PULLU_PIN2_Msk (0x01 << PORT_PORTP_PULLU_PIN2_Pos)
|
||
#define PORT_PORTP_PULLU_PIN3_Pos 3
|
||
#define PORT_PORTP_PULLU_PIN3_Msk (0x01 << PORT_PORTP_PULLU_PIN3_Pos)
|
||
#define PORT_PORTP_PULLU_PIN4_Pos 4
|
||
#define PORT_PORTP_PULLU_PIN4_Msk (0x01 << PORT_PORTP_PULLU_PIN4_Pos)
|
||
#define PORT_PORTP_PULLU_PIN5_Pos 5
|
||
#define PORT_PORTP_PULLU_PIN5_Msk (0x01 << PORT_PORTP_PULLU_PIN5_Pos)
|
||
#define PORT_PORTP_PULLU_PIN6_Pos 6
|
||
#define PORT_PORTP_PULLU_PIN6_Msk (0x01 << PORT_PORTP_PULLU_PIN6_Pos)
|
||
#define PORT_PORTP_PULLU_PIN7_Pos 7
|
||
#define PORT_PORTP_PULLU_PIN7_Msk (0x01 << PORT_PORTP_PULLU_PIN7_Pos)
|
||
#define PORT_PORTP_PULLU_PIN8_Pos 8
|
||
#define PORT_PORTP_PULLU_PIN8_Msk (0x01 << PORT_PORTP_PULLU_PIN8_Pos)
|
||
#define PORT_PORTP_PULLU_PIN9_Pos 9
|
||
#define PORT_PORTP_PULLU_PIN9_Msk (0x01 << PORT_PORTP_PULLU_PIN9_Pos)
|
||
#define PORT_PORTP_PULLU_PIN10_Pos 10
|
||
#define PORT_PORTP_PULLU_PIN10_Msk (0x01 << PORT_PORTP_PULLU_PIN10_Pos)
|
||
#define PORT_PORTP_PULLU_PIN11_Pos 11
|
||
#define PORT_PORTP_PULLU_PIN11_Msk (0x01 << PORT_PORTP_PULLU_PIN11_Pos)
|
||
#define PORT_PORTP_PULLU_PIN12_Pos 12
|
||
#define PORT_PORTP_PULLU_PIN12_Msk (0x01 << PORT_PORTP_PULLU_PIN12_Pos)
|
||
#define PORT_PORTP_PULLU_PIN13_Pos 13
|
||
#define PORT_PORTP_PULLU_PIN13_Msk (0x01 << PORT_PORTP_PULLU_PIN13_Pos)
|
||
#define PORT_PORTP_PULLU_PIN14_Pos 14
|
||
#define PORT_PORTP_PULLU_PIN14_Msk (0x01 << PORT_PORTP_PULLU_PIN14_Pos)
|
||
#define PORT_PORTP_PULLU_PIN15_Pos 15
|
||
#define PORT_PORTP_PULLU_PIN15_Msk (0x01 << PORT_PORTP_PULLU_PIN15_Pos)
|
||
#define PORT_PORTP_PULLU_PIN16_Pos 16
|
||
#define PORT_PORTP_PULLU_PIN16_Msk (0x01 << PORT_PORTP_PULLU_PIN16_Pos)
|
||
#define PORT_PORTP_PULLU_PIN17_Pos 17
|
||
#define PORT_PORTP_PULLU_PIN17_Msk (0x01 << PORT_PORTP_PULLU_PIN17_Pos)
|
||
#define PORT_PORTP_PULLU_PIN18_Pos 18
|
||
#define PORT_PORTP_PULLU_PIN18_Msk (0x01 << PORT_PORTP_PULLU_PIN18_Pos)
|
||
#define PORT_PORTP_PULLU_PIN19_Pos 19
|
||
#define PORT_PORTP_PULLU_PIN19_Msk (0x01 << PORT_PORTP_PULLU_PIN19_Pos)
|
||
#define PORT_PORTP_PULLU_PIN20_Pos 20
|
||
#define PORT_PORTP_PULLU_PIN20_Msk (0x01 << PORT_PORTP_PULLU_PIN20_Pos)
|
||
#define PORT_PORTP_PULLU_PIN21_Pos 21
|
||
#define PORT_PORTP_PULLU_PIN21_Msk (0x01 << PORT_PORTP_PULLU_PIN21_Pos)
|
||
#define PORT_PORTP_PULLU_PIN22_Pos 22
|
||
#define PORT_PORTP_PULLU_PIN22_Msk (0x01 << PORT_PORTP_PULLU_PIN22_Pos)
|
||
#define PORT_PORTP_PULLU_PIN23_Pos 23
|
||
#define PORT_PORTP_PULLU_PIN23_Msk (0x01 << PORT_PORTP_PULLU_PIN23_Pos)
|
||
|
||
#define PORT_PORTB_PULLD_PIN0_Pos 0
|
||
#define PORT_PORTB_PULLD_PIN0_Msk (0x01 << PORT_PORTB_PULLD_PIN0_Pos)
|
||
#define PORT_PORTB_PULLD_PIN1_Pos 1
|
||
#define PORT_PORTB_PULLD_PIN1_Msk (0x01 << PORT_PORTB_PULLD_PIN1_Pos)
|
||
#define PORT_PORTB_PULLD_PIN2_Pos 2
|
||
#define PORT_PORTB_PULLD_PIN2_Msk (0x01 << PORT_PORTB_PULLD_PIN2_Pos)
|
||
#define PORT_PORTB_PULLD_PIN3_Pos 3
|
||
#define PORT_PORTB_PULLD_PIN3_Msk (0x01 << PORT_PORTB_PULLD_PIN3_Pos)
|
||
#define PORT_PORTB_PULLD_PIN4_Pos 4
|
||
#define PORT_PORTB_PULLD_PIN4_Msk (0x01 << PORT_PORTB_PULLD_PIN4_Pos)
|
||
#define PORT_PORTB_PULLD_PIN5_Pos 5
|
||
#define PORT_PORTB_PULLD_PIN5_Msk (0x01 << PORT_PORTB_PULLD_PIN5_Pos)
|
||
#define PORT_PORTB_PULLD_PIN6_Pos 6
|
||
#define PORT_PORTB_PULLD_PIN6_Msk (0x01 << PORT_PORTB_PULLD_PIN6_Pos)
|
||
#define PORT_PORTB_PULLD_PIN7_Pos 7
|
||
#define PORT_PORTB_PULLD_PIN7_Msk (0x01 << PORT_PORTB_PULLD_PIN7_Pos)
|
||
#define PORT_PORTB_PULLD_PIN8_Pos 8
|
||
#define PORT_PORTB_PULLD_PIN8_Msk (0x01 << PORT_PORTB_PULLD_PIN8_Pos)
|
||
#define PORT_PORTB_PULLD_PIN9_Pos 9
|
||
#define PORT_PORTB_PULLD_PIN9_Msk (0x01 << PORT_PORTB_PULLD_PIN9_Pos)
|
||
#define PORT_PORTB_PULLD_PIN10_Pos 10
|
||
#define PORT_PORTB_PULLD_PIN10_Msk (0x01 << PORT_PORTB_PULLD_PIN10_Pos)
|
||
#define PORT_PORTB_PULLD_PIN11_Pos 11
|
||
#define PORT_PORTB_PULLD_PIN11_Msk (0x01 << PORT_PORTB_PULLD_PIN11_Pos)
|
||
#define PORT_PORTB_PULLD_PIN12_Pos 12
|
||
#define PORT_PORTB_PULLD_PIN12_Msk (0x01 << PORT_PORTB_PULLD_PIN12_Pos)
|
||
#define PORT_PORTB_PULLD_PIN13_Pos 13
|
||
#define PORT_PORTB_PULLD_PIN13_Msk (0x01 << PORT_PORTB_PULLD_PIN13_Pos)
|
||
#define PORT_PORTB_PULLD_PIN14_Pos 14
|
||
#define PORT_PORTB_PULLD_PIN14_Msk (0x01 << PORT_PORTB_PULLD_PIN14_Pos)
|
||
#define PORT_PORTB_PULLD_PIN15_Pos 15
|
||
#define PORT_PORTB_PULLD_PIN15_Msk (0x01 << PORT_PORTB_PULLD_PIN15_Pos)
|
||
|
||
#define PORT_PORTN_PULLD_PIN0_Pos 0
|
||
#define PORT_PORTN_PULLD_PIN0_Msk (0x01 << PORT_PORTN_PULLD_PIN0_Pos)
|
||
#define PORT_PORTN_PULLD_PIN1_Pos 1
|
||
#define PORT_PORTN_PULLD_PIN1_Msk (0x01 << PORT_PORTN_PULLD_PIN1_Pos)
|
||
#define PORT_PORTN_PULLD_PIN2_Pos 2
|
||
#define PORT_PORTN_PULLD_PIN2_Msk (0x01 << PORT_PORTN_PULLD_PIN2_Pos)
|
||
#define PORT_PORTN_PULLD_PIN3_Pos 3
|
||
#define PORT_PORTN_PULLD_PIN3_Msk (0x01 << PORT_PORTN_PULLD_PIN3_Pos)
|
||
#define PORT_PORTN_PULLD_PIN4_Pos 4
|
||
#define PORT_PORTN_PULLD_PIN4_Msk (0x01 << PORT_PORTN_PULLD_PIN4_Pos)
|
||
#define PORT_PORTN_PULLD_PIN5_Pos 5
|
||
#define PORT_PORTN_PULLD_PIN5_Msk (0x01 << PORT_PORTN_PULLD_PIN5_Pos)
|
||
#define PORT_PORTN_PULLD_PIN6_Pos 6
|
||
#define PORT_PORTN_PULLD_PIN6_Msk (0x01 << PORT_PORTN_PULLD_PIN6_Pos)
|
||
#define PORT_PORTN_PULLD_PIN7_Pos 7
|
||
#define PORT_PORTN_PULLD_PIN7_Msk (0x01 << PORT_PORTN_PULLD_PIN7_Pos)
|
||
#define PORT_PORTN_PULLD_PIN8_Pos 8
|
||
#define PORT_PORTN_PULLD_PIN8_Msk (0x01 << PORT_PORTN_PULLD_PIN8_Pos)
|
||
#define PORT_PORTN_PULLD_PIN9_Pos 9
|
||
#define PORT_PORTN_PULLD_PIN9_Msk (0x01 << PORT_PORTN_PULLD_PIN9_Pos)
|
||
#define PORT_PORTN_PULLD_PIN10_Pos 10
|
||
#define PORT_PORTN_PULLD_PIN10_Msk (0x01 << PORT_PORTN_PULLD_PIN10_Pos)
|
||
#define PORT_PORTN_PULLD_PIN11_Pos 11
|
||
#define PORT_PORTN_PULLD_PIN11_Msk (0x01 << PORT_PORTN_PULLD_PIN11_Pos)
|
||
#define PORT_PORTN_PULLD_PIN12_Pos 12
|
||
#define PORT_PORTN_PULLD_PIN12_Msk (0x01 << PORT_PORTN_PULLD_PIN12_Pos)
|
||
#define PORT_PORTN_PULLD_PIN13_Pos 13
|
||
#define PORT_PORTN_PULLD_PIN13_Msk (0x01 << PORT_PORTN_PULLD_PIN13_Pos)
|
||
#define PORT_PORTN_PULLD_PIN14_Pos 14
|
||
#define PORT_PORTN_PULLD_PIN14_Msk (0x01 << PORT_PORTN_PULLD_PIN14_Pos)
|
||
#define PORT_PORTN_PULLD_PIN15_Pos 15
|
||
#define PORT_PORTN_PULLD_PIN15_Msk (0x01 << PORT_PORTN_PULLD_PIN15_Pos)
|
||
#define PORT_PORTN_PULLD_PIN16_Pos 16
|
||
#define PORT_PORTN_PULLD_PIN16_Msk (0x01 << PORT_PORTN_PULLD_PIN16_Pos)
|
||
#define PORT_PORTN_PULLD_PIN17_Pos 17
|
||
#define PORT_PORTN_PULLD_PIN17_Msk (0x01 << PORT_PORTN_PULLD_PIN17_Pos)
|
||
#define PORT_PORTN_PULLD_PIN18_Pos 18
|
||
#define PORT_PORTN_PULLD_PIN18_Msk (0x01 << PORT_PORTN_PULLD_PIN18_Pos)
|
||
#define PORT_PORTN_PULLD_PIN19_Pos 19
|
||
#define PORT_PORTN_PULLD_PIN19_Msk (0x01 << PORT_PORTN_PULLD_PIN19_Pos)
|
||
#define PORT_PORTN_PULLD_PIN20_Pos 20
|
||
#define PORT_PORTN_PULLD_PIN20_Msk (0x01 << PORT_PORTN_PULLD_PIN20_Pos)
|
||
#define PORT_PORTN_PULLD_PIN21_Pos 21
|
||
#define PORT_PORTN_PULLD_PIN21_Msk (0x01 << PORT_PORTN_PULLD_PIN21_Pos)
|
||
#define PORT_PORTN_PULLD_PIN22_Pos 22
|
||
#define PORT_PORTN_PULLD_PIN22_Msk (0x01 << PORT_PORTN_PULLD_PIN22_Pos)
|
||
#define PORT_PORTN_PULLD_PIN23_Pos 23
|
||
#define PORT_PORTN_PULLD_PIN23_Msk (0x01 << PORT_PORTN_PULLD_PIN23_Pos)
|
||
|
||
#define PORT_PORTM_DRIVS_PIN0_Pos 0
|
||
#define PORT_PORTM_DRIVS_PIN0_Msk (0x01 << PORT_PORTM_DRIVS_PIN0_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN1_Pos 1
|
||
#define PORT_PORTM_DRIVS_PIN1_Msk (0x01 << PORT_PORTM_DRIVS_PIN1_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN2_Pos 2
|
||
#define PORT_PORTM_DRIVS_PIN2_Msk (0x01 << PORT_PORTM_DRIVS_PIN2_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN3_Pos 3
|
||
#define PORT_PORTM_DRIVS_PIN3_Msk (0x01 << PORT_PORTM_DRIVS_PIN3_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN4_Pos 4
|
||
#define PORT_PORTM_DRIVS_PIN4_Msk (0x01 << PORT_PORTM_DRIVS_PIN4_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN5_Pos 5
|
||
#define PORT_PORTM_DRIVS_PIN5_Msk (0x01 << PORT_PORTM_DRIVS_PIN5_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN6_Pos 6
|
||
#define PORT_PORTM_DRIVS_PIN6_Msk (0x01 << PORT_PORTM_DRIVS_PIN6_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN7_Pos 7
|
||
#define PORT_PORTM_DRIVS_PIN7_Msk (0x01 << PORT_PORTM_DRIVS_PIN7_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN8_Pos 8
|
||
#define PORT_PORTM_DRIVS_PIN8_Msk (0x01 << PORT_PORTM_DRIVS_PIN8_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN9_Pos 9
|
||
#define PORT_PORTM_DRIVS_PIN9_Msk (0x01 << PORT_PORTM_DRIVS_PIN9_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN10_Pos 10
|
||
#define PORT_PORTM_DRIVS_PIN10_Msk (0x01 << PORT_PORTM_DRIVS_PIN10_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN11_Pos 11
|
||
#define PORT_PORTM_DRIVS_PIN11_Msk (0x01 << PORT_PORTM_DRIVS_PIN11_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN12_Pos 12
|
||
#define PORT_PORTM_DRIVS_PIN12_Msk (0x01 << PORT_PORTM_DRIVS_PIN12_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN13_Pos 13
|
||
#define PORT_PORTM_DRIVS_PIN13_Msk (0x01 << PORT_PORTM_DRIVS_PIN13_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN14_Pos 14
|
||
#define PORT_PORTM_DRIVS_PIN14_Msk (0x01 << PORT_PORTM_DRIVS_PIN14_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN15_Pos 15
|
||
#define PORT_PORTM_DRIVS_PIN15_Msk (0x01 << PORT_PORTM_DRIVS_PIN15_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN16_Pos 16
|
||
#define PORT_PORTM_DRIVS_PIN16_Msk (0x01 << PORT_PORTM_DRIVS_PIN16_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN17_Pos 17
|
||
#define PORT_PORTM_DRIVS_PIN17_Msk (0x01 << PORT_PORTM_DRIVS_PIN17_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN18_Pos 18
|
||
#define PORT_PORTM_DRIVS_PIN18_Msk (0x01 << PORT_PORTM_DRIVS_PIN18_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN19_Pos 19
|
||
#define PORT_PORTM_DRIVS_PIN19_Msk (0x01 << PORT_PORTM_DRIVS_PIN19_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN20_Pos 20
|
||
#define PORT_PORTM_DRIVS_PIN20_Msk (0x01 << PORT_PORTM_DRIVS_PIN20_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN21_Pos 21
|
||
#define PORT_PORTM_DRIVS_PIN21_Msk (0x01 << PORT_PORTM_DRIVS_PIN21_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN22_Pos 22
|
||
#define PORT_PORTM_DRIVS_PIN22_Msk (0x01 << PORT_PORTM_DRIVS_PIN22_Pos)
|
||
#define PORT_PORTM_DRIVS_PIN23_Pos 23
|
||
#define PORT_PORTM_DRIVS_PIN23_Msk (0x01 << PORT_PORTM_DRIVS_PIN23_Pos)
|
||
|
||
#define PORT_PORTN_DRIVS_PIN0_Pos 0
|
||
#define PORT_PORTN_DRIVS_PIN0_Msk (0x01 << PORT_PORTN_DRIVS_PIN0_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN1_Pos 1
|
||
#define PORT_PORTN_DRIVS_PIN1_Msk (0x01 << PORT_PORTN_DRIVS_PIN1_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN2_Pos 2
|
||
#define PORT_PORTN_DRIVS_PIN2_Msk (0x01 << PORT_PORTN_DRIVS_PIN2_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN3_Pos 3
|
||
#define PORT_PORTN_DRIVS_PIN3_Msk (0x01 << PORT_PORTN_DRIVS_PIN3_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN4_Pos 4
|
||
#define PORT_PORTN_DRIVS_PIN4_Msk (0x01 << PORT_PORTN_DRIVS_PIN4_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN5_Pos 5
|
||
#define PORT_PORTN_DRIVS_PIN5_Msk (0x01 << PORT_PORTN_DRIVS_PIN5_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN6_Pos 6
|
||
#define PORT_PORTN_DRIVS_PIN6_Msk (0x01 << PORT_PORTN_DRIVS_PIN6_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN7_Pos 7
|
||
#define PORT_PORTN_DRIVS_PIN7_Msk (0x01 << PORT_PORTN_DRIVS_PIN7_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN8_Pos 8
|
||
#define PORT_PORTN_DRIVS_PIN8_Msk (0x01 << PORT_PORTN_DRIVS_PIN8_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN9_Pos 9
|
||
#define PORT_PORTN_DRIVS_PIN9_Msk (0x01 << PORT_PORTN_DRIVS_PIN9_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN10_Pos 10
|
||
#define PORT_PORTN_DRIVS_PIN10_Msk (0x01 << PORT_PORTN_DRIVS_PIN10_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN11_Pos 11
|
||
#define PORT_PORTN_DRIVS_PIN11_Msk (0x01 << PORT_PORTN_DRIVS_PIN11_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN12_Pos 12
|
||
#define PORT_PORTN_DRIVS_PIN12_Msk (0x01 << PORT_PORTN_DRIVS_PIN12_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN13_Pos 13
|
||
#define PORT_PORTN_DRIVS_PIN13_Msk (0x01 << PORT_PORTN_DRIVS_PIN13_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN14_Pos 14
|
||
#define PORT_PORTN_DRIVS_PIN14_Msk (0x01 << PORT_PORTN_DRIVS_PIN14_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN15_Pos 15
|
||
#define PORT_PORTN_DRIVS_PIN15_Msk (0x01 << PORT_PORTN_DRIVS_PIN15_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN16_Pos 16
|
||
#define PORT_PORTN_DRIVS_PIN16_Msk (0x01 << PORT_PORTN_DRIVS_PIN16_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN17_Pos 17
|
||
#define PORT_PORTN_DRIVS_PIN17_Msk (0x01 << PORT_PORTN_DRIVS_PIN17_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN18_Pos 18
|
||
#define PORT_PORTN_DRIVS_PIN18_Msk (0x01 << PORT_PORTN_DRIVS_PIN18_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN19_Pos 19
|
||
#define PORT_PORTN_DRIVS_PIN19_Msk (0x01 << PORT_PORTN_DRIVS_PIN19_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN20_Pos 20
|
||
#define PORT_PORTN_DRIVS_PIN20_Msk (0x01 << PORT_PORTN_DRIVS_PIN20_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN21_Pos 21
|
||
#define PORT_PORTN_DRIVS_PIN21_Msk (0x01 << PORT_PORTN_DRIVS_PIN21_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN22_Pos 22
|
||
#define PORT_PORTN_DRIVS_PIN22_Msk (0x01 << PORT_PORTN_DRIVS_PIN22_Pos)
|
||
#define PORT_PORTN_DRIVS_PIN23_Pos 23
|
||
#define PORT_PORTN_DRIVS_PIN23_Msk (0x01 << PORT_PORTN_DRIVS_PIN23_Pos)
|
||
|
||
#define PORT_PORTP_DRIVS_PIN0_Pos 0
|
||
#define PORT_PORTP_DRIVS_PIN0_Msk (0x01 << PORT_PORTP_DRIVS_PIN0_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN1_Pos 1
|
||
#define PORT_PORTP_DRIVS_PIN1_Msk (0x01 << PORT_PORTP_DRIVS_PIN1_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN2_Pos 2
|
||
#define PORT_PORTP_DRIVS_PIN2_Msk (0x01 << PORT_PORTP_DRIVS_PIN2_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN3_Pos 3
|
||
#define PORT_PORTP_DRIVS_PIN3_Msk (0x01 << PORT_PORTP_DRIVS_PIN3_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN4_Pos 4
|
||
#define PORT_PORTP_DRIVS_PIN4_Msk (0x01 << PORT_PORTP_DRIVS_PIN4_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN5_Pos 5
|
||
#define PORT_PORTP_DRIVS_PIN5_Msk (0x01 << PORT_PORTP_DRIVS_PIN5_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN6_Pos 6
|
||
#define PORT_PORTP_DRIVS_PIN6_Msk (0x01 << PORT_PORTP_DRIVS_PIN6_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN7_Pos 7
|
||
#define PORT_PORTP_DRIVS_PIN7_Msk (0x01 << PORT_PORTP_DRIVS_PIN7_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN8_Pos 8
|
||
#define PORT_PORTP_DRIVS_PIN8_Msk (0x01 << PORT_PORTP_DRIVS_PIN8_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN9_Pos 9
|
||
#define PORT_PORTP_DRIVS_PIN9_Msk (0x01 << PORT_PORTP_DRIVS_PIN9_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN10_Pos 10
|
||
#define PORT_PORTP_DRIVS_PIN10_Msk (0x01 << PORT_PORTP_DRIVS_PIN10_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN11_Pos 11
|
||
#define PORT_PORTP_DRIVS_PIN11_Msk (0x01 << PORT_PORTP_DRIVS_PIN11_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN12_Pos 12
|
||
#define PORT_PORTP_DRIVS_PIN12_Msk (0x01 << PORT_PORTP_DRIVS_PIN12_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN13_Pos 13
|
||
#define PORT_PORTP_DRIVS_PIN13_Msk (0x01 << PORT_PORTP_DRIVS_PIN13_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN14_Pos 14
|
||
#define PORT_PORTP_DRIVS_PIN14_Msk (0x01 << PORT_PORTP_DRIVS_PIN14_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN15_Pos 15
|
||
#define PORT_PORTP_DRIVS_PIN15_Msk (0x01 << PORT_PORTP_DRIVS_PIN15_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN16_Pos 16
|
||
#define PORT_PORTP_DRIVS_PIN16_Msk (0x01 << PORT_PORTP_DRIVS_PIN16_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN17_Pos 17
|
||
#define PORT_PORTP_DRIVS_PIN17_Msk (0x01 << PORT_PORTP_DRIVS_PIN17_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN18_Pos 18
|
||
#define PORT_PORTP_DRIVS_PIN18_Msk (0x01 << PORT_PORTP_DRIVS_PIN18_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN19_Pos 19
|
||
#define PORT_PORTP_DRIVS_PIN19_Msk (0x01 << PORT_PORTP_DRIVS_PIN19_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN20_Pos 20
|
||
#define PORT_PORTP_DRIVS_PIN20_Msk (0x01 << PORT_PORTP_DRIVS_PIN20_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN21_Pos 21
|
||
#define PORT_PORTP_DRIVS_PIN21_Msk (0x01 << PORT_PORTP_DRIVS_PIN21_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN22_Pos 22
|
||
#define PORT_PORTP_DRIVS_PIN22_Msk (0x01 << PORT_PORTP_DRIVS_PIN22_Pos)
|
||
#define PORT_PORTP_DRIVS_PIN23_Pos 23
|
||
#define PORT_PORTP_DRIVS_PIN23_Msk (0x01 << PORT_PORTP_DRIVS_PIN23_Pos)
|
||
|
||
#define PORT_PORTA_INEN_PIN0_Pos 0
|
||
#define PORT_PORTA_INEN_PIN0_Msk (0x01 << PORT_PORTA_INEN_PIN0_Pos)
|
||
#define PORT_PORTA_INEN_PIN1_Pos 1
|
||
#define PORT_PORTA_INEN_PIN1_Msk (0x01 << PORT_PORTA_INEN_PIN1_Pos)
|
||
#define PORT_PORTA_INEN_PIN2_Pos 2
|
||
#define PORT_PORTA_INEN_PIN2_Msk (0x01 << PORT_PORTA_INEN_PIN2_Pos)
|
||
#define PORT_PORTA_INEN_PIN3_Pos 3
|
||
#define PORT_PORTA_INEN_PIN3_Msk (0x01 << PORT_PORTA_INEN_PIN3_Pos)
|
||
#define PORT_PORTA_INEN_PIN4_Pos 4
|
||
#define PORT_PORTA_INEN_PIN4_Msk (0x01 << PORT_PORTA_INEN_PIN4_Pos)
|
||
#define PORT_PORTA_INEN_PIN5_Pos 5
|
||
#define PORT_PORTA_INEN_PIN5_Msk (0x01 << PORT_PORTA_INEN_PIN5_Pos)
|
||
#define PORT_PORTA_INEN_PIN6_Pos 6
|
||
#define PORT_PORTA_INEN_PIN6_Msk (0x01 << PORT_PORTA_INEN_PIN6_Pos)
|
||
#define PORT_PORTA_INEN_PIN7_Pos 7
|
||
#define PORT_PORTA_INEN_PIN7_Msk (0x01 << PORT_PORTA_INEN_PIN7_Pos)
|
||
#define PORT_PORTA_INEN_PIN8_Pos 8
|
||
#define PORT_PORTA_INEN_PIN8_Msk (0x01 << PORT_PORTA_INEN_PIN8_Pos)
|
||
#define PORT_PORTA_INEN_PIN9_Pos 9
|
||
#define PORT_PORTA_INEN_PIN9_Msk (0x01 << PORT_PORTA_INEN_PIN9_Pos)
|
||
#define PORT_PORTA_INEN_PIN10_Pos 10
|
||
#define PORT_PORTA_INEN_PIN10_Msk (0x01 << PORT_PORTA_INEN_PIN10_Pos)
|
||
#define PORT_PORTA_INEN_PIN11_Pos 11
|
||
#define PORT_PORTA_INEN_PIN11_Msk (0x01 << PORT_PORTA_INEN_PIN11_Pos)
|
||
#define PORT_PORTA_INEN_PIN12_Pos 12
|
||
#define PORT_PORTA_INEN_PIN12_Msk (0x01 << PORT_PORTA_INEN_PIN12_Pos)
|
||
#define PORT_PORTA_INEN_PIN13_Pos 13
|
||
#define PORT_PORTA_INEN_PIN13_Msk (0x01 << PORT_PORTA_INEN_PIN13_Pos)
|
||
#define PORT_PORTA_INEN_PIN14_Pos 14
|
||
#define PORT_PORTA_INEN_PIN14_Msk (0x01 << PORT_PORTA_INEN_PIN14_Pos)
|
||
#define PORT_PORTA_INEN_PIN15_Pos 15
|
||
#define PORT_PORTA_INEN_PIN15_Msk (0x01 << PORT_PORTA_INEN_PIN15_Pos)
|
||
|
||
#define PORT_PORTB_INEN_PIN0_Pos 0
|
||
#define PORT_PORTB_INEN_PIN0_Msk (0x01 << PORT_PORTB_INEN_PIN0_Pos)
|
||
#define PORT_PORTB_INEN_PIN1_Pos 1
|
||
#define PORT_PORTB_INEN_PIN1_Msk (0x01 << PORT_PORTB_INEN_PIN1_Pos)
|
||
#define PORT_PORTB_INEN_PIN2_Pos 2
|
||
#define PORT_PORTB_INEN_PIN2_Msk (0x01 << PORT_PORTB_INEN_PIN2_Pos)
|
||
#define PORT_PORTB_INEN_PIN3_Pos 3
|
||
#define PORT_PORTB_INEN_PIN3_Msk (0x01 << PORT_PORTB_INEN_PIN3_Pos)
|
||
#define PORT_PORTB_INEN_PIN4_Pos 4
|
||
#define PORT_PORTB_INEN_PIN4_Msk (0x01 << PORT_PORTB_INEN_PIN4_Pos)
|
||
#define PORT_PORTB_INEN_PIN5_Pos 5
|
||
#define PORT_PORTB_INEN_PIN5_Msk (0x01 << PORT_PORTB_INEN_PIN5_Pos)
|
||
#define PORT_PORTB_INEN_PIN6_Pos 6
|
||
#define PORT_PORTB_INEN_PIN6_Msk (0x01 << PORT_PORTB_INEN_PIN6_Pos)
|
||
#define PORT_PORTB_INEN_PIN7_Pos 7
|
||
#define PORT_PORTB_INEN_PIN7_Msk (0x01 << PORT_PORTB_INEN_PIN7_Pos)
|
||
#define PORT_PORTB_INEN_PIN8_Pos 8
|
||
#define PORT_PORTB_INEN_PIN8_Msk (0x01 << PORT_PORTB_INEN_PIN8_Pos)
|
||
#define PORT_PORTB_INEN_PIN9_Pos 9
|
||
#define PORT_PORTB_INEN_PIN9_Msk (0x01 << PORT_PORTB_INEN_PIN9_Pos)
|
||
#define PORT_PORTB_INEN_PIN10_Pos 10
|
||
#define PORT_PORTB_INEN_PIN10_Msk (0x01 << PORT_PORTB_INEN_PIN10_Pos)
|
||
#define PORT_PORTB_INEN_PIN11_Pos 11
|
||
#define PORT_PORTB_INEN_PIN11_Msk (0x01 << PORT_PORTB_INEN_PIN11_Pos)
|
||
#define PORT_PORTB_INEN_PIN12_Pos 12
|
||
#define PORT_PORTB_INEN_PIN12_Msk (0x01 << PORT_PORTB_INEN_PIN12_Pos)
|
||
#define PORT_PORTB_INEN_PIN13_Pos 13
|
||
#define PORT_PORTB_INEN_PIN13_Msk (0x01 << PORT_PORTB_INEN_PIN13_Pos)
|
||
#define PORT_PORTB_INEN_PIN14_Pos 14
|
||
#define PORT_PORTB_INEN_PIN14_Msk (0x01 << PORT_PORTB_INEN_PIN14_Pos)
|
||
#define PORT_PORTB_INEN_PIN15_Pos 15
|
||
#define PORT_PORTB_INEN_PIN15_Msk (0x01 << PORT_PORTB_INEN_PIN15_Pos)
|
||
|
||
#define PORT_PORTC_INEN_PIN0_Pos 0
|
||
#define PORT_PORTC_INEN_PIN0_Msk (0x01 << PORT_PORTC_INEN_PIN0_Pos)
|
||
#define PORT_PORTC_INEN_PIN1_Pos 1
|
||
#define PORT_PORTC_INEN_PIN1_Msk (0x01 << PORT_PORTC_INEN_PIN1_Pos)
|
||
#define PORT_PORTC_INEN_PIN2_Pos 2
|
||
#define PORT_PORTC_INEN_PIN2_Msk (0x01 << PORT_PORTC_INEN_PIN2_Pos)
|
||
#define PORT_PORTC_INEN_PIN3_Pos 3
|
||
#define PORT_PORTC_INEN_PIN3_Msk (0x01 << PORT_PORTC_INEN_PIN3_Pos)
|
||
#define PORT_PORTC_INEN_PIN4_Pos 4
|
||
#define PORT_PORTC_INEN_PIN4_Msk (0x01 << PORT_PORTC_INEN_PIN4_Pos)
|
||
#define PORT_PORTC_INEN_PIN5_Pos 5
|
||
#define PORT_PORTC_INEN_PIN5_Msk (0x01 << PORT_PORTC_INEN_PIN5_Pos)
|
||
#define PORT_PORTC_INEN_PIN6_Pos 6
|
||
#define PORT_PORTC_INEN_PIN6_Msk (0x01 << PORT_PORTC_INEN_PIN6_Pos)
|
||
#define PORT_PORTC_INEN_PIN7_Pos 7
|
||
#define PORT_PORTC_INEN_PIN7_Msk (0x01 << PORT_PORTC_INEN_PIN7_Pos)
|
||
#define PORT_PORTC_INEN_PIN8_Pos 8
|
||
#define PORT_PORTC_INEN_PIN8_Msk (0x01 << PORT_PORTC_INEN_PIN8_Pos)
|
||
#define PORT_PORTC_INEN_PIN9_Pos 9
|
||
#define PORT_PORTC_INEN_PIN9_Msk (0x01 << PORT_PORTC_INEN_PIN9_Pos)
|
||
#define PORT_PORTC_INEN_PIN10_Pos 10
|
||
#define PORT_PORTC_INEN_PIN10_Msk (0x01 << PORT_PORTC_INEN_PIN10_Pos)
|
||
#define PORT_PORTC_INEN_PIN11_Pos 11
|
||
#define PORT_PORTC_INEN_PIN11_Msk (0x01 << PORT_PORTC_INEN_PIN11_Pos)
|
||
#define PORT_PORTC_INEN_PIN12_Pos 12
|
||
#define PORT_PORTC_INEN_PIN12_Msk (0x01 << PORT_PORTC_INEN_PIN12_Pos)
|
||
#define PORT_PORTC_INEN_PIN13_Pos 13
|
||
#define PORT_PORTC_INEN_PIN13_Msk (0x01 << PORT_PORTC_INEN_PIN13_Pos)
|
||
#define PORT_PORTC_INEN_PIN14_Pos 14
|
||
#define PORT_PORTC_INEN_PIN14_Msk (0x01 << PORT_PORTC_INEN_PIN14_Pos)
|
||
#define PORT_PORTC_INEN_PIN15_Pos 15
|
||
#define PORT_PORTC_INEN_PIN15_Msk (0x01 << PORT_PORTC_INEN_PIN15_Pos)
|
||
|
||
#define PORT_PORTM_INEN_PIN0_Pos 0
|
||
#define PORT_PORTM_INEN_PIN0_Msk (0x01 << PORT_PORTM_INEN_PIN0_Pos)
|
||
#define PORT_PORTM_INEN_PIN1_Pos 1
|
||
#define PORT_PORTM_INEN_PIN1_Msk (0x01 << PORT_PORTM_INEN_PIN1_Pos)
|
||
#define PORT_PORTM_INEN_PIN2_Pos 2
|
||
#define PORT_PORTM_INEN_PIN2_Msk (0x01 << PORT_PORTM_INEN_PIN2_Pos)
|
||
#define PORT_PORTM_INEN_PIN3_Pos 3
|
||
#define PORT_PORTM_INEN_PIN3_Msk (0x01 << PORT_PORTM_INEN_PIN3_Pos)
|
||
#define PORT_PORTM_INEN_PIN4_Pos 4
|
||
#define PORT_PORTM_INEN_PIN4_Msk (0x01 << PORT_PORTM_INEN_PIN4_Pos)
|
||
#define PORT_PORTM_INEN_PIN5_Pos 5
|
||
#define PORT_PORTM_INEN_PIN5_Msk (0x01 << PORT_PORTM_INEN_PIN5_Pos)
|
||
#define PORT_PORTM_INEN_PIN6_Pos 6
|
||
#define PORT_PORTM_INEN_PIN6_Msk (0x01 << PORT_PORTM_INEN_PIN6_Pos)
|
||
#define PORT_PORTM_INEN_PIN7_Pos 7
|
||
#define PORT_PORTM_INEN_PIN7_Msk (0x01 << PORT_PORTM_INEN_PIN7_Pos)
|
||
#define PORT_PORTM_INEN_PIN8_Pos 8
|
||
#define PORT_PORTM_INEN_PIN8_Msk (0x01 << PORT_PORTM_INEN_PIN8_Pos)
|
||
#define PORT_PORTM_INEN_PIN9_Pos 9
|
||
#define PORT_PORTM_INEN_PIN9_Msk (0x01 << PORT_PORTM_INEN_PIN9_Pos)
|
||
#define PORT_PORTM_INEN_PIN10_Pos 10
|
||
#define PORT_PORTM_INEN_PIN10_Msk (0x01 << PORT_PORTM_INEN_PIN10_Pos)
|
||
#define PORT_PORTM_INEN_PIN11_Pos 11
|
||
#define PORT_PORTM_INEN_PIN11_Msk (0x01 << PORT_PORTM_INEN_PIN11_Pos)
|
||
#define PORT_PORTM_INEN_PIN12_Pos 12
|
||
#define PORT_PORTM_INEN_PIN12_Msk (0x01 << PORT_PORTM_INEN_PIN12_Pos)
|
||
#define PORT_PORTM_INEN_PIN13_Pos 13
|
||
#define PORT_PORTM_INEN_PIN13_Msk (0x01 << PORT_PORTM_INEN_PIN13_Pos)
|
||
#define PORT_PORTM_INEN_PIN14_Pos 14
|
||
#define PORT_PORTM_INEN_PIN14_Msk (0x01 << PORT_PORTM_INEN_PIN14_Pos)
|
||
#define PORT_PORTM_INEN_PIN15_Pos 15
|
||
#define PORT_PORTM_INEN_PIN15_Msk (0x01 << PORT_PORTM_INEN_PIN15_Pos)
|
||
#define PORT_PORTM_INEN_PIN16_Pos 16
|
||
#define PORT_PORTM_INEN_PIN16_Msk (0x01 << PORT_PORTM_INEN_PIN16_Pos)
|
||
#define PORT_PORTM_INEN_PIN17_Pos 17
|
||
#define PORT_PORTM_INEN_PIN17_Msk (0x01 << PORT_PORTM_INEN_PIN17_Pos)
|
||
#define PORT_PORTM_INEN_PIN18_Pos 18
|
||
#define PORT_PORTM_INEN_PIN18_Msk (0x01 << PORT_PORTM_INEN_PIN18_Pos)
|
||
#define PORT_PORTM_INEN_PIN19_Pos 19
|
||
#define PORT_PORTM_INEN_PIN19_Msk (0x01 << PORT_PORTM_INEN_PIN19_Pos)
|
||
#define PORT_PORTM_INEN_PIN20_Pos 20
|
||
#define PORT_PORTM_INEN_PIN20_Msk (0x01 << PORT_PORTM_INEN_PIN20_Pos)
|
||
#define PORT_PORTM_INEN_PIN21_Pos 21
|
||
#define PORT_PORTM_INEN_PIN21_Msk (0x01 << PORT_PORTM_INEN_PIN21_Pos)
|
||
#define PORT_PORTM_INEN_PIN22_Pos 22
|
||
#define PORT_PORTM_INEN_PIN22_Msk (0x01 << PORT_PORTM_INEN_PIN22_Pos)
|
||
#define PORT_PORTM_INEN_PIN23_Pos 23
|
||
#define PORT_PORTM_INEN_PIN23_Msk (0x01 << PORT_PORTM_INEN_PIN23_Pos)
|
||
|
||
#define PORT_PORTN_INEN_PIN0_Pos 0
|
||
#define PORT_PORTN_INEN_PIN0_Msk (0x01 << PORT_PORTN_INEN_PIN0_Pos)
|
||
#define PORT_PORTN_INEN_PIN1_Pos 1
|
||
#define PORT_PORTN_INEN_PIN1_Msk (0x01 << PORT_PORTN_INEN_PIN1_Pos)
|
||
#define PORT_PORTN_INEN_PIN2_Pos 2
|
||
#define PORT_PORTN_INEN_PIN2_Msk (0x01 << PORT_PORTN_INEN_PIN2_Pos)
|
||
#define PORT_PORTN_INEN_PIN3_Pos 3
|
||
#define PORT_PORTN_INEN_PIN3_Msk (0x01 << PORT_PORTN_INEN_PIN3_Pos)
|
||
#define PORT_PORTN_INEN_PIN4_Pos 4
|
||
#define PORT_PORTN_INEN_PIN4_Msk (0x01 << PORT_PORTN_INEN_PIN4_Pos)
|
||
#define PORT_PORTN_INEN_PIN5_Pos 5
|
||
#define PORT_PORTN_INEN_PIN5_Msk (0x01 << PORT_PORTN_INEN_PIN5_Pos)
|
||
#define PORT_PORTN_INEN_PIN6_Pos 6
|
||
#define PORT_PORTN_INEN_PIN6_Msk (0x01 << PORT_PORTN_INEN_PIN6_Pos)
|
||
#define PORT_PORTN_INEN_PIN7_Pos 7
|
||
#define PORT_PORTN_INEN_PIN7_Msk (0x01 << PORT_PORTN_INEN_PIN7_Pos)
|
||
#define PORT_PORTN_INEN_PIN8_Pos 8
|
||
#define PORT_PORTN_INEN_PIN8_Msk (0x01 << PORT_PORTN_INEN_PIN8_Pos)
|
||
#define PORT_PORTN_INEN_PIN9_Pos 9
|
||
#define PORT_PORTN_INEN_PIN9_Msk (0x01 << PORT_PORTN_INEN_PIN9_Pos)
|
||
#define PORT_PORTN_INEN_PIN10_Pos 10
|
||
#define PORT_PORTN_INEN_PIN10_Msk (0x01 << PORT_PORTN_INEN_PIN10_Pos)
|
||
#define PORT_PORTN_INEN_PIN11_Pos 11
|
||
#define PORT_PORTN_INEN_PIN11_Msk (0x01 << PORT_PORTN_INEN_PIN11_Pos)
|
||
#define PORT_PORTN_INEN_PIN12_Pos 12
|
||
#define PORT_PORTN_INEN_PIN12_Msk (0x01 << PORT_PORTN_INEN_PIN12_Pos)
|
||
#define PORT_PORTN_INEN_PIN13_Pos 13
|
||
#define PORT_PORTN_INEN_PIN13_Msk (0x01 << PORT_PORTN_INEN_PIN13_Pos)
|
||
#define PORT_PORTN_INEN_PIN14_Pos 14
|
||
#define PORT_PORTN_INEN_PIN14_Msk (0x01 << PORT_PORTN_INEN_PIN14_Pos)
|
||
#define PORT_PORTN_INEN_PIN15_Pos 15
|
||
#define PORT_PORTN_INEN_PIN15_Msk (0x01 << PORT_PORTN_INEN_PIN15_Pos)
|
||
#define PORT_PORTN_INEN_PIN16_Pos 16
|
||
#define PORT_PORTN_INEN_PIN16_Msk (0x01 << PORT_PORTN_INEN_PIN16_Pos)
|
||
#define PORT_PORTN_INEN_PIN17_Pos 17
|
||
#define PORT_PORTN_INEN_PIN17_Msk (0x01 << PORT_PORTN_INEN_PIN17_Pos)
|
||
#define PORT_PORTN_INEN_PIN18_Pos 18
|
||
#define PORT_PORTN_INEN_PIN18_Msk (0x01 << PORT_PORTN_INEN_PIN18_Pos)
|
||
#define PORT_PORTN_INEN_PIN19_Pos 19
|
||
#define PORT_PORTN_INEN_PIN19_Msk (0x01 << PORT_PORTN_INEN_PIN19_Pos)
|
||
#define PORT_PORTN_INEN_PIN20_Pos 20
|
||
#define PORT_PORTN_INEN_PIN20_Msk (0x01 << PORT_PORTN_INEN_PIN20_Pos)
|
||
#define PORT_PORTN_INEN_PIN21_Pos 21
|
||
#define PORT_PORTN_INEN_PIN21_Msk (0x01 << PORT_PORTN_INEN_PIN21_Pos)
|
||
#define PORT_PORTN_INEN_PIN22_Pos 22
|
||
#define PORT_PORTN_INEN_PIN22_Msk (0x01 << PORT_PORTN_INEN_PIN22_Pos)
|
||
#define PORT_PORTN_INEN_PIN23_Pos 23
|
||
#define PORT_PORTN_INEN_PIN23_Msk (0x01 << PORT_PORTN_INEN_PIN23_Pos)
|
||
|
||
#define PORT_PORTP_INEN_PIN0_Pos 0
|
||
#define PORT_PORTP_INEN_PIN0_Msk (0x01 << PORT_PORTP_INEN_PIN0_Pos)
|
||
#define PORT_PORTP_INEN_PIN1_Pos 1
|
||
#define PORT_PORTP_INEN_PIN1_Msk (0x01 << PORT_PORTP_INEN_PIN1_Pos)
|
||
#define PORT_PORTP_INEN_PIN2_Pos 2
|
||
#define PORT_PORTP_INEN_PIN2_Msk (0x01 << PORT_PORTP_INEN_PIN2_Pos)
|
||
#define PORT_PORTP_INEN_PIN3_Pos 3
|
||
#define PORT_PORTP_INEN_PIN3_Msk (0x01 << PORT_PORTP_INEN_PIN3_Pos)
|
||
#define PORT_PORTP_INEN_PIN4_Pos 4
|
||
#define PORT_PORTP_INEN_PIN4_Msk (0x01 << PORT_PORTP_INEN_PIN4_Pos)
|
||
#define PORT_PORTP_INEN_PIN5_Pos 5
|
||
#define PORT_PORTP_INEN_PIN5_Msk (0x01 << PORT_PORTP_INEN_PIN5_Pos)
|
||
#define PORT_PORTP_INEN_PIN6_Pos 6
|
||
#define PORT_PORTP_INEN_PIN6_Msk (0x01 << PORT_PORTP_INEN_PIN6_Pos)
|
||
#define PORT_PORTP_INEN_PIN7_Pos 7
|
||
#define PORT_PORTP_INEN_PIN7_Msk (0x01 << PORT_PORTP_INEN_PIN7_Pos)
|
||
#define PORT_PORTP_INEN_PIN8_Pos 8
|
||
#define PORT_PORTP_INEN_PIN8_Msk (0x01 << PORT_PORTP_INEN_PIN8_Pos)
|
||
#define PORT_PORTP_INEN_PIN9_Pos 9
|
||
#define PORT_PORTP_INEN_PIN9_Msk (0x01 << PORT_PORTP_INEN_PIN9_Pos)
|
||
#define PORT_PORTP_INEN_PIN10_Pos 10
|
||
#define PORT_PORTP_INEN_PIN10_Msk (0x01 << PORT_PORTP_INEN_PIN10_Pos)
|
||
#define PORT_PORTP_INEN_PIN11_Pos 11
|
||
#define PORT_PORTP_INEN_PIN11_Msk (0x01 << PORT_PORTP_INEN_PIN11_Pos)
|
||
#define PORT_PORTP_INEN_PIN12_Pos 12
|
||
#define PORT_PORTP_INEN_PIN12_Msk (0x01 << PORT_PORTP_INEN_PIN12_Pos)
|
||
#define PORT_PORTP_INEN_PIN13_Pos 13
|
||
#define PORT_PORTP_INEN_PIN13_Msk (0x01 << PORT_PORTP_INEN_PIN13_Pos)
|
||
#define PORT_PORTP_INEN_PIN14_Pos 14
|
||
#define PORT_PORTP_INEN_PIN14_Msk (0x01 << PORT_PORTP_INEN_PIN14_Pos)
|
||
#define PORT_PORTP_INEN_PIN15_Pos 15
|
||
#define PORT_PORTP_INEN_PIN15_Msk (0x01 << PORT_PORTP_INEN_PIN15_Pos)
|
||
#define PORT_PORTP_INEN_PIN16_Pos 16
|
||
#define PORT_PORTP_INEN_PIN16_Msk (0x01 << PORT_PORTP_INEN_PIN16_Pos)
|
||
#define PORT_PORTP_INEN_PIN17_Pos 17
|
||
#define PORT_PORTP_INEN_PIN17_Msk (0x01 << PORT_PORTP_INEN_PIN17_Pos)
|
||
#define PORT_PORTP_INEN_PIN18_Pos 18
|
||
#define PORT_PORTP_INEN_PIN18_Msk (0x01 << PORT_PORTP_INEN_PIN18_Pos)
|
||
#define PORT_PORTP_INEN_PIN19_Pos 19
|
||
#define PORT_PORTP_INEN_PIN19_Msk (0x01 << PORT_PORTP_INEN_PIN19_Pos)
|
||
#define PORT_PORTP_INEN_PIN20_Pos 20
|
||
#define PORT_PORTP_INEN_PIN20_Msk (0x01 << PORT_PORTP_INEN_PIN20_Pos)
|
||
#define PORT_PORTP_INEN_PIN21_Pos 21
|
||
#define PORT_PORTP_INEN_PIN21_Msk (0x01 << PORT_PORTP_INEN_PIN21_Pos)
|
||
#define PORT_PORTP_INEN_PIN22_Pos 22
|
||
#define PORT_PORTP_INEN_PIN22_Msk (0x01 << PORT_PORTP_INEN_PIN22_Pos)
|
||
#define PORT_PORTP_INEN_PIN23_Pos 23
|
||
#define PORT_PORTP_INEN_PIN23_Msk (0x01 << PORT_PORTP_INEN_PIN23_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t DATA;
|
||
#define PIN0 0
|
||
#define PIN1 1
|
||
#define PIN2 2
|
||
#define PIN3 3
|
||
#define PIN4 4
|
||
#define PIN5 5
|
||
#define PIN6 6
|
||
#define PIN7 7
|
||
#define PIN8 8
|
||
#define PIN9 9
|
||
#define PIN10 10
|
||
#define PIN11 11
|
||
#define PIN12 12
|
||
#define PIN13 13
|
||
#define PIN14 14
|
||
#define PIN15 15
|
||
#define PIN16 16
|
||
#define PIN17 17
|
||
#define PIN18 18
|
||
#define PIN19 19
|
||
#define PIN20 20
|
||
#define PIN21 21
|
||
#define PIN22 22
|
||
#define PIN23 23
|
||
#define PIN24 24
|
||
|
||
__IO uint32_t DIR; //0 <20><><EFBFBD><EFBFBD> 1 <20><><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t INTLVLTRG; //Interrupt Level Trigger 1 <20><>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> 0 <20><><EFBFBD>ش<EFBFBD><D8B4><EFBFBD><EFBFBD>ж<EFBFBD>
|
||
|
||
__IO uint32_t INTBE; //Both Edge<67><65><EFBFBD><EFBFBD>INTLVLTRG<52><47>Ϊ<EFBFBD><CEAA><EFBFBD>ش<EFBFBD><D8B4><EFBFBD><EFBFBD>ж<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>1<EFBFBD><31>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD>غ<EFBFBD><D8BA>½<EFBFBD><C2BD>ض<EFBFBD><D8B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<D0B6><CFA3><EFBFBD>0ʱ<30><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>INTRISEENѡ<4E><D1A1>
|
||
|
||
__IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable 1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F>ߵ<EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> 0 <20>½<EFBFBD><C2BD><EFBFBD>/<2F>͵<EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||
|
||
__IO uint32_t INTEN; //1 <20>ж<EFBFBD>ʹ<EFBFBD><CAB9> 0 <20>жϽ<D0B6>ֹ
|
||
|
||
__IO uint32_t INTRAWSTAT; //<2F>жϼ<D0B6><CFBC>ⵥԪ<E2B5A5>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>˴<EFBFBD><CBB4><EFBFBD><EFBFBD>жϵ<D0B6><CFB5><EFBFBD><EFBFBD><EFBFBD> 1 <20><><EFBFBD><EFBFBD><E2B5BD><EFBFBD>жϴ<D0B6><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0 û<>м<EFBFBD><D0BC><EFBFBD>жϴ<D0B6><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t INTSTAT; //INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0
|
||
|
||
__IO uint32_t INTCLR; //д1<D0B4><31><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־<EFBFBD><D6BE>ֻ<EFBFBD>Ա<EFBFBD><D4B1>ش<EFBFBD><D8B4><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>
|
||
} GPIO_TypeDef;
|
||
|
||
|
||
#define GPIO_DATA_PIN0_Pos 0
|
||
#define GPIO_DATA_PIN0_Msk (0x01 << GPIO_DATA_PIN0_Pos)
|
||
#define GPIO_DATA_PIN1_Pos 1
|
||
#define GPIO_DATA_PIN1_Msk (0x01 << GPIO_DATA_PIN1_Pos)
|
||
#define GPIO_DATA_PIN2_Pos 2
|
||
#define GPIO_DATA_PIN2_Msk (0x01 << GPIO_DATA_PIN2_Pos)
|
||
#define GPIO_DATA_PIN3_Pos 3
|
||
#define GPIO_DATA_PIN3_Msk (0x01 << GPIO_DATA_PIN3_Pos)
|
||
#define GPIO_DATA_PIN4_Pos 4
|
||
#define GPIO_DATA_PIN4_Msk (0x01 << GPIO_DATA_PIN4_Pos)
|
||
#define GPIO_DATA_PIN5_Pos 5
|
||
#define GPIO_DATA_PIN5_Msk (0x01 << GPIO_DATA_PIN5_Pos)
|
||
#define GPIO_DATA_PIN6_Pos 6
|
||
#define GPIO_DATA_PIN6_Msk (0x01 << GPIO_DATA_PIN6_Pos)
|
||
#define GPIO_DATA_PIN7_Pos 7
|
||
#define GPIO_DATA_PIN7_Msk (0x01 << GPIO_DATA_PIN7_Pos)
|
||
#define GPIO_DATA_PIN8_Pos 8
|
||
#define GPIO_DATA_PIN8_Msk (0x01 << GPIO_DATA_PIN8_Pos)
|
||
#define GPIO_DATA_PIN9_Pos 9
|
||
#define GPIO_DATA_PIN9_Msk (0x01 << GPIO_DATA_PIN9_Pos)
|
||
#define GPIO_DATA_PIN10_Pos 10
|
||
#define GPIO_DATA_PIN10_Msk (0x01 << GPIO_DATA_PIN10_Pos)
|
||
#define GPIO_DATA_PIN11_Pos 11
|
||
#define GPIO_DATA_PIN11_Msk (0x01 << GPIO_DATA_PIN11_Pos)
|
||
#define GPIO_DATA_PIN12_Pos 12
|
||
#define GPIO_DATA_PIN12_Msk (0x01 << GPIO_DATA_PIN12_Pos)
|
||
#define GPIO_DATA_PIN13_Pos 13
|
||
#define GPIO_DATA_PIN13_Msk (0x01 << GPIO_DATA_PIN13_Pos)
|
||
#define GPIO_DATA_PIN14_Pos 14
|
||
#define GPIO_DATA_PIN14_Msk (0x01 << GPIO_DATA_PIN14_Pos)
|
||
#define GPIO_DATA_PIN15_Pos 15
|
||
#define GPIO_DATA_PIN15_Msk (0x01 << GPIO_DATA_PIN15_Pos)
|
||
#define GPIO_DATA_PIN16_Pos 16
|
||
#define GPIO_DATA_PIN16_Msk (0x01 << GPIO_DATA_PIN16_Pos)
|
||
#define GPIO_DATA_PIN17_Pos 17
|
||
#define GPIO_DATA_PIN17_Msk (0x01 << GPIO_DATA_PIN17_Pos)
|
||
#define GPIO_DATA_PIN18_Pos 18
|
||
#define GPIO_DATA_PIN18_Msk (0x01 << GPIO_DATA_PIN18_Pos)
|
||
#define GPIO_DATA_PIN19_Pos 19
|
||
#define GPIO_DATA_PIN19_Msk (0x01 << GPIO_DATA_PIN19_Pos)
|
||
#define GPIO_DATA_PIN20_Pos 20
|
||
#define GPIO_DATA_PIN20_Msk (0x01 << GPIO_DATA_PIN20_Pos)
|
||
#define GPIO_DATA_PIN21_Pos 21
|
||
#define GPIO_DATA_PIN21_Msk (0x01 << GPIO_DATA_PIN21_Pos)
|
||
#define GPIO_DATA_PIN22_Pos 22
|
||
#define GPIO_DATA_PIN22_Msk (0x01 << GPIO_DATA_PIN22_Pos)
|
||
#define GPIO_DATA_PIN23_Pos 23
|
||
#define GPIO_DATA_PIN23_Msk (0x01 << GPIO_DATA_PIN23_Pos)
|
||
|
||
#define GPIO_DIR_PIN0_Pos 0
|
||
#define GPIO_DIR_PIN0_Msk (0x01 << GPIO_DIR_PIN0_Pos)
|
||
#define GPIO_DIR_PIN1_Pos 1
|
||
#define GPIO_DIR_PIN1_Msk (0x01 << GPIO_DIR_PIN1_Pos)
|
||
#define GPIO_DIR_PIN2_Pos 2
|
||
#define GPIO_DIR_PIN2_Msk (0x01 << GPIO_DIR_PIN2_Pos)
|
||
#define GPIO_DIR_PIN3_Pos 3
|
||
#define GPIO_DIR_PIN3_Msk (0x01 << GPIO_DIR_PIN3_Pos)
|
||
#define GPIO_DIR_PIN4_Pos 4
|
||
#define GPIO_DIR_PIN4_Msk (0x01 << GPIO_DIR_PIN4_Pos)
|
||
#define GPIO_DIR_PIN5_Pos 5
|
||
#define GPIO_DIR_PIN5_Msk (0x01 << GPIO_DIR_PIN5_Pos)
|
||
#define GPIO_DIR_PIN6_Pos 6
|
||
#define GPIO_DIR_PIN6_Msk (0x01 << GPIO_DIR_PIN6_Pos)
|
||
#define GPIO_DIR_PIN7_Pos 7
|
||
#define GPIO_DIR_PIN7_Msk (0x01 << GPIO_DIR_PIN7_Pos)
|
||
#define GPIO_DIR_PIN8_Pos 8
|
||
#define GPIO_DIR_PIN8_Msk (0x01 << GPIO_DIR_PIN8_Pos)
|
||
#define GPIO_DIR_PIN9_Pos 9
|
||
#define GPIO_DIR_PIN9_Msk (0x01 << GPIO_DIR_PIN9_Pos)
|
||
#define GPIO_DIR_PIN10_Pos 10
|
||
#define GPIO_DIR_PIN10_Msk (0x01 << GPIO_DIR_PIN10_Pos)
|
||
#define GPIO_DIR_PIN11_Pos 11
|
||
#define GPIO_DIR_PIN11_Msk (0x01 << GPIO_DIR_PIN11_Pos)
|
||
#define GPIO_DIR_PIN12_Pos 12
|
||
#define GPIO_DIR_PIN12_Msk (0x01 << GPIO_DIR_PIN12_Pos)
|
||
#define GPIO_DIR_PIN13_Pos 13
|
||
#define GPIO_DIR_PIN13_Msk (0x01 << GPIO_DIR_PIN13_Pos)
|
||
#define GPIO_DIR_PIN14_Pos 14
|
||
#define GPIO_DIR_PIN14_Msk (0x01 << GPIO_DIR_PIN14_Pos)
|
||
#define GPIO_DIR_PIN15_Pos 15
|
||
#define GPIO_DIR_PIN15_Msk (0x01 << GPIO_DIR_PIN15_Pos)
|
||
#define GPIO_DIR_PIN16_Pos 16
|
||
#define GPIO_DIR_PIN16_Msk (0x01 << GPIO_DIR_PIN16_Pos)
|
||
#define GPIO_DIR_PIN17_Pos 17
|
||
#define GPIO_DIR_PIN17_Msk (0x01 << GPIO_DIR_PIN17_Pos)
|
||
#define GPIO_DIR_PIN18_Pos 18
|
||
#define GPIO_DIR_PIN18_Msk (0x01 << GPIO_DIR_PIN18_Pos)
|
||
#define GPIO_DIR_PIN19_Pos 19
|
||
#define GPIO_DIR_PIN19_Msk (0x01 << GPIO_DIR_PIN19_Pos)
|
||
#define GPIO_DIR_PIN20_Pos 20
|
||
#define GPIO_DIR_PIN20_Msk (0x01 << GPIO_DIR_PIN20_Pos)
|
||
#define GPIO_DIR_PIN21_Pos 21
|
||
#define GPIO_DIR_PIN21_Msk (0x01 << GPIO_DIR_PIN21_Pos)
|
||
#define GPIO_DIR_PIN22_Pos 22
|
||
#define GPIO_DIR_PIN22_Msk (0x01 << GPIO_DIR_PIN22_Pos)
|
||
#define GPIO_DIR_PIN23_Pos 23
|
||
#define GPIO_DIR_PIN23_Msk (0x01 << GPIO_DIR_PIN23_Pos)
|
||
|
||
#define GPIO_INTLVLTRG_PIN0_Pos 0
|
||
#define GPIO_INTLVLTRG_PIN0_Msk (0x01 << GPIO_INTLVLTRG_PIN0_Pos)
|
||
#define GPIO_INTLVLTRG_PIN1_Pos 1
|
||
#define GPIO_INTLVLTRG_PIN1_Msk (0x01 << GPIO_INTLVLTRG_PIN1_Pos)
|
||
#define GPIO_INTLVLTRG_PIN2_Pos 2
|
||
#define GPIO_INTLVLTRG_PIN2_Msk (0x01 << GPIO_INTLVLTRG_PIN2_Pos)
|
||
#define GPIO_INTLVLTRG_PIN3_Pos 3
|
||
#define GPIO_INTLVLTRG_PIN3_Msk (0x01 << GPIO_INTLVLTRG_PIN3_Pos)
|
||
#define GPIO_INTLVLTRG_PIN4_Pos 4
|
||
#define GPIO_INTLVLTRG_PIN4_Msk (0x01 << GPIO_INTLVLTRG_PIN4_Pos)
|
||
#define GPIO_INTLVLTRG_PIN5_Pos 5
|
||
#define GPIO_INTLVLTRG_PIN5_Msk (0x01 << GPIO_INTLVLTRG_PIN5_Pos)
|
||
#define GPIO_INTLVLTRG_PIN6_Pos 6
|
||
#define GPIO_INTLVLTRG_PIN6_Msk (0x01 << GPIO_INTLVLTRG_PIN6_Pos)
|
||
#define GPIO_INTLVLTRG_PIN7_Pos 7
|
||
#define GPIO_INTLVLTRG_PIN7_Msk (0x01 << GPIO_INTLVLTRG_PIN7_Pos)
|
||
#define GPIO_INTLVLTRG_PIN8_Pos 8
|
||
#define GPIO_INTLVLTRG_PIN8_Msk (0x01 << GPIO_INTLVLTRG_PIN8_Pos)
|
||
#define GPIO_INTLVLTRG_PIN9_Pos 9
|
||
#define GPIO_INTLVLTRG_PIN9_Msk (0x01 << GPIO_INTLVLTRG_PIN9_Pos)
|
||
#define GPIO_INTLVLTRG_PIN10_Pos 10
|
||
#define GPIO_INTLVLTRG_PIN10_Msk (0x01 << GPIO_INTLVLTRG_PIN10_Pos)
|
||
#define GPIO_INTLVLTRG_PIN11_Pos 11
|
||
#define GPIO_INTLVLTRG_PIN11_Msk (0x01 << GPIO_INTLVLTRG_PIN11_Pos)
|
||
#define GPIO_INTLVLTRG_PIN12_Pos 12
|
||
#define GPIO_INTLVLTRG_PIN12_Msk (0x01 << GPIO_INTLVLTRG_PIN12_Pos)
|
||
#define GPIO_INTLVLTRG_PIN13_Pos 13
|
||
#define GPIO_INTLVLTRG_PIN13_Msk (0x01 << GPIO_INTLVLTRG_PIN13_Pos)
|
||
#define GPIO_INTLVLTRG_PIN14_Pos 14
|
||
#define GPIO_INTLVLTRG_PIN14_Msk (0x01 << GPIO_INTLVLTRG_PIN14_Pos)
|
||
#define GPIO_INTLVLTRG_PIN15_Pos 15
|
||
#define GPIO_INTLVLTRG_PIN15_Msk (0x01 << GPIO_INTLVLTRG_PIN15_Pos)
|
||
#define GPIO_INTLVLTRG_PIN16_Pos 16
|
||
#define GPIO_INTLVLTRG_PIN16_Msk (0x01 << GPIO_INTLVLTRG_PIN16_Pos)
|
||
#define GPIO_INTLVLTRG_PIN17_Pos 17
|
||
#define GPIO_INTLVLTRG_PIN17_Msk (0x01 << GPIO_INTLVLTRG_PIN17_Pos)
|
||
#define GPIO_INTLVLTRG_PIN18_Pos 18
|
||
#define GPIO_INTLVLTRG_PIN18_Msk (0x01 << GPIO_INTLVLTRG_PIN18_Pos)
|
||
#define GPIO_INTLVLTRG_PIN19_Pos 19
|
||
#define GPIO_INTLVLTRG_PIN19_Msk (0x01 << GPIO_INTLVLTRG_PIN19_Pos)
|
||
#define GPIO_INTLVLTRG_PIN20_Pos 20
|
||
#define GPIO_INTLVLTRG_PIN20_Msk (0x01 << GPIO_INTLVLTRG_PIN20_Pos)
|
||
#define GPIO_INTLVLTRG_PIN21_Pos 21
|
||
#define GPIO_INTLVLTRG_PIN21_Msk (0x01 << GPIO_INTLVLTRG_PIN21_Pos)
|
||
#define GPIO_INTLVLTRG_PIN22_Pos 22
|
||
#define GPIO_INTLVLTRG_PIN22_Msk (0x01 << GPIO_INTLVLTRG_PIN22_Pos)
|
||
#define GPIO_INTLVLTRG_PIN23_Pos 23
|
||
#define GPIO_INTLVLTRG_PIN23_Msk (0x01 << GPIO_INTLVLTRG_PIN23_Pos)
|
||
|
||
#define GPIO_INTBE_PIN0_Pos 0
|
||
#define GPIO_INTBE_PIN0_Msk (0x01 << GPIO_INTBE_PIN0_Pos)
|
||
#define GPIO_INTBE_PIN1_Pos 1
|
||
#define GPIO_INTBE_PIN1_Msk (0x01 << GPIO_INTBE_PIN1_Pos)
|
||
#define GPIO_INTBE_PIN2_Pos 2
|
||
#define GPIO_INTBE_PIN2_Msk (0x01 << GPIO_INTBE_PIN2_Pos)
|
||
#define GPIO_INTBE_PIN3_Pos 3
|
||
#define GPIO_INTBE_PIN3_Msk (0x01 << GPIO_INTBE_PIN3_Pos)
|
||
#define GPIO_INTBE_PIN4_Pos 4
|
||
#define GPIO_INTBE_PIN4_Msk (0x01 << GPIO_INTBE_PIN4_Pos)
|
||
#define GPIO_INTBE_PIN5_Pos 5
|
||
#define GPIO_INTBE_PIN5_Msk (0x01 << GPIO_INTBE_PIN5_Pos)
|
||
#define GPIO_INTBE_PIN6_Pos 6
|
||
#define GPIO_INTBE_PIN6_Msk (0x01 << GPIO_INTBE_PIN6_Pos)
|
||
#define GPIO_INTBE_PIN7_Pos 7
|
||
#define GPIO_INTBE_PIN7_Msk (0x01 << GPIO_INTBE_PIN7_Pos)
|
||
#define GPIO_INTBE_PIN8_Pos 8
|
||
#define GPIO_INTBE_PIN8_Msk (0x01 << GPIO_INTBE_PIN8_Pos)
|
||
#define GPIO_INTBE_PIN9_Pos 9
|
||
#define GPIO_INTBE_PIN9_Msk (0x01 << GPIO_INTBE_PIN9_Pos)
|
||
#define GPIO_INTBE_PIN10_Pos 10
|
||
#define GPIO_INTBE_PIN10_Msk (0x01 << GPIO_INTBE_PIN10_Pos)
|
||
#define GPIO_INTBE_PIN11_Pos 11
|
||
#define GPIO_INTBE_PIN11_Msk (0x01 << GPIO_INTBE_PIN11_Pos)
|
||
#define GPIO_INTBE_PIN12_Pos 12
|
||
#define GPIO_INTBE_PIN12_Msk (0x01 << GPIO_INTBE_PIN12_Pos)
|
||
#define GPIO_INTBE_PIN13_Pos 13
|
||
#define GPIO_INTBE_PIN13_Msk (0x01 << GPIO_INTBE_PIN13_Pos)
|
||
#define GPIO_INTBE_PIN14_Pos 14
|
||
#define GPIO_INTBE_PIN14_Msk (0x01 << GPIO_INTBE_PIN14_Pos)
|
||
#define GPIO_INTBE_PIN15_Pos 15
|
||
#define GPIO_INTBE_PIN15_Msk (0x01 << GPIO_INTBE_PIN15_Pos)
|
||
#define GPIO_INTBE_PIN16_Pos 16
|
||
#define GPIO_INTBE_PIN16_Msk (0x01 << GPIO_INTBE_PIN16_Pos)
|
||
#define GPIO_INTBE_PIN17_Pos 17
|
||
#define GPIO_INTBE_PIN17_Msk (0x01 << GPIO_INTBE_PIN17_Pos)
|
||
#define GPIO_INTBE_PIN18_Pos 18
|
||
#define GPIO_INTBE_PIN18_Msk (0x01 << GPIO_INTBE_PIN18_Pos)
|
||
#define GPIO_INTBE_PIN19_Pos 19
|
||
#define GPIO_INTBE_PIN19_Msk (0x01 << GPIO_INTBE_PIN19_Pos)
|
||
#define GPIO_INTBE_PIN20_Pos 20
|
||
#define GPIO_INTBE_PIN20_Msk (0x01 << GPIO_INTBE_PIN20_Pos)
|
||
#define GPIO_INTBE_PIN21_Pos 21
|
||
#define GPIO_INTBE_PIN21_Msk (0x01 << GPIO_INTBE_PIN21_Pos)
|
||
#define GPIO_INTBE_PIN22_Pos 22
|
||
#define GPIO_INTBE_PIN22_Msk (0x01 << GPIO_INTBE_PIN22_Pos)
|
||
#define GPIO_INTBE_PIN23_Pos 23
|
||
#define GPIO_INTBE_PIN23_Msk (0x01 << GPIO_INTBE_PIN23_Pos)
|
||
|
||
#define GPIO_INTRISEEN_PIN0_Pos 0
|
||
#define GPIO_INTRISEEN_PIN0_Msk (0x01 << GPIO_INTRISEEN_PIN0_Pos)
|
||
#define GPIO_INTRISEEN_PIN1_Pos 1
|
||
#define GPIO_INTRISEEN_PIN1_Msk (0x01 << GPIO_INTRISEEN_PIN1_Pos)
|
||
#define GPIO_INTRISEEN_PIN2_Pos 2
|
||
#define GPIO_INTRISEEN_PIN2_Msk (0x01 << GPIO_INTRISEEN_PIN2_Pos)
|
||
#define GPIO_INTRISEEN_PIN3_Pos 3
|
||
#define GPIO_INTRISEEN_PIN3_Msk (0x01 << GPIO_INTRISEEN_PIN3_Pos)
|
||
#define GPIO_INTRISEEN_PIN4_Pos 4
|
||
#define GPIO_INTRISEEN_PIN4_Msk (0x01 << GPIO_INTRISEEN_PIN4_Pos)
|
||
#define GPIO_INTRISEEN_PIN5_Pos 5
|
||
#define GPIO_INTRISEEN_PIN5_Msk (0x01 << GPIO_INTRISEEN_PIN5_Pos)
|
||
#define GPIO_INTRISEEN_PIN6_Pos 6
|
||
#define GPIO_INTRISEEN_PIN6_Msk (0x01 << GPIO_INTRISEEN_PIN6_Pos)
|
||
#define GPIO_INTRISEEN_PIN7_Pos 7
|
||
#define GPIO_INTRISEEN_PIN7_Msk (0x01 << GPIO_INTRISEEN_PIN7_Pos)
|
||
#define GPIO_INTRISEEN_PIN8_Pos 8
|
||
#define GPIO_INTRISEEN_PIN8_Msk (0x01 << GPIO_INTRISEEN_PIN8_Pos)
|
||
#define GPIO_INTRISEEN_PIN9_Pos 9
|
||
#define GPIO_INTRISEEN_PIN9_Msk (0x01 << GPIO_INTRISEEN_PIN9_Pos)
|
||
#define GPIO_INTRISEEN_PIN10_Pos 10
|
||
#define GPIO_INTRISEEN_PIN10_Msk (0x01 << GPIO_INTRISEEN_PIN10_Pos)
|
||
#define GPIO_INTRISEEN_PIN11_Pos 11
|
||
#define GPIO_INTRISEEN_PIN11_Msk (0x01 << GPIO_INTRISEEN_PIN11_Pos)
|
||
#define GPIO_INTRISEEN_PIN12_Pos 12
|
||
#define GPIO_INTRISEEN_PIN12_Msk (0x01 << GPIO_INTRISEEN_PIN12_Pos)
|
||
#define GPIO_INTRISEEN_PIN13_Pos 13
|
||
#define GPIO_INTRISEEN_PIN13_Msk (0x01 << GPIO_INTRISEEN_PIN13_Pos)
|
||
#define GPIO_INTRISEEN_PIN14_Pos 14
|
||
#define GPIO_INTRISEEN_PIN14_Msk (0x01 << GPIO_INTRISEEN_PIN14_Pos)
|
||
#define GPIO_INTRISEEN_PIN15_Pos 15
|
||
#define GPIO_INTRISEEN_PIN15_Msk (0x01 << GPIO_INTRISEEN_PIN15_Pos)
|
||
#define GPIO_INTRISEEN_PIN16_Pos 16
|
||
#define GPIO_INTRISEEN_PIN16_Msk (0x01 << GPIO_INTRISEEN_PIN16_Pos)
|
||
#define GPIO_INTRISEEN_PIN17_Pos 17
|
||
#define GPIO_INTRISEEN_PIN17_Msk (0x01 << GPIO_INTRISEEN_PIN17_Pos)
|
||
#define GPIO_INTRISEEN_PIN18_Pos 18
|
||
#define GPIO_INTRISEEN_PIN18_Msk (0x01 << GPIO_INTRISEEN_PIN18_Pos)
|
||
#define GPIO_INTRISEEN_PIN19_Pos 19
|
||
#define GPIO_INTRISEEN_PIN19_Msk (0x01 << GPIO_INTRISEEN_PIN19_Pos)
|
||
#define GPIO_INTRISEEN_PIN20_Pos 20
|
||
#define GPIO_INTRISEEN_PIN20_Msk (0x01 << GPIO_INTRISEEN_PIN20_Pos)
|
||
#define GPIO_INTRISEEN_PIN21_Pos 21
|
||
#define GPIO_INTRISEEN_PIN21_Msk (0x01 << GPIO_INTRISEEN_PIN21_Pos)
|
||
#define GPIO_INTRISEEN_PIN22_Pos 22
|
||
#define GPIO_INTRISEEN_PIN22_Msk (0x01 << GPIO_INTRISEEN_PIN22_Pos)
|
||
#define GPIO_INTRISEEN_PIN23_Pos 23
|
||
#define GPIO_INTRISEEN_PIN23_Msk (0x01 << GPIO_INTRISEEN_PIN23_Pos)
|
||
|
||
#define GPIO_INTEN_PIN0_Pos 0
|
||
#define GPIO_INTEN_PIN0_Msk (0x01 << GPIO_INTEN_PIN0_Pos)
|
||
#define GPIO_INTEN_PIN1_Pos 1
|
||
#define GPIO_INTEN_PIN1_Msk (0x01 << GPIO_INTEN_PIN1_Pos)
|
||
#define GPIO_INTEN_PIN2_Pos 2
|
||
#define GPIO_INTEN_PIN2_Msk (0x01 << GPIO_INTEN_PIN2_Pos)
|
||
#define GPIO_INTEN_PIN3_Pos 3
|
||
#define GPIO_INTEN_PIN3_Msk (0x01 << GPIO_INTEN_PIN3_Pos)
|
||
#define GPIO_INTEN_PIN4_Pos 4
|
||
#define GPIO_INTEN_PIN4_Msk (0x01 << GPIO_INTEN_PIN4_Pos)
|
||
#define GPIO_INTEN_PIN5_Pos 5
|
||
#define GPIO_INTEN_PIN5_Msk (0x01 << GPIO_INTEN_PIN5_Pos)
|
||
#define GPIO_INTEN_PIN6_Pos 6
|
||
#define GPIO_INTEN_PIN6_Msk (0x01 << GPIO_INTEN_PIN6_Pos)
|
||
#define GPIO_INTEN_PIN7_Pos 7
|
||
#define GPIO_INTEN_PIN7_Msk (0x01 << GPIO_INTEN_PIN7_Pos)
|
||
#define GPIO_INTEN_PIN8_Pos 8
|
||
#define GPIO_INTEN_PIN8_Msk (0x01 << GPIO_INTEN_PIN8_Pos)
|
||
#define GPIO_INTEN_PIN9_Pos 9
|
||
#define GPIO_INTEN_PIN9_Msk (0x01 << GPIO_INTEN_PIN9_Pos)
|
||
#define GPIO_INTEN_PIN10_Pos 10
|
||
#define GPIO_INTEN_PIN10_Msk (0x01 << GPIO_INTEN_PIN10_Pos)
|
||
#define GPIO_INTEN_PIN11_Pos 11
|
||
#define GPIO_INTEN_PIN11_Msk (0x01 << GPIO_INTEN_PIN11_Pos)
|
||
#define GPIO_INTEN_PIN12_Pos 12
|
||
#define GPIO_INTEN_PIN12_Msk (0x01 << GPIO_INTEN_PIN12_Pos)
|
||
#define GPIO_INTEN_PIN13_Pos 13
|
||
#define GPIO_INTEN_PIN13_Msk (0x01 << GPIO_INTEN_PIN13_Pos)
|
||
#define GPIO_INTEN_PIN14_Pos 14
|
||
#define GPIO_INTEN_PIN14_Msk (0x01 << GPIO_INTEN_PIN14_Pos)
|
||
#define GPIO_INTEN_PIN15_Pos 15
|
||
#define GPIO_INTEN_PIN15_Msk (0x01 << GPIO_INTEN_PIN15_Pos)
|
||
#define GPIO_INTEN_PIN16_Pos 16
|
||
#define GPIO_INTEN_PIN16_Msk (0x01 << GPIO_INTEN_PIN16_Pos)
|
||
#define GPIO_INTEN_PIN17_Pos 17
|
||
#define GPIO_INTEN_PIN17_Msk (0x01 << GPIO_INTEN_PIN17_Pos)
|
||
#define GPIO_INTEN_PIN18_Pos 18
|
||
#define GPIO_INTEN_PIN18_Msk (0x01 << GPIO_INTEN_PIN18_Pos)
|
||
#define GPIO_INTEN_PIN19_Pos 19
|
||
#define GPIO_INTEN_PIN19_Msk (0x01 << GPIO_INTEN_PIN19_Pos)
|
||
#define GPIO_INTEN_PIN20_Pos 20
|
||
#define GPIO_INTEN_PIN20_Msk (0x01 << GPIO_INTEN_PIN20_Pos)
|
||
#define GPIO_INTEN_PIN21_Pos 21
|
||
#define GPIO_INTEN_PIN21_Msk (0x01 << GPIO_INTEN_PIN21_Pos)
|
||
#define GPIO_INTEN_PIN22_Pos 22
|
||
#define GPIO_INTEN_PIN22_Msk (0x01 << GPIO_INTEN_PIN22_Pos)
|
||
#define GPIO_INTEN_PIN23_Pos 23
|
||
#define GPIO_INTEN_PIN23_Msk (0x01 << GPIO_INTEN_PIN23_Pos)
|
||
|
||
#define GPIO_INTRAWSTAT_PIN0_Pos 0
|
||
#define GPIO_INTRAWSTAT_PIN0_Msk (0x01 << GPIO_INTRAWSTAT_PIN0_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN1_Pos 1
|
||
#define GPIO_INTRAWSTAT_PIN1_Msk (0x01 << GPIO_INTRAWSTAT_PIN1_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN2_Pos 2
|
||
#define GPIO_INTRAWSTAT_PIN2_Msk (0x01 << GPIO_INTRAWSTAT_PIN2_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN3_Pos 3
|
||
#define GPIO_INTRAWSTAT_PIN3_Msk (0x01 << GPIO_INTRAWSTAT_PIN3_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN4_Pos 4
|
||
#define GPIO_INTRAWSTAT_PIN4_Msk (0x01 << GPIO_INTRAWSTAT_PIN4_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN5_Pos 5
|
||
#define GPIO_INTRAWSTAT_PIN5_Msk (0x01 << GPIO_INTRAWSTAT_PIN5_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN6_Pos 6
|
||
#define GPIO_INTRAWSTAT_PIN6_Msk (0x01 << GPIO_INTRAWSTAT_PIN6_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN7_Pos 7
|
||
#define GPIO_INTRAWSTAT_PIN7_Msk (0x01 << GPIO_INTRAWSTAT_PIN7_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN8_Pos 8
|
||
#define GPIO_INTRAWSTAT_PIN8_Msk (0x01 << GPIO_INTRAWSTAT_PIN8_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN9_Pos 9
|
||
#define GPIO_INTRAWSTAT_PIN9_Msk (0x01 << GPIO_INTRAWSTAT_PIN9_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN10_Pos 10
|
||
#define GPIO_INTRAWSTAT_PIN10_Msk (0x01 << GPIO_INTRAWSTAT_PIN10_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN11_Pos 11
|
||
#define GPIO_INTRAWSTAT_PIN11_Msk (0x01 << GPIO_INTRAWSTAT_PIN11_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN12_Pos 12
|
||
#define GPIO_INTRAWSTAT_PIN12_Msk (0x01 << GPIO_INTRAWSTAT_PIN12_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN13_Pos 13
|
||
#define GPIO_INTRAWSTAT_PIN13_Msk (0x01 << GPIO_INTRAWSTAT_PIN13_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN14_Pos 14
|
||
#define GPIO_INTRAWSTAT_PIN14_Msk (0x01 << GPIO_INTRAWSTAT_PIN14_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN15_Pos 15
|
||
#define GPIO_INTRAWSTAT_PIN15_Msk (0x01 << GPIO_INTRAWSTAT_PIN15_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN16_Pos 16
|
||
#define GPIO_INTRAWSTAT_PIN16_Msk (0x01 << GPIO_INTRAWSTAT_PIN16_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN17_Pos 17
|
||
#define GPIO_INTRAWSTAT_PIN17_Msk (0x01 << GPIO_INTRAWSTAT_PIN17_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN18_Pos 18
|
||
#define GPIO_INTRAWSTAT_PIN18_Msk (0x01 << GPIO_INTRAWSTAT_PIN18_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN19_Pos 19
|
||
#define GPIO_INTRAWSTAT_PIN19_Msk (0x01 << GPIO_INTRAWSTAT_PIN19_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN20_Pos 20
|
||
#define GPIO_INTRAWSTAT_PIN20_Msk (0x01 << GPIO_INTRAWSTAT_PIN20_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN21_Pos 21
|
||
#define GPIO_INTRAWSTAT_PIN21_Msk (0x01 << GPIO_INTRAWSTAT_PIN21_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN22_Pos 22
|
||
#define GPIO_INTRAWSTAT_PIN22_Msk (0x01 << GPIO_INTRAWSTAT_PIN22_Pos)
|
||
#define GPIO_INTRAWSTAT_PIN23_Pos 23
|
||
#define GPIO_INTRAWSTAT_PIN23_Msk (0x01 << GPIO_INTRAWSTAT_PIN23_Pos)
|
||
|
||
#define GPIO_INTSTAT_PIN0_Pos 0
|
||
#define GPIO_INTSTAT_PIN0_Msk (0x01 << GPIO_INTSTAT_PIN0_Pos)
|
||
#define GPIO_INTSTAT_PIN1_Pos 1
|
||
#define GPIO_INTSTAT_PIN1_Msk (0x01 << GPIO_INTSTAT_PIN1_Pos)
|
||
#define GPIO_INTSTAT_PIN2_Pos 2
|
||
#define GPIO_INTSTAT_PIN2_Msk (0x01 << GPIO_INTSTAT_PIN2_Pos)
|
||
#define GPIO_INTSTAT_PIN3_Pos 3
|
||
#define GPIO_INTSTAT_PIN3_Msk (0x01 << GPIO_INTSTAT_PIN3_Pos)
|
||
#define GPIO_INTSTAT_PIN4_Pos 4
|
||
#define GPIO_INTSTAT_PIN4_Msk (0x01 << GPIO_INTSTAT_PIN4_Pos)
|
||
#define GPIO_INTSTAT_PIN5_Pos 5
|
||
#define GPIO_INTSTAT_PIN5_Msk (0x01 << GPIO_INTSTAT_PIN5_Pos)
|
||
#define GPIO_INTSTAT_PIN6_Pos 6
|
||
#define GPIO_INTSTAT_PIN6_Msk (0x01 << GPIO_INTSTAT_PIN6_Pos)
|
||
#define GPIO_INTSTAT_PIN7_Pos 7
|
||
#define GPIO_INTSTAT_PIN7_Msk (0x01 << GPIO_INTSTAT_PIN7_Pos)
|
||
#define GPIO_INTSTAT_PIN8_Pos 8
|
||
#define GPIO_INTSTAT_PIN8_Msk (0x01 << GPIO_INTSTAT_PIN8_Pos)
|
||
#define GPIO_INTSTAT_PIN9_Pos 9
|
||
#define GPIO_INTSTAT_PIN9_Msk (0x01 << GPIO_INTSTAT_PIN9_Pos)
|
||
#define GPIO_INTSTAT_PIN10_Pos 10
|
||
#define GPIO_INTSTAT_PIN10_Msk (0x01 << GPIO_INTSTAT_PIN10_Pos)
|
||
#define GPIO_INTSTAT_PIN11_Pos 11
|
||
#define GPIO_INTSTAT_PIN11_Msk (0x01 << GPIO_INTSTAT_PIN11_Pos)
|
||
#define GPIO_INTSTAT_PIN12_Pos 12
|
||
#define GPIO_INTSTAT_PIN12_Msk (0x01 << GPIO_INTSTAT_PIN12_Pos)
|
||
#define GPIO_INTSTAT_PIN13_Pos 13
|
||
#define GPIO_INTSTAT_PIN13_Msk (0x01 << GPIO_INTSTAT_PIN13_Pos)
|
||
#define GPIO_INTSTAT_PIN14_Pos 14
|
||
#define GPIO_INTSTAT_PIN14_Msk (0x01 << GPIO_INTSTAT_PIN14_Pos)
|
||
#define GPIO_INTSTAT_PIN15_Pos 15
|
||
#define GPIO_INTSTAT_PIN15_Msk (0x01 << GPIO_INTSTAT_PIN15_Pos)
|
||
#define GPIO_INTSTAT_PIN16_Pos 16
|
||
#define GPIO_INTSTAT_PIN16_Msk (0x01 << GPIO_INTSTAT_PIN16_Pos)
|
||
#define GPIO_INTSTAT_PIN17_Pos 17
|
||
#define GPIO_INTSTAT_PIN17_Msk (0x01 << GPIO_INTSTAT_PIN17_Pos)
|
||
#define GPIO_INTSTAT_PIN18_Pos 18
|
||
#define GPIO_INTSTAT_PIN18_Msk (0x01 << GPIO_INTSTAT_PIN18_Pos)
|
||
#define GPIO_INTSTAT_PIN19_Pos 19
|
||
#define GPIO_INTSTAT_PIN19_Msk (0x01 << GPIO_INTSTAT_PIN19_Pos)
|
||
#define GPIO_INTSTAT_PIN20_Pos 20
|
||
#define GPIO_INTSTAT_PIN20_Msk (0x01 << GPIO_INTSTAT_PIN20_Pos)
|
||
#define GPIO_INTSTAT_PIN21_Pos 21
|
||
#define GPIO_INTSTAT_PIN21_Msk (0x01 << GPIO_INTSTAT_PIN21_Pos)
|
||
#define GPIO_INTSTAT_PIN22_Pos 22
|
||
#define GPIO_INTSTAT_PIN22_Msk (0x01 << GPIO_INTSTAT_PIN22_Pos)
|
||
#define GPIO_INTSTAT_PIN23_Pos 23
|
||
#define GPIO_INTSTAT_PIN23_Msk (0x01 << GPIO_INTSTAT_PIN23_Pos)
|
||
|
||
#define GPIO_INTCLR_PIN0_Pos 0
|
||
#define GPIO_INTCLR_PIN0_Msk (0x01 << GPIO_INTCLR_PIN0_Pos)
|
||
#define GPIO_INTCLR_PIN1_Pos 1
|
||
#define GPIO_INTCLR_PIN1_Msk (0x01 << GPIO_INTCLR_PIN1_Pos)
|
||
#define GPIO_INTCLR_PIN2_Pos 2
|
||
#define GPIO_INTCLR_PIN2_Msk (0x01 << GPIO_INTCLR_PIN2_Pos)
|
||
#define GPIO_INTCLR_PIN3_Pos 3
|
||
#define GPIO_INTCLR_PIN3_Msk (0x01 << GPIO_INTCLR_PIN3_Pos)
|
||
#define GPIO_INTCLR_PIN4_Pos 4
|
||
#define GPIO_INTCLR_PIN4_Msk (0x01 << GPIO_INTCLR_PIN4_Pos)
|
||
#define GPIO_INTCLR_PIN5_Pos 5
|
||
#define GPIO_INTCLR_PIN5_Msk (0x01 << GPIO_INTCLR_PIN5_Pos)
|
||
#define GPIO_INTCLR_PIN6_Pos 6
|
||
#define GPIO_INTCLR_PIN6_Msk (0x01 << GPIO_INTCLR_PIN6_Pos)
|
||
#define GPIO_INTCLR_PIN7_Pos 7
|
||
#define GPIO_INTCLR_PIN7_Msk (0x01 << GPIO_INTCLR_PIN7_Pos)
|
||
#define GPIO_INTCLR_PIN8_Pos 8
|
||
#define GPIO_INTCLR_PIN8_Msk (0x01 << GPIO_INTCLR_PIN8_Pos)
|
||
#define GPIO_INTCLR_PIN9_Pos 9
|
||
#define GPIO_INTCLR_PIN9_Msk (0x01 << GPIO_INTCLR_PIN9_Pos)
|
||
#define GPIO_INTCLR_PIN10_Pos 10
|
||
#define GPIO_INTCLR_PIN10_Msk (0x01 << GPIO_INTCLR_PIN10_Pos)
|
||
#define GPIO_INTCLR_PIN11_Pos 11
|
||
#define GPIO_INTCLR_PIN11_Msk (0x01 << GPIO_INTCLR_PIN11_Pos)
|
||
#define GPIO_INTCLR_PIN12_Pos 12
|
||
#define GPIO_INTCLR_PIN12_Msk (0x01 << GPIO_INTCLR_PIN12_Pos)
|
||
#define GPIO_INTCLR_PIN13_Pos 13
|
||
#define GPIO_INTCLR_PIN13_Msk (0x01 << GPIO_INTCLR_PIN13_Pos)
|
||
#define GPIO_INTCLR_PIN14_Pos 14
|
||
#define GPIO_INTCLR_PIN14_Msk (0x01 << GPIO_INTCLR_PIN14_Pos)
|
||
#define GPIO_INTCLR_PIN15_Pos 15
|
||
#define GPIO_INTCLR_PIN15_Msk (0x01 << GPIO_INTCLR_PIN15_Pos)
|
||
#define GPIO_INTCLR_PIN16_Pos 16
|
||
#define GPIO_INTCLR_PIN16_Msk (0x01 << GPIO_INTCLR_PIN16_Pos)
|
||
#define GPIO_INTCLR_PIN17_Pos 17
|
||
#define GPIO_INTCLR_PIN17_Msk (0x01 << GPIO_INTCLR_PIN17_Pos)
|
||
#define GPIO_INTCLR_PIN18_Pos 18
|
||
#define GPIO_INTCLR_PIN18_Msk (0x01 << GPIO_INTCLR_PIN18_Pos)
|
||
#define GPIO_INTCLR_PIN19_Pos 19
|
||
#define GPIO_INTCLR_PIN19_Msk (0x01 << GPIO_INTCLR_PIN19_Pos)
|
||
#define GPIO_INTCLR_PIN20_Pos 20
|
||
#define GPIO_INTCLR_PIN20_Msk (0x01 << GPIO_INTCLR_PIN20_Pos)
|
||
#define GPIO_INTCLR_PIN21_Pos 21
|
||
#define GPIO_INTCLR_PIN21_Msk (0x01 << GPIO_INTCLR_PIN21_Pos)
|
||
#define GPIO_INTCLR_PIN22_Pos 22
|
||
#define GPIO_INTCLR_PIN22_Msk (0x01 << GPIO_INTCLR_PIN22_Pos)
|
||
#define GPIO_INTCLR_PIN23_Pos 23
|
||
#define GPIO_INTCLR_PIN23_Msk (0x01 << GPIO_INTCLR_PIN23_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t LDVAL; //<2F><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>ʹ<EFBFBD>ܺ<EFBFBD><DCBA><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD>ֵ<EFBFBD><D6B5>ʼ<EFBFBD><CABC><EFBFBD>µݼ<C2B5><DDBC><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
__I uint32_t CVAL; //<2F><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ǰֵ<C7B0><D6B5>LDVAL-CVAL <20>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱʱ<CAB1><CAB1>
|
||
|
||
__IO uint32_t CTRL;
|
||
} TIMR_TypeDef;
|
||
|
||
|
||
#define TIMR_CTRL_EN_Pos 0 //<2F><>λ<EFBFBD><CEBB>1<EFBFBD><31><EFBFBD><EFBFBD>TIMR<4D><52>LDVAL<41><4C>ʼ<EFBFBD><CABC><EFBFBD>µݼ<C2B5><DDBC><EFBFBD><EFBFBD><EFBFBD>
|
||
#define TIMR_CTRL_EN_Msk (0x01 << TIMR_CTRL_EN_Pos)
|
||
#define TIMR_CTRL_CLKSRC_Pos 1 //ʱ<><CAB1>Դ<EFBFBD><D4B4>0 <20>ڲ<EFBFBD>ϵͳʱ<CDB3><CAB1> 1 <20>ⲿ<EFBFBD><E2B2BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define TIMR_CTRL_CLKSRC_Msk (0x01 << TIMR_CTRL_CLKSRC_Pos)
|
||
#define TIMR_CTRL_CASCADE_Pos 2 //1 TIMRx<52>ļ<EFBFBD><C4BC><EFBFBD>ʱ<EFBFBD><CAB1>ΪTIMRx-1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>
|
||
#define TIMR_CTRL_CASCADE_Msk (0x01 << TIMR_CTRL_CASCADE_Pos)
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t PCTRL; //Pulse Control<6F><6C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
|
||
|
||
__I uint32_t PCVAL; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ǰֵ
|
||
|
||
uint32_t RESERVED[2];
|
||
|
||
__IO uint32_t IE;
|
||
|
||
__IO uint32_t IF;
|
||
|
||
__IO uint32_t HALT;
|
||
} TIMRG_TypeDef;
|
||
|
||
|
||
#define TIMRG_PCTRL_EN_Pos 0 //<2F><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>32λ<32><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30>ʼ<EFBFBD><CABC><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD>
|
||
#define TIMRG_PCTRL_EN_Msk (0x01 << TIMRG_PCTRL_EN_Pos)
|
||
#define TIMRG_PCTRL_HIGH_Pos 1 //0 <20><><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD> 1 <20><><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD>
|
||
#define TIMRG_PCTRL_HIGH_Msk (0x01 << TIMRG_PCTRL_HIGH_Pos)
|
||
#define TIMRG_PCTRL_CLKSRC_Pos 2 //ʱ<><CAB1>Դ<EFBFBD><D4B4>0 <20>ڲ<EFBFBD>ϵͳʱ<CDB3><CAB1> 1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>پ<EFBFBD><D9BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define TIMRG_PCTRL_CLKSRC_Msk (0x01 << TIMRG_PCTRL_CLKSRC_Pos)
|
||
|
||
#define TIMRG_IE_TIMR0_Pos 0
|
||
#define TIMRG_IE_TIMR0_Msk (0x01 << TIMRG_IE_TIMR0_Pos)
|
||
#define TIMRG_IE_TIMR1_Pos 1
|
||
#define TIMRG_IE_TIMR1_Msk (0x01 << TIMRG_IE_TIMR1_Pos)
|
||
#define TIMRG_IE_TIMR2_Pos 2
|
||
#define TIMRG_IE_TIMR2_Msk (0x01 << TIMRG_IE_TIMR2_Pos)
|
||
#define TIMRG_IE_TIMR3_Pos 3
|
||
#define TIMRG_IE_TIMR3_Msk (0x01 << TIMRG_IE_TIMR3_Pos)
|
||
#define TIMRG_IE_TIMR4_Pos 4
|
||
#define TIMRG_IE_TIMR4_Msk (0x01 << TIMRG_IE_TIMR4_Pos)
|
||
#define TIMRG_IE_TIMR5_Pos 5
|
||
#define TIMRG_IE_TIMR5_Msk (0x01 << TIMRG_IE_TIMR5_Pos)
|
||
#define TIMRG_IE_PULSE_Pos 16
|
||
#define TIMRG_IE_PULSE_Msk (0x01 << TIMRG_IE_PULSE_Pos)
|
||
|
||
#define TIMRG_IF_TIMR0_Pos 0 //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define TIMRG_IF_TIMR0_Msk (0x01 << TIMRG_IF_TIMR0_Pos)
|
||
#define TIMRG_IF_TIMR1_Pos 1
|
||
#define TIMRG_IF_TIMR1_Msk (0x01 << TIMRG_IF_TIMR1_Pos)
|
||
#define TIMRG_IF_TIMR2_Pos 2
|
||
#define TIMRG_IF_TIMR2_Msk (0x01 << TIMRG_IF_TIMR2_Pos)
|
||
#define TIMRG_IF_TIMR3_Pos 3
|
||
#define TIMRG_IF_TIMR3_Msk (0x01 << TIMRG_IF_TIMR3_Pos)
|
||
#define TIMRG_IF_TIMR4_Pos 4
|
||
#define TIMRG_IF_TIMR4_Msk (0x01 << TIMRG_IF_TIMR4_Pos)
|
||
#define TIMRG_IF_TIMR5_Pos 5
|
||
#define TIMRG_IF_TIMR5_Msk (0x01 << TIMRG_IF_TIMR5_Pos)
|
||
#define TIMRG_IF_PULSE_Pos 16
|
||
#define TIMRG_IF_PULSE_Msk (0x01 << TIMRG_IF_PULSE_Pos)
|
||
|
||
#define TIMRG_HALT_TIMR0_Pos 0 //1 <20><>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>
|
||
#define TIMRG_HALT_TIMR0_Msk (0x01 << TIMRG_HALT_TIMR0_Pos)
|
||
#define TIMRG_HALT_TIMR1_Pos 1
|
||
#define TIMRG_HALT_TIMR1_Msk (0x01 << TIMRG_HALT_TIMR1_Pos)
|
||
#define TIMRG_HALT_TIMR2_Pos 2
|
||
#define TIMRG_HALT_TIMR2_Msk (0x01 << TIMRG_HALT_TIMR2_Pos)
|
||
#define TIMRG_HALT_TIMR3_Pos 3
|
||
#define TIMRG_HALT_TIMR3_Msk (0x01 << TIMRG_HALT_TIMR3_Pos)
|
||
#define TIMRG_HALT_TIMR4_Pos 4
|
||
#define TIMRG_HALT_TIMR4_Msk (0x01 << TIMRG_HALT_TIMR4_Pos)
|
||
#define TIMRG_HALT_TIMR5_Pos 5
|
||
#define TIMRG_HALT_TIMR5_Msk (0x01 << TIMRG_HALT_TIMR5_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t DATA;
|
||
|
||
__IO uint32_t CTRL;
|
||
|
||
__IO uint32_t BAUD;
|
||
|
||
__IO uint32_t FIFO;
|
||
|
||
__IO uint32_t LINCR;
|
||
|
||
union {
|
||
__IO uint32_t CTSCR;
|
||
|
||
__IO uint32_t RTSCR;
|
||
};
|
||
} UART_TypeDef;
|
||
|
||
|
||
#define UART_DATA_DATA_Pos 0
|
||
#define UART_DATA_DATA_Msk (0x1FF << UART_DATA_DATA_Pos)
|
||
#define UART_DATA_VALID_Pos 9 //<2F><>DATA<54>ֶ<EFBFBD><D6B6><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD>Ľ<EFBFBD><C4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>λӲ<CEBB><D3B2><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD>ݺ<EFBFBD><DDBA>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
|
||
#define UART_DATA_VALID_Msk (0x01 << UART_DATA_VALID_Pos)
|
||
#define UART_DATA_PAERR_Pos 10 //Parity Error
|
||
#define UART_DATA_PAERR_Msk (0x01 << UART_DATA_PAERR_Pos)
|
||
|
||
#define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 <20><><EFBFBD>ڷ<EFBFBD><DAB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 <20><><EFBFBD><EFBFBD>״̬<D7B4><CCAC>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD>
|
||
#define UART_CTRL_TXIDLE_Msk (0x01 << UART_CTRL_TXIDLE_Pos)
|
||
#define UART_CTRL_TXFF_Pos 1 //TX FIFO Full
|
||
#define UART_CTRL_TXFF_Msk (0x01 << UART_CTRL_TXFF_Pos)
|
||
#define UART_CTRL_TXIE_Pos 2 //TX <20>ж<EFBFBD>ʹ<EFBFBD><CAB9>: 1 TX FF <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||
#define UART_CTRL_TXIE_Msk (0x01 << UART_CTRL_TXIE_Pos)
|
||
#define UART_CTRL_RXNE_Pos 3 //RX FIFO Not Empty
|
||
#define UART_CTRL_RXNE_Msk (0x01 << UART_CTRL_RXNE_Pos)
|
||
#define UART_CTRL_RXIE_Pos 4 //RX <20>ж<EFBFBD>ʹ<EFBFBD><CAB9>: 1 RX FF <20><><EFBFBD><EFBFBD><EFBFBD>ݴﵽ<DDB4>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||
#define UART_CTRL_RXIE_Msk (0x01 << UART_CTRL_RXIE_Pos)
|
||
#define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflow<6F><77>д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define UART_CTRL_RXOV_Msk (0x01 << UART_CTRL_RXOV_Pos)
|
||
#define UART_CTRL_TXDOIE_Pos 6 //TX Done <20>ж<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD>ҷ<EFBFBD><D2B7>ͷ<EFBFBD><CDB7><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>ѽ<EFBFBD><D1BD><EFBFBD><EFBFBD><EFBFBD>һλ<D2BB><CEBB><EFBFBD>ͳ<EFBFBD>ȥ
|
||
#define UART_CTRL_TXDOIE_Msk (0x01 << UART_CTRL_TXDOIE_Pos)
|
||
#define UART_CTRL_EN_Pos 9
|
||
#define UART_CTRL_EN_Msk (0x01 << UART_CTRL_EN_Pos)
|
||
#define UART_CTRL_LOOP_Pos 10
|
||
#define UART_CTRL_LOOP_Msk (0x01 << UART_CTRL_LOOP_Pos)
|
||
#define UART_CTRL_BAUDEN_Pos 13 //<2F><><EFBFBD><EFBFBD>д1
|
||
#define UART_CTRL_BAUDEN_Msk (0x01 << UART_CTRL_BAUDEN_Pos)
|
||
#define UART_CTRL_TOIE_Pos 14 //TimeOut <20>ж<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD>յ<EFBFBD><D5B5>ϸ<EFBFBD><CFB8>ַ<EFBFBD><D6B7><EFBFBD><F3A3ACB3><EFBFBD> TOTIME/BAUDRAUD <20><>û<EFBFBD>н<EFBFBD><D0BD>յ<EFBFBD><D5B5>µ<EFBFBD><C2B5><EFBFBD><EFBFBD><EFBFBD>
|
||
#define UART_CTRL_TOIE_Msk (0x01 << UART_CTRL_TOIE_Pos)
|
||
#define UART_CTRL_BRKDET_Pos 15 //LIN Break Detect<63><74><EFBFBD><EFBFBD><EFBFBD>LIN Break<61><6B><EFBFBD><EFBFBD>RX<52><58><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD><E2B5BD><EFBFBD><EFBFBD>11λ<31>͵<EFBFBD>ƽ
|
||
#define UART_CTRL_BRKDET_Msk (0x01 << UART_CTRL_BRKDET_Pos)
|
||
#define UART_CTRL_BRKIE_Pos 16 //LIN Break Detect <20>ж<EFBFBD>ʹ<EFBFBD><CAB9>
|
||
#define UART_CTRL_BRKIE_Msk (0x01 << UART_CTRL_BRKIE_Pos)
|
||
#define UART_CTRL_GENBRK_Pos 17 //Generate LIN Break<61><6B><EFBFBD><EFBFBD><EFBFBD><EFBFBD>LIN Break
|
||
#define UART_CTRL_GENBRK_Msk (0x01 << UART_CTRL_GENBRK_Pos)
|
||
#define UART_CTRL_DATA9b_Pos 18 //1 9λ<39><CEBB><EFBFBD><EFBFBD>λ 0 8λ<38><CEBB><EFBFBD><EFBFBD>λ
|
||
#define UART_CTRL_DATA9b_Msk (0x01 << UART_CTRL_DATA9b_Pos)
|
||
#define UART_CTRL_PARITY_Pos 19 //000 <20><>У<EFBFBD><D0A3> 001 <20><>У<EFBFBD><D0A3> 011 żУ<C5BC><D0A3> 101 <20>̶<EFBFBD>Ϊ1 111 <20>̶<EFBFBD>Ϊ0
|
||
#define UART_CTRL_PARITY_Msk (0x07 << UART_CTRL_PARITY_Pos)
|
||
#define UART_CTRL_STOP2b_Pos 22 //1 2λֹͣλ 0 1λֹͣλ
|
||
#define UART_CTRL_STOP2b_Msk (0x03 << UART_CTRL_STOP2b_Pos)
|
||
#define UART_CTRL_TOTIME_Pos 24 //TimeOut ʱ<><CAB1> = TOTIME/(BAUDRAUD/10) <20><>
|
||
#define UART_CTRL_TOTIME_Msk (0xFFu<< UART_CTRL_TOTIME_Pos)
|
||
|
||
#define UART_BAUD_BAUD_Pos 0 //<2F><><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD> = SYS_Freq/16/BAUD - 1
|
||
#define UART_BAUD_BAUD_Msk (0x3FFF << UART_BAUD_BAUD_Pos)
|
||
#define UART_BAUD_TXD_Pos 14 //ͨ<><CDA8><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ֱ<EFBFBD>Ӷ<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>TXD<58><44><EFBFBD><EFBFBD><EFBFBD>ϵĵ<CFB5>ƽ
|
||
#define UART_BAUD_TXD_Msk (0x01 << UART_BAUD_TXD_Pos)
|
||
#define UART_BAUD_RXD_Pos 15 //ͨ<><CDA8><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ֱ<EFBFBD>Ӷ<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>RXD<58><44><EFBFBD><EFBFBD><EFBFBD>ϵĵ<CFB5>ƽ
|
||
#define UART_BAUD_RXD_Msk (0x01 << UART_BAUD_RXD_Pos)
|
||
#define UART_BAUD_RXTOIF_Pos 16 //<2F><><EFBFBD><EFBFBD>&<26><>ʱ<EFBFBD><CAB1><EFBFBD>жϱ<D0B6>־ = RXIF | TOIF
|
||
#define UART_BAUD_RXTOIF_Msk (0x01 << UART_BAUD_RXTOIF_Pos)
|
||
#define UART_BAUD_TXIF_Pos 17 //<2F><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־ = TXTHRF & TXIE
|
||
#define UART_BAUD_TXIF_Msk (0x01 << UART_BAUD_TXIF_Pos)
|
||
#define UART_BAUD_BRKIF_Pos 18 //LIN Break Detect <20>жϱ<D0B6>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD>LIN Breakʱ<6B><CAB1>BRKIE=1<><31><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>λ
|
||
#define UART_BAUD_BRKIF_Msk (0x01 << UART_BAUD_BRKIF_Pos)
|
||
#define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold Flag<61><67>RX FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD>ݴﵽ<DDB4>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RXLVL >= RXTHR<48><52>ʱӲ<CAB1><D3B2><EFBFBD><EFBFBD>1
|
||
#define UART_BAUD_RXTHRF_Msk (0x01 << UART_BAUD_RXTHRF_Pos)
|
||
#define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold Flag<61><67>TX FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>TXLVL <= TXTHR<48><52>ʱӲ<CAB1><D3B2><EFBFBD><EFBFBD>1
|
||
#define UART_BAUD_TXTHRF_Msk (0x01 << UART_BAUD_TXTHRF_Pos)
|
||
#define UART_BAUD_TOIF_Pos 21 //TimeOut <20>жϱ<D0B6>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD> TOTIME/BAUDRAUD <20><>û<EFBFBD>н<EFBFBD><D0BD>յ<EFBFBD><D5B5>µ<EFBFBD><C2B5><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>TOIE=1<><31><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>λ
|
||
#define UART_BAUD_TOIF_Msk (0x01 << UART_BAUD_TOIF_Pos)
|
||
#define UART_BAUD_RXIF_Pos 22 //<2F><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־ = RXTHRF & RXIE
|
||
#define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos)
|
||
#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable<6C><65>д1<D0B4><31><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>У<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
|
||
#define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos)
|
||
#define UART_BAUD_ABRBIT_Pos 24 //Auto Baudrate Bit<69><74><EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD><DABC>㲨<EFBFBD><E3B2A8><EFBFBD>ʵļ<CAB5><C4BC><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>0 1λ<31><CEBB>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼλ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>㲨<EFBFBD><E3B2A8><EFBFBD>ʣ<EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>Ͷ˷<CDB6><CBB7><EFBFBD>0xFF
|
||
// 1 2λ<32><CEBB>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼλ<CABC><CEBB>1λ<31><CEBB><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>㲨<EFBFBD><E3B2A8><EFBFBD>ʣ<EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>Ͷ˷<CDB6><CBB7><EFBFBD>0xFE
|
||
// 1 4λ<34><CEBB>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼλ<CABC><CEBB>3λ<33><CEBB><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>㲨<EFBFBD><E3B2A8><EFBFBD>ʣ<EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>Ͷ˷<CDB6><CBB7><EFBFBD>0xF8
|
||
// 1 8λ<38><CEBB>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼλ<CABC><CEBB>7λ<37><CEBB><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>㲨<EFBFBD><E3B2A8><EFBFBD>ʣ<EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>Ͷ˷<CDB6><CBB7><EFBFBD>0x80
|
||
#define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos)
|
||
#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error<6F><72>0 <20>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>У<D0A3>ɹ<EFBFBD> 1 <20>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Уʧ<D7BC><CAA7>
|
||
#define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos)
|
||
#define UART_BAUD_TXDOIF_Pos 27 //TX Done <20>жϱ<D0B6>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD>ҷ<EFBFBD><D2B7>ͷ<EFBFBD><CDB7><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>ѽ<EFBFBD><D1BD><EFBFBD><EFBFBD><EFBFBD>һλ<D2BB><CEBB><EFBFBD>ͳ<EFBFBD>ȥ
|
||
#define UART_BAUD_TXDOIF_Msk (0x01 << UART_BAUD_TXDOIF_Pos)
|
||
|
||
#define UART_FIFO_RXLVL_Pos 0 //RX FIFO Level<65><6C>RX FIFO <20><><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>
|
||
#define UART_FIFO_RXLVL_Msk (0xFF << UART_FIFO_RXLVL_Pos)
|
||
#define UART_FIFO_TXLVL_Pos 8 //TX FIFO Level<65><6C>TX FIFO <20><><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>
|
||
#define UART_FIFO_TXLVL_Msk (0xFF << UART_FIFO_TXLVL_Pos)
|
||
#define UART_FIFO_RXTHR_Pos 16 //RX FIFO Threshold<6C><64>RX<52>жϴ<D0B6><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ޣ<EFBFBD><DEA3>ж<EFBFBD>ʹ<EFBFBD><CAB9>ʱ RXLVL >= RXTHR <20><><EFBFBD><EFBFBD>RX<52>ж<EFBFBD>
|
||
#define UART_FIFO_RXTHR_Msk (0xFF << UART_FIFO_RXTHR_Pos)
|
||
#define UART_FIFO_TXTHR_Pos 24 //TX FIFO Threshold<6C><64>TX<54>жϴ<D0B6><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ޣ<EFBFBD><DEA3>ж<EFBFBD>ʹ<EFBFBD><CAB9>ʱ TXLVL <= TXTHR <20><><EFBFBD><EFBFBD>TX<54>ж<EFBFBD>
|
||
#define UART_FIFO_TXTHR_Msk (0xFFu<< UART_FIFO_TXTHR_Pos)
|
||
|
||
#define UART_LINCR_BRKDETIE_Pos 0 //<2F><><EFBFBD>LIN Break<61>ж<EFBFBD>ʹ<EFBFBD><CAB9>
|
||
#define UART_LINCR_BRKDETIE_Msk (0x01 << UART_LINCR_BRKDETIE_Pos)
|
||
#define UART_LINCR_BRKDETIF_Pos 1 //<2F><><EFBFBD>LIN Break<61>ж<EFBFBD>״̬
|
||
#define UART_LINCR_BRKDETIF_Msk (0x01 << UART_LINCR_BRKDETIF_Pos)
|
||
#define UART_LINCR_GENBRKIE_Pos 2 //<2F><><EFBFBD><EFBFBD>LIN Break<61><6B><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
|
||
#define UART_LINCR_GENBRKIE_Msk (0x01 << UART_LINCR_GENBRKIE_Pos)
|
||
#define UART_LINCR_GENBRKIF_Pos 3 //<2F><><EFBFBD><EFBFBD>LIN Break<61><6B><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>״̬
|
||
#define UART_LINCR_GENBRKIF_Msk (0x01 << UART_LINCR_GENBRKIF_Pos)
|
||
#define UART_LINCR_GENBRK_Pos 4 //<2F><><EFBFBD><EFBFBD>LIN Break<61><6B><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
|
||
#define UART_LINCR_GENBRK_Msk (0x01 << UART_LINCR_GENBRK_Pos)
|
||
|
||
#define UART_CTSCR_EN_Pos 0 //CTS<54><53><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
|
||
#define UART_CTSCR_EN_Msk (0x01 << UART_CTSCR_EN_Pos)
|
||
#define UART_CTSCR_POL_Pos 2 //CTS<54>źż<C5BA><C5BC>ԣ<EFBFBD>0 <20><><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>CTS<54><53><EFBFBD><EFBFBD>Ϊ<EFBFBD>ͱ<EFBFBD>ʾ<EFBFBD><CABE><EFBFBD>Է<EFBFBD><D4B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define UART_CTSCR_POL_Msk (0x01 << UART_CTSCR_POL_Pos)
|
||
#define UART_CTSCR_STAT_Pos 7 //CTS<54>źŵĵ<C5B5>ǰ״̬
|
||
#define UART_CTSCR_STAT_Msk (0x01 << UART_CTSCR_STAT_Pos)
|
||
|
||
#define UART_RTSCR_EN_Pos 1 //RTS<54><53><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
|
||
#define UART_RTSCR_EN_Msk (0x01 << UART_RTSCR_EN_Pos)
|
||
#define UART_RTSCR_POL_Pos 3 //RTS<54>źż<C5BA><C5BC><EFBFBD> 0 <20><><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>RTS<54><53><EFBFBD><EFBFBD>Ϊ<EFBFBD>ͱ<EFBFBD>ʾ<EFBFBD><CABE><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define UART_RTSCR_POL_Msk (0x01 << UART_RTSCR_POL_Pos)
|
||
#define UART_RTSCR_THR_Pos 4 //RTS<54><53><EFBFBD>صĴ<D8B5><C4B4><EFBFBD><EFBFBD><EFBFBD>ֵ 0 1<>ֽ<EFBFBD> 1 2<>ֽ<EFBFBD> 2 4<>ֽ<EFBFBD> 3 6<>ֽ<EFBFBD>
|
||
#define UART_RTSCR_THR_Msk (0x07 << UART_RTSCR_THR_Pos)
|
||
#define UART_RTSCR_STAT_Pos 8 //RTS<54>źŵĵ<C5B5>ǰ״̬
|
||
#define UART_RTSCR_STAT_Msk (0x01 << UART_RTSCR_STAT_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t CTRL;
|
||
|
||
__IO uint32_t DATA;
|
||
|
||
__IO uint32_t STAT;
|
||
|
||
__IO uint32_t IE;
|
||
|
||
__IO uint32_t IF;
|
||
} SPI_TypeDef;
|
||
|
||
|
||
#define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPI<50><49><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1> = SYS_Freq/pow(2, CLKDIV+2)
|
||
#define SPI_CTRL_CLKDIV_Msk (0x07 << SPI_CTRL_CLKDIV_Pos)
|
||
#define SPI_CTRL_EN_Pos 3
|
||
#define SPI_CTRL_EN_Msk (0x01 << SPI_CTRL_EN_Pos)
|
||
#define SPI_CTRL_SIZE_Pos 4 //Data Size Select, ȡֵ3--15<31><35><EFBFBD><EFBFBD>ʾ4--16λ
|
||
#define SPI_CTRL_SIZE_Msk (0x0F << SPI_CTRL_SIZE_Pos)
|
||
#define SPI_CTRL_CPHA_Pos 8 //0 <20><>SCLK<4C>ĵ<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ز<EFBFBD><D8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 <20><>SCLK<4C>ĵڶ<C4B5><DAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ز<EFBFBD><D8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define SPI_CTRL_CPHA_Msk (0x01 << SPI_CTRL_CPHA_Pos)
|
||
#define SPI_CTRL_CPOL_Pos 9 //0 <20><><EFBFBD><EFBFBD>״̬<D7B4><CCAC>SCLKΪ<4B>͵<EFBFBD>ƽ 1 <20><><EFBFBD><EFBFBD>״̬<D7B4><CCAC>SCLKΪ<4B>ߵ<EFBFBD>ƽ
|
||
#define SPI_CTRL_CPOL_Msk (0x01 << SPI_CTRL_CPOL_Pos)
|
||
#define SPI_CTRL_FFS_Pos 10 //Frame Format Select, 0 SPI 1 TI SSI 2 SPI 3 SPI
|
||
#define SPI_CTRL_FFS_Msk (0x03 << SPI_CTRL_FFS_Pos)
|
||
#define SPI_CTRL_MSTR_Pos 12 //Master, 1 <20><>ģʽ 0 <20><>ģʽ
|
||
#define SPI_CTRL_MSTR_Msk (0x01 << SPI_CTRL_MSTR_Pos)
|
||
#define SPI_CTRL_FAST_Pos 13 //1 SPI<50><49><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1> = SYS_Freq/2 0 SPI<50><49><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>SPI->CTRL.CLKDIV<49><56><EFBFBD><EFBFBD>
|
||
#define SPI_CTRL_FAST_Msk (0x01 << SPI_CTRL_FAST_Pos)
|
||
#define SPI_CTRL_FILTE_Pos 16 //1 <20><>SPI<50><49><EFBFBD><EFBFBD><EFBFBD>źŽ<C5BA><C5BD><EFBFBD>ȥ<EFBFBD><C8A5><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0 <20><>SPI<50><49><EFBFBD><EFBFBD><EFBFBD>źŲ<C5BA><C5B2><EFBFBD><EFBFBD><EFBFBD>ȥ<EFBFBD><C8A5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define SPI_CTRL_FILTE_Msk (0x01 << SPI_CTRL_FILTE_Pos)
|
||
#define SPI_CTRL_SSN_H_Pos 17 //0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SSNʼ<4E><CABC>Ϊ0 1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ÿ<EFBFBD>ַ<EFBFBD>֮<EFBFBD><D6AE><EFBFBD>ὫSSN<53><4E><EFBFBD>߰<EFBFBD><DFB0><EFBFBD>SCLK<4C><4B><EFBFBD><EFBFBD>
|
||
#define SPI_CTRL_SSN_H_Msk (0x01 << SPI_CTRL_SSN_H_Pos)
|
||
#define SPI_CTRL_TFCLR_Pos 24 //TX FIFO Clear
|
||
#define SPI_CTRL_TFCLR_Msk (0x01 << SPI_CTRL_TFCLR_Pos)
|
||
#define SPI_CTRL_RFCLR_Pos 25 //RX FIFO Clear
|
||
#define SPI_CTRL_RFCLR_Msk (0x01 << SPI_CTRL_RFCLR_Pos)
|
||
|
||
#define SPI_STAT_WTC_Pos 0 //Word Transmit Complete<74><65>ÿ<EFBFBD><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define SPI_STAT_WTC_Msk (0x01 << SPI_STAT_WTC_Pos)
|
||
#define SPI_STAT_TFE_Pos 1 //<2F><><EFBFBD><EFBFBD>FIFO Empty
|
||
#define SPI_STAT_TFE_Msk (0x01 << SPI_STAT_TFE_Pos)
|
||
#define SPI_STAT_TFNF_Pos 2 //<2F><><EFBFBD><EFBFBD>FIFO Not Full
|
||
#define SPI_STAT_TFNF_Msk (0x01 << SPI_STAT_TFNF_Pos)
|
||
#define SPI_STAT_RFNE_Pos 3 //<2F><><EFBFBD><EFBFBD>FIFO Not Empty
|
||
#define SPI_STAT_RFNE_Msk (0x01 << SPI_STAT_RFNE_Pos)
|
||
#define SPI_STAT_RFF_Pos 4 //<2F><><EFBFBD><EFBFBD>FIFO Full
|
||
#define SPI_STAT_RFF_Msk (0x01 << SPI_STAT_RFF_Pos)
|
||
#define SPI_STAT_RFOVF_Pos 5 //<2F><><EFBFBD><EFBFBD>FIFO Overflow
|
||
#define SPI_STAT_RFOVF_Msk (0x01 << SPI_STAT_RFOVF_Pos)
|
||
#define SPI_STAT_TFLVL_Pos 6 //<2F><><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD><DDB8><EFBFBD><EFBFBD><EFBFBD> 0 TFNF=0ʱ<30><CAB1>ʾFIFO<46><4F><EFBFBD><EFBFBD>8<EFBFBD><38><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD>TFNF=1ʱ<31><CAB1>ʾFIFO<46><4F><EFBFBD><EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1--7 FIFO<46><4F><EFBFBD><EFBFBD>1--7<><37><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define SPI_STAT_TFLVL_Msk (0x07 << SPI_STAT_TFLVL_Pos)
|
||
#define SPI_STAT_RFLVL_Pos 9 //<2F><><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD><DDB8><EFBFBD><EFBFBD><EFBFBD> 0 RFF=1ʱ<31><CAB1>ʾFIFO<46><4F><EFBFBD><EFBFBD>8<EFBFBD><38><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD> RFF=0ʱ<30><CAB1>ʾFIFO<46><4F><EFBFBD><EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1--7 FIFO<46><4F><EFBFBD><EFBFBD>1--7<><37><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define SPI_STAT_RFLVL_Msk (0x07 << SPI_STAT_RFLVL_Pos)
|
||
#define SPI_STAT_BUSY_Pos 15
|
||
#define SPI_STAT_BUSY_Msk (0x01 << SPI_STAT_BUSY_Pos)
|
||
|
||
#define SPI_IE_RFOVF_Pos 0
|
||
#define SPI_IE_RFOVF_Msk (0x01 << SPI_IE_RFOVF_Pos)
|
||
#define SPI_IE_RFF_Pos 1
|
||
#define SPI_IE_RFF_Msk (0x01 << SPI_IE_RFF_Pos)
|
||
#define SPI_IE_RFHF_Pos 2
|
||
#define SPI_IE_RFHF_Msk (0x01 << SPI_IE_RFHF_Pos)
|
||
#define SPI_IE_TFE_Pos 3
|
||
#define SPI_IE_TFE_Msk (0x01 << SPI_IE_TFE_Pos)
|
||
#define SPI_IE_TFHF_Pos 4
|
||
#define SPI_IE_TFHF_Msk (0x01 << SPI_IE_TFHF_Pos)
|
||
#define SPI_IE_WTC_Pos 8 //Word Transmit Complete
|
||
#define SPI_IE_WTC_Msk (0x01 << SPI_IE_WTC_Pos)
|
||
#define SPI_IE_FTC_Pos 9 //Frame Transmit Complete
|
||
#define SPI_IE_FTC_Msk (0x01 << SPI_IE_FTC_Pos)
|
||
|
||
#define SPI_IF_RFOVF_Pos 0 //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define SPI_IF_RFOVF_Msk (0x01 << SPI_IF_RFOVF_Pos)
|
||
#define SPI_IF_RFF_Pos 1
|
||
#define SPI_IF_RFF_Msk (0x01 << SPI_IF_RFF_Pos)
|
||
#define SPI_IF_RFHF_Pos 2
|
||
#define SPI_IF_RFHF_Msk (0x01 << SPI_IF_RFHF_Pos)
|
||
#define SPI_IF_TFE_Pos 3
|
||
#define SPI_IF_TFE_Msk (0x01 << SPI_IF_TFE_Pos)
|
||
#define SPI_IF_TFHF_Pos 4
|
||
#define SPI_IF_TFHF_Msk (0x01 << SPI_IF_TFHF_Pos)
|
||
#define SPI_IF_WTC_Pos 8 //Word Transmit Complete<74><65>ÿ<EFBFBD><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>1
|
||
#define SPI_IF_WTC_Msk (0x01 << SPI_IF_WTC_Pos)
|
||
#define SPI_IF_FTC_Pos 9 //Frame Transmit Complete<74><65>WTC<54><43>λʱ<CEBB><CAB1>TX FIFO<46>ǿյģ<D5B5><C4A3><EFBFBD>FTC<54><43>λ
|
||
#define SPI_IF_FTC_Msk (0x01 << SPI_IF_FTC_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t CLKDIV; //[15:0] <20>뽫<EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD>ʷֵ<CAB7>SCLƵ<4C>ʵ<EFBFBD>5<EFBFBD><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CLKDIV = SYS_Freq/5/SCL_Freq - 1
|
||
|
||
__IO uint32_t CTRL;
|
||
|
||
__IO uint32_t MSTDAT;
|
||
|
||
__IO uint32_t MSTCMD;
|
||
|
||
__IO uint32_t SLVCR;
|
||
|
||
__IO uint32_t SLVIF;
|
||
|
||
__IO uint32_t SLVTX;
|
||
|
||
__IO uint32_t SLVRX;
|
||
} I2C_TypeDef;
|
||
|
||
|
||
#define I2C_CTRL_MSTIE_Pos 6
|
||
#define I2C_CTRL_MSTIE_Msk (0x01 << I2C_CTRL_MSTIE_Pos)
|
||
#define I2C_CTRL_EN_Pos 7
|
||
#define I2C_CTRL_EN_Msk (0x01 << I2C_CTRL_EN_Pos)
|
||
|
||
#define I2C_MSTCMD_IF_Pos 0 //1 <20>еȴ<D0B5><C8B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<D0B6>д1<D0B4><31><EFBFBD><EFBFBD> <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>´<EFBFBD>λӲ<CEBB><D3B2><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>1<EFBFBD><31>һ<EFBFBD><D2BB><EFBFBD>ֽڴ<D6BD><DAB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2<><32><EFBFBD><EFBFBD><EFBFBD>߷<EFBFBD><DFB7><EFBFBD>Ȩ<EFBFBD><C8A8>ʧ
|
||
#define I2C_MSTCMD_IF_Msk (0x01 << I2C_MSTCMD_IF_Pos)
|
||
#define I2C_MSTCMD_TIP_Pos 1 //Transmission In Process
|
||
#define I2C_MSTCMD_TIP_Msk (0x01 << I2C_MSTCMD_TIP_Pos)
|
||
#define I2C_MSTCMD_ACK_Pos 3 //<2F><><EFBFBD><EFBFBD>ģʽ<C4A3>£<EFBFBD>0 <20><><EFBFBD><EFBFBD><EFBFBD>Ͷ˷<CDB6><CBB7><EFBFBD>ACK 1 <20><><EFBFBD><EFBFBD><EFBFBD>Ͷ˷<CDB6><CBB7><EFBFBD>NACK
|
||
#define I2C_MSTCMD_ACK_Msk (0x01 << I2C_MSTCMD_ACK_Pos)
|
||
#define I2C_MSTCMD_WR_Pos 4 // <20><>Slaveд<65><D0B4><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һλд1<D0B4><31><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
|
||
#define I2C_MSTCMD_WR_Msk (0x01 << I2C_MSTCMD_WR_Pos)
|
||
#define I2C_MSTCMD_RD_Pos 5 //д<><D0B4><EFBFBD><EFBFBD>Slave<76><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һλд1<D0B4><31><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD> <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>I2Cģ<43><C4A3>ʧȥ<CAA7><C8A5><EFBFBD>ߵķ<DFB5><C4B7><EFBFBD>ȨʱӲ<CAB1><D3B2><EFBFBD><EFBFBD>1
|
||
#define I2C_MSTCMD_RD_Msk (0x01 << I2C_MSTCMD_RD_Pos)
|
||
#define I2C_MSTCMD_BUSY_Pos 6 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>START֮<54><D6AE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һλ<D2BB><CEBB>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>STOP֮<50><D6AE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һλ<D2BB><CEBB>0
|
||
#define I2C_MSTCMD_BUSY_Msk (0x01 << I2C_MSTCMD_BUSY_Pos)
|
||
#define I2C_MSTCMD_STO_Pos 6 //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>STOP<4F><50><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
|
||
#define I2C_MSTCMD_STO_Msk (0x01 << I2C_MSTCMD_STO_Pos)
|
||
#define I2C_MSTCMD_RXACK_Pos 7 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD>Slave<76><65>ACKλ<4B><CEBB>0 <20>յ<EFBFBD>ACK 1 <20>յ<EFBFBD>NACK
|
||
#define I2C_MSTCMD_RXACK_Msk (0x01 << I2C_MSTCMD_RXACK_Pos)
|
||
#define I2C_MSTCMD_STA_Pos 7 //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>START<52><54><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
|
||
#define I2C_MSTCMD_STA_Msk (0x01 << I2C_MSTCMD_STA_Pos)
|
||
|
||
#define I2C_SLVCR_IM_RXEND_Pos 0 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϽ<D0B6>ֹ
|
||
#define I2C_SLVCR_IM_RXEND_Msk (0x01 << I2C_SLVCR_IM_RXEND_Pos)
|
||
#define I2C_SLVCR_IM_TXEND_Pos 1 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϽ<D0B6>ֹ
|
||
#define I2C_SLVCR_IM_TXEND_Msk (0x01 << I2C_SLVCR_IM_TXEND_Pos)
|
||
#define I2C_SLVCR_IM_STADET_Pos 2 //<2F><><EFBFBD><EFBFBD><E2B5BD>ʼ<EFBFBD>жϽ<D0B6>ֹ
|
||
#define I2C_SLVCR_IM_STADET_Msk (0x01 << I2C_SLVCR_IM_STADET_Pos)
|
||
#define I2C_SLVCR_IM_STODET_Pos 3 //<2F><><EFBFBD>ֹͣ<CDA3>жϽ<D0B6>ֹ
|
||
#define I2C_SLVCR_IM_STODET_Msk (0x01 << I2C_SLVCR_IM_STODET_Pos)
|
||
#define I2C_SLVCR_IM_RDREQ_Pos 4 //<2F><><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϽ<D0B6>ֹ
|
||
#define I2C_SLVCR_IM_RDREQ_Msk (0x01 << I2C_SLVCR_IM_RDREQ_Pos)
|
||
#define I2C_SLVCR_IM_WRREQ_Pos 5 //<2F><><EFBFBD>յ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD>жϽ<D0B6>ֹ
|
||
#define I2C_SLVCR_IM_WRREQ_Msk (0x01 << I2C_SLVCR_IM_WRREQ_Pos)
|
||
#define I2C_SLVCR_ADDR7b_Pos 16 //1 7λ<37><CEBB>ַģʽ 0 10λ<30><CEBB>ַģʽ
|
||
#define I2C_SLVCR_ADDR7b_Msk (0x01 << I2C_SLVCR_ADDR7b_Pos)
|
||
#define I2C_SLVCR_ACK_Pos 17 //1 Ӧ<><D3A6>ACK 0 Ӧ<><D3A6>NACK
|
||
#define I2C_SLVCR_ACK_Msk (0x01 << I2C_SLVCR_ACK_Pos)
|
||
#define I2C_SLVCR_SLAVE_Pos 18 //1 <20>ӻ<EFBFBD>ģʽ 0 <20><><EFBFBD><EFBFBD>ģʽ
|
||
#define I2C_SLVCR_SLAVE_Msk (0x01 << I2C_SLVCR_SLAVE_Pos)
|
||
#define I2C_SLVCR_DEBOUNCE_Pos 19 //ȥ<><C8A5><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
|
||
#define I2C_SLVCR_DEBOUNCE_Msk (0x01 << I2C_SLVCR_DEBOUNCE_Pos)
|
||
#define I2C_SLVCR_ADDR_Pos 20 //<2F>ӻ<EFBFBD><D3BB><EFBFBD>ַ
|
||
#define I2C_SLVCR_ADDR_Msk (0x3FF << I2C_SLVCR_ADDR_Pos)
|
||
|
||
#define I2C_SLVIF_RXEND_Pos 0 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־<EFBFBD><D6BE>д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define I2C_SLVIF_RXEND_Msk (0x01 << I2C_SLVIF_RXEND_Pos)
|
||
#define I2C_SLVIF_TXEND_Pos 1 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־<EFBFBD><D6BE>д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define I2C_SLVIF_TXEND_Msk (0x01 << I2C_SLVIF_TXEND_Pos)
|
||
#define I2C_SLVIF_STADET_Pos 2 //<2F><><EFBFBD><EFBFBD><E2B5BD>ʼ<EFBFBD>жϱ<D0B6>־<EFBFBD><D6BE>д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define I2C_SLVIF_STADET_Msk (0x01 << I2C_SLVIF_STADET_Pos)
|
||
#define I2C_SLVIF_STODET_Pos 3 //<2F><><EFBFBD>ֹͣ<CDA3>жϱ<D0B6>־<EFBFBD><D6BE>д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define I2C_SLVIF_STODET_Msk (0x01 << I2C_SLVIF_STODET_Pos)
|
||
#define I2C_SLVIF_RDREQ_Pos 4 //<2F><><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־
|
||
#define I2C_SLVIF_RDREQ_Msk (0x01 << I2C_SLVIF_RDREQ_Pos)
|
||
#define I2C_SLVIF_WRREQ_Pos 5 //<2F><><EFBFBD>յ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־
|
||
#define I2C_SLVIF_WRREQ_Msk (0x01 << I2C_SLVIF_WRREQ_Pos)
|
||
#define I2C_SLVIF_ACTIVE_Pos 6 //slave <20><>Ч
|
||
#define I2C_SLVIF_ACTIVE_Msk (0x01 << I2C_SLVIF_ACTIVE_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t CTRL;
|
||
|
||
__IO uint32_t START;
|
||
|
||
__IO uint32_t IE;
|
||
|
||
__IO uint32_t IF;
|
||
|
||
struct {
|
||
__IO uint32_t STAT;
|
||
|
||
__IO uint32_t DATA;
|
||
|
||
uint32_t RESERVED[2];
|
||
} CH[8];
|
||
|
||
__IO uint32_t CTRL1;
|
||
|
||
__IO uint32_t CTRL2;
|
||
|
||
uint32_t RESERVED[2];
|
||
|
||
__IO uint32_t CALIBSET;
|
||
|
||
__IO uint32_t CALIBEN;
|
||
} ADC_TypeDef;
|
||
|
||
|
||
#define ADC_CTRL_CH0_Pos 0 //ͨ<><CDA8>ѡ<EFBFBD><D1A1>
|
||
#define ADC_CTRL_CH0_Msk (0x01 << ADC_CTRL_CH0_Pos)
|
||
#define ADC_CTRL_CH1_Pos 1
|
||
#define ADC_CTRL_CH1_Msk (0x01 << ADC_CTRL_CH1_Pos)
|
||
#define ADC_CTRL_CH2_Pos 2
|
||
#define ADC_CTRL_CH2_Msk (0x01 << ADC_CTRL_CH2_Pos)
|
||
#define ADC_CTRL_CH3_Pos 3
|
||
#define ADC_CTRL_CH3_Msk (0x01 << ADC_CTRL_CH3_Pos)
|
||
#define ADC_CTRL_CH4_Pos 4
|
||
#define ADC_CTRL_CH4_Msk (0x01 << ADC_CTRL_CH4_Pos)
|
||
#define ADC_CTRL_CH5_Pos 5
|
||
#define ADC_CTRL_CH5_Msk (0x01 << ADC_CTRL_CH5_Pos)
|
||
#define ADC_CTRL_CH6_Pos 6
|
||
#define ADC_CTRL_CH6_Msk (0x01 << ADC_CTRL_CH6_Pos)
|
||
#define ADC_CTRL_CH7_Pos 7
|
||
#define ADC_CTRL_CH7_Msk (0x01 << ADC_CTRL_CH7_Pos)
|
||
#define ADC_CTRL_AVG_Pos 8 //0 1<>β<EFBFBD><CEB2><EFBFBD> 1 2<>β<EFBFBD><CEB2><EFBFBD>ȡƽ<C8A1><C6BD>ֵ 3 4<>β<EFBFBD><CEB2><EFBFBD>ȡƽ<C8A1><C6BD>ֵ 7 8<>β<EFBFBD><CEB2><EFBFBD>ȡƽ<C8A1><C6BD>ֵ 15 16<31>β<EFBFBD><CEB2><EFBFBD>ȡƽ<C8A1><C6BD>ֵ
|
||
#define ADC_CTRL_AVG_Msk (0x0F << ADC_CTRL_AVG_Pos)
|
||
#define ADC_CTRL_EN_Pos 12
|
||
#define ADC_CTRL_EN_Msk (0x01 << ADC_CTRL_EN_Pos)
|
||
#define ADC_CTRL_CONT_Pos 13 //Continuous conversion<6F><6E>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>0 <20><><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD>STARTλ<54>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>ֹͣת<D6B9><D7AA>
|
||
#define ADC_CTRL_CONT_Msk (0x01 << ADC_CTRL_CONT_Pos) // 1 <20><><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һֱ<D2BB><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>STARTλ
|
||
#define ADC_CTRL_TRIG_Pos 14 //ת<><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><CABD>0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA> 1 PWM<57><4D><EFBFBD><EFBFBD>
|
||
#define ADC_CTRL_TRIG_Msk (0x01 << ADC_CTRL_TRIG_Pos)
|
||
#define ADC_CTRL_CLKSRC_Pos 15 //0 VCO 1 HRC
|
||
#define ADC_CTRL_CLKSRC_Msk (0x01 << ADC_CTRL_CLKSRC_Pos)
|
||
#define ADC_CTRL_FIFOCLR_Pos 24 //[24] CH0_FIFO_CLR [25] CH1_FIFO_CLR ... [31] CH7_FIFO_CLR
|
||
#define ADC_CTRL_FIFOCLR_Msk (0xFFu<< ADC_CTRL_FIFOCLR_Pos)
|
||
|
||
#define ADC_START_GO_Pos 0 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>£<EFBFBD>д1<D0B4><31><EFBFBD><EFBFBD>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD><DAB5><EFBFBD>ģʽ<C4A3><CABD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD>㣬<EFBFBD><E3A3AC>ɨ<EFBFBD><C9A8>ģʽ<C4A3>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д0ֹͣADCת<43><D7AA>
|
||
#define ADC_START_GO_Msk (0x01 << ADC_START_GO_Pos)
|
||
#define ADC_START_BUSY_Pos 4
|
||
#define ADC_START_BUSY_Msk (0x01 << ADC_START_BUSY_Pos)
|
||
|
||
#define ADC_IE_CH0EOC_Pos 0 //End Of Convertion
|
||
#define ADC_IE_CH0EOC_Msk (0x01 << ADC_IE_CH0EOC_Pos)
|
||
#define ADC_IE_CH0OVF_Pos 1 //Overflow
|
||
#define ADC_IE_CH0OVF_Msk (0x01 << ADC_IE_CH0OVF_Pos)
|
||
#define ADC_IE_CH0HFULL_Pos 2 //FIFO Half Full
|
||
#define ADC_IE_CH0HFULL_Msk (0x01 << ADC_IE_CH0HFULL_Pos)
|
||
#define ADC_IE_CH0FULL_Pos 3 //FIFO Full
|
||
#define ADC_IE_CH0FULL_Msk (0x01 << ADC_IE_CH0FULL_Pos)
|
||
#define ADC_IE_CH1EOC_Pos 4
|
||
#define ADC_IE_CH1EOC_Msk (0x01 << ADC_IE_CH1EOC_Pos)
|
||
#define ADC_IE_CH1OVF_Pos 5
|
||
#define ADC_IE_CH1OVF_Msk (0x01 << ADC_IE_CH1OVF_Pos)
|
||
#define ADC_IE_CH1HFULL_Pos 6
|
||
#define ADC_IE_CH1HFULL_Msk (0x01 << ADC_IE_CH1HFULL_Pos)
|
||
#define ADC_IE_CH1FULL_Pos 7
|
||
#define ADC_IE_CH1FULL_Msk (0x01 << ADC_IE_CH1FULL_Pos)
|
||
#define ADC_IE_CH2EOC_Pos 8
|
||
#define ADC_IE_CH2EOC_Msk (0x01 << ADC_IE_CH2EOC_Pos)
|
||
#define ADC_IE_CH2OVF_Pos 9
|
||
#define ADC_IE_CH2OVF_Msk (0x01 << ADC_IE_CH2OVF_Pos)
|
||
#define ADC_IE_CH2HFULL_Pos 10
|
||
#define ADC_IE_CH2HFULL_Msk (0x01 << ADC_IE_CH2HFULL_Pos)
|
||
#define ADC_IE_CH2FULL_Pos 11
|
||
#define ADC_IE_CH2FULL_Msk (0x01 << ADC_IE_CH2FULL_Pos)
|
||
#define ADC_IE_CH3EOC_Pos 12
|
||
#define ADC_IE_CH3EOC_Msk (0x01 << ADC_IE_CH3EOC_Pos)
|
||
#define ADC_IE_CH3OVF_Pos 13
|
||
#define ADC_IE_CH3OVF_Msk (0x01 << ADC_IE_CH3OVF_Pos)
|
||
#define ADC_IE_CH3HFULL_Pos 14
|
||
#define ADC_IE_CH3HFULL_Msk (0x01 << ADC_IE_CH3HFULL_Pos)
|
||
#define ADC_IE_CH3FULL_Pos 15
|
||
#define ADC_IE_CH3FULL_Msk (0x01 << ADC_IE_CH3FULL_Pos)
|
||
#define ADC_IE_CH4EOC_Pos 16
|
||
#define ADC_IE_CH4EOC_Msk (0x01 << ADC_IE_CH4EOC_Pos)
|
||
#define ADC_IE_CH4OVF_Pos 17
|
||
#define ADC_IE_CH4OVF_Msk (0x01 << ADC_IE_CH4OVF_Pos)
|
||
#define ADC_IE_CH4HFULL_Pos 18
|
||
#define ADC_IE_CH4HFULL_Msk (0x01 << ADC_IE_CH4HFULL_Pos)
|
||
#define ADC_IE_CH4FULL_Pos 19
|
||
#define ADC_IE_CH4FULL_Msk (0x01 << ADC_IE_CH4FULL_Pos)
|
||
#define ADC_IE_CH5EOC_Pos 20
|
||
#define ADC_IE_CH5EOC_Msk (0x01 << ADC_IE_CH5EOC_Pos)
|
||
#define ADC_IE_CH5OVF_Pos 21
|
||
#define ADC_IE_CH5OVF_Msk (0x01 << ADC_IE_CH5OVF_Pos)
|
||
#define ADC_IE_CH5HFULL_Pos 22
|
||
#define ADC_IE_CH5HFULL_Msk (0x01 << ADC_IE_CH5HFULL_Pos)
|
||
#define ADC_IE_CH5FULL_Pos 23
|
||
#define ADC_IE_CH5FULL_Msk (0x01 << ADC_IE_CH5FULL_Pos)
|
||
#define ADC_IE_CH6EOC_Pos 24
|
||
#define ADC_IE_CH6EOC_Msk (0x01 << ADC_IE_CH6EOC_Pos)
|
||
#define ADC_IE_CH6OVF_Pos 25
|
||
#define ADC_IE_CH6OVF_Msk (0x01 << ADC_IE_CH6OVF_Pos)
|
||
#define ADC_IE_CH6HFULL_Pos 26
|
||
#define ADC_IE_CH6HFULL_Msk (0x01 << ADC_IE_CH6HFULL_Pos)
|
||
#define ADC_IE_CH6FULL_Pos 27
|
||
#define ADC_IE_CH6FULL_Msk (0x01 << ADC_IE_CH6FULL_Pos)
|
||
#define ADC_IE_CH7EOC_Pos 28
|
||
#define ADC_IE_CH7EOC_Msk (0x01 << ADC_IE_CH7EOC_Pos)
|
||
#define ADC_IE_CH7OVF_Pos 29
|
||
#define ADC_IE_CH7OVF_Msk (0x01 << ADC_IE_CH7OVF_Pos)
|
||
#define ADC_IE_CH7HFULL_Pos 30
|
||
#define ADC_IE_CH7HFULL_Msk (0x01 << ADC_IE_CH7HFULL_Pos)
|
||
#define ADC_IE_CH7FULL_Pos 31
|
||
#define ADC_IE_CH7FULL_Msk (0x01u<< ADC_IE_CH7FULL_Pos)
|
||
|
||
#define ADC_IF_CH0EOC_Pos 0 //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define ADC_IF_CH0EOC_Msk (0x01 << ADC_IF_CH0EOC_Pos)
|
||
#define ADC_IF_CH0OVF_Pos 1 //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define ADC_IF_CH0OVF_Msk (0x01 << ADC_IF_CH0OVF_Pos)
|
||
#define ADC_IF_CH0HFULL_Pos 2 //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define ADC_IF_CH0HFULL_Msk (0x01 << ADC_IF_CH0HFULL_Pos)
|
||
#define ADC_IF_CH0FULL_Pos 3 //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define ADC_IF_CH0FULL_Msk (0x01 << ADC_IF_CH0FULL_Pos)
|
||
#define ADC_IF_CH1EOC_Pos 4
|
||
#define ADC_IF_CH1EOC_Msk (0x01 << ADC_IF_CH1EOC_Pos)
|
||
#define ADC_IF_CH1OVF_Pos 5
|
||
#define ADC_IF_CH1OVF_Msk (0x01 << ADC_IF_CH1OVF_Pos)
|
||
#define ADC_IF_CH1HFULL_Pos 6
|
||
#define ADC_IF_CH1HFULL_Msk (0x01 << ADC_IF_CH1HFULL_Pos)
|
||
#define ADC_IF_CH1FULL_Pos 7
|
||
#define ADC_IF_CH1FULL_Msk (0x01 << ADC_IF_CH1FULL_Pos)
|
||
#define ADC_IF_CH2EOC_Pos 8
|
||
#define ADC_IF_CH2EOC_Msk (0x01 << ADC_IF_CH2EOC_Pos)
|
||
#define ADC_IF_CH2OVF_Pos 9
|
||
#define ADC_IF_CH2OVF_Msk (0x01 << ADC_IF_CH2OVF_Pos)
|
||
#define ADC_IF_CH2HFULL_Pos 10
|
||
#define ADC_IF_CH2HFULL_Msk (0x01 << ADC_IF_CH2HFULL_Pos)
|
||
#define ADC_IF_CH2FULL_Pos 11
|
||
#define ADC_IF_CH2FULL_Msk (0x01 << ADC_IF_CH2FULL_Pos)
|
||
#define ADC_IF_CH3EOC_Pos 12
|
||
#define ADC_IF_CH3EOC_Msk (0x01 << ADC_IF_CH3EOC_Pos)
|
||
#define ADC_IF_CH3OVF_Pos 13
|
||
#define ADC_IF_CH3OVF_Msk (0x01 << ADC_IF_CH3OVF_Pos)
|
||
#define ADC_IF_CH3HFULL_Pos 14
|
||
#define ADC_IF_CH3HFULL_Msk (0x01 << ADC_IF_CH3HFULL_Pos)
|
||
#define ADC_IF_CH3FULL_Pos 15
|
||
#define ADC_IF_CH3FULL_Msk (0x01 << ADC_IF_CH3FULL_Pos)
|
||
#define ADC_IF_CH4EOC_Pos 16
|
||
#define ADC_IF_CH4EOC_Msk (0x01 << ADC_IF_CH4EOC_Pos)
|
||
#define ADC_IF_CH4OVF_Pos 17
|
||
#define ADC_IF_CH4OVF_Msk (0x01 << ADC_IF_CH4OVF_Pos)
|
||
#define ADC_IF_CH4HFULL_Pos 18
|
||
#define ADC_IF_CH4HFULL_Msk (0x01 << ADC_IF_CH4HFULL_Pos)
|
||
#define ADC_IF_CH4FULL_Pos 19
|
||
#define ADC_IF_CH4FULL_Msk (0x01 << ADC_IF_CH4FULL_Pos)
|
||
#define ADC_IF_CH5EOC_Pos 20
|
||
#define ADC_IF_CH5EOC_Msk (0x01 << ADC_IF_CH5EOC_Pos)
|
||
#define ADC_IF_CH5OVF_Pos 21
|
||
#define ADC_IF_CH5OVF_Msk (0x01 << ADC_IF_CH5OVF_Pos)
|
||
#define ADC_IF_CH5HFULL_Pos 22
|
||
#define ADC_IF_CH5HFULL_Msk (0x01 << ADC_IF_CH5HFULL_Pos)
|
||
#define ADC_IF_CH5FULL_Pos 23
|
||
#define ADC_IF_CH5FULL_Msk (0x01 << ADC_IF_CH5FULL_Pos)
|
||
#define ADC_IF_CH6EOC_Pos 24
|
||
#define ADC_IF_CH6EOC_Msk (0x01 << ADC_IF_CH6EOC_Pos)
|
||
#define ADC_IF_CH6OVF_Pos 25
|
||
#define ADC_IF_CH6OVF_Msk (0x01 << ADC_IF_CH6OVF_Pos)
|
||
#define ADC_IF_CH6HFULL_Pos 26
|
||
#define ADC_IF_CH6HFULL_Msk (0x01 << ADC_IF_CH6HFULL_Pos)
|
||
#define ADC_IF_CH6FULL_Pos 27
|
||
#define ADC_IF_CH6FULL_Msk (0x01 << ADC_IF_CH6FULL_Pos)
|
||
#define ADC_IF_CH7EOC_Pos 28
|
||
#define ADC_IF_CH7EOC_Msk (0x01 << ADC_IF_CH7EOC_Pos)
|
||
#define ADC_IF_CH7OVF_Pos 29
|
||
#define ADC_IF_CH7OVF_Msk (0x01 << ADC_IF_CH7OVF_Pos)
|
||
#define ADC_IF_CH7HFULL_Pos 30
|
||
#define ADC_IF_CH7HFULL_Msk (0x01 << ADC_IF_CH7HFULL_Pos)
|
||
#define ADC_IF_CH7FULL_Pos 31
|
||
#define ADC_IF_CH7FULL_Msk (0x01 << ADC_IF_CH7FULL_Pos)
|
||
|
||
#define ADC_STAT_EOC_Pos 0 //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define ADC_STAT_EOC_Msk (0x01 << ADC_STAT_EOC_Pos)
|
||
#define ADC_STAT_OVF_Pos 1 //<2F><><EFBFBD><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define ADC_STAT_OVF_Msk (0x01 << ADC_STAT_OVF_Pos)
|
||
#define ADC_STAT_HFULL_Pos 2
|
||
#define ADC_STAT_HFULL_Msk (0x01 << ADC_STAT_HFULL_Pos)
|
||
#define ADC_STAT_FULL_Pos 3
|
||
#define ADC_STAT_FULL_Msk (0x01 << ADC_STAT_FULL_Pos)
|
||
#define ADC_STAT_EMPTY_Pos 4
|
||
#define ADC_STAT_EMPTY_Msk (0x01 << ADC_STAT_EMPTY_Pos)
|
||
|
||
#define ADC_CTRL1_RIN_Pos 4 //<2F><><EFBFBD><EFBFBD><EFBFBD>迹<EFBFBD><E8BFB9>0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 105K 2 90K 3 75K 4 60K 5 45K 6 30K 7 15K
|
||
#define ADC_CTRL1_RIN_Msk (0x07 << ADC_CTRL1_RIN_Pos)
|
||
|
||
#define ADC_CTRL2_RESET_Pos 0 //<2F><><EFBFBD>ֵ<EFBFBD>·<EFBFBD><C2B7>λ
|
||
#define ADC_CTRL2_RESET_Msk (0x01 << ADC_CTRL2_RESET_Pos)
|
||
#define ADC_CTRL2_ADCEVCM_Pos 1 //ADC External VCM<43><4D>ADC<44><43>PGA<47><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ƽѡ<C6BD><D1A1>
|
||
#define ADC_CTRL2_ADCEVCM_Msk (0x01 << ADC_CTRL2_ADCEVCM_Pos)
|
||
#define ADC_CTRL2_PGAIVCM_Pos 2 //PGA Internal VCM<43><4D>PGA<47><41><EFBFBD>빲ģ<EBB9B2><C4A3>ƽѡ<C6BD><D1A1>
|
||
#define ADC_CTRL2_PGAIVCM_Msk (0x01 << ADC_CTRL2_PGAIVCM_Pos)
|
||
#define ADC_CTRL2_PGAGAIN_Pos 3 //0 25.1dB 1 21.6dB 2 11.1dB 3 3.5dB 4 0dB(1.8V) 5 -2.9dB 6 -5.3dB
|
||
#define ADC_CTRL2_PGAGAIN_Msk (0x07 << ADC_CTRL2_PGAGAIN_Pos)
|
||
#define ADC_CTRL2_REFPOUT_Pos 23 //1 ADC <20>ڲ<EFBFBD> 1.2V REFP<46><50>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ⲿREFP<46><50><EFBFBD>ţ<EFBFBD><C5A3><EFBFBD><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ1.2V<EFBFBD>ⲿREFPʱ<EFBFBD><EFBFBD>ʡ<EFBFBD>ɱ<EFBFBD>
|
||
#define ADC_CTRL2_REFPOUT_Msk (0x01 << ADC_CTRL2_REFPOUT_Pos
|
||
#define ADC_CTRL2_CLKDIV_Pos 24 //ʱ<>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5>ֻ<EFBFBD><D6BB>ʱ<EFBFBD><CAB1>ԴΪHRCʱ<43><CAB1>Ч
|
||
#define ADC_CTRL2_CLKDIV_Msk (0x1F << ADC_CTRL2_CLKDIV_Pos)
|
||
#define ADC_CTRL2_PGAVCM_Pos 29
|
||
#define ADC_CTRL2_PGAVCM_Msk (0x07u<< ADC_CTRL2_PGAVCM_Pos)
|
||
|
||
#define ADC_CALIBSET_OFFSET_Pos 0
|
||
#define ADC_CALIBSET_OFFSET_Msk (0x1FF<< ADC_CALIBSET_OFFSET_Pos)
|
||
#define ADC_CALIBSET_K_Pos 16
|
||
#define ADC_CALIBSET_K_Msk (0x1FF<< ADC_CALIBSET_K_Pos)
|
||
|
||
#define ADC_CALIBEN_OFFSET_Pos 0
|
||
#define ADC_CALIBEN_OFFSET_Msk (0x01 << ADC_CALIBEN_OFFSET_Pos)
|
||
#define ADC_CALIBEN_K_Pos 1
|
||
#define ADC_CALIBEN_K_Msk (0x01 << ADC_CALIBEN_K_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t MODE; //0 <20><>ͨģʽ<C4A3><CABD>A<EFBFBD><41>B<EFBFBD><42>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
//1 <20><><EFBFBD><EFBFBD>ģʽ<C4A3><CABD>A<EFBFBD><41>B<EFBFBD><42>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PERA<52><41>HIGHA<48><41><EFBFBD>ƣ<EFBFBD>B·<42><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>A·<41><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>෴<EFBFBD><E0B7B4><EFBFBD><EFBFBD>DZA<5A><41>DZB<5A><42><EFBFBD><EFBFBD>A<EFBFBD><41>B·<42><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƴ<EFBFBD>ʱ<EFBFBD><CAB1>
|
||
//2 <20><><EFBFBD><EFBFBD>ģʽ<C4A3><CABD>ͬ<EFBFBD><CDAC>ͨģʽ<C4A3><CABD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ں<EFBFBD><DABA>Զ<EFBFBD>ֹͣ
|
||
//3 <20>Գ<EFBFBD>ģʽ<C4A3><CABD>A<EFBFBD><41>B<EFBFBD><42>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD><DAA3>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>Ƶ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD>һ<EFBFBD><D2BB>
|
||
//4 <20>Գƻ<D4B3><C6BB><EFBFBD>ģʽ<C4A3><CABD><EFBFBD>Գ<EFBFBD>ģʽ<C4A3>ͻ<EFBFBD><CDBB><EFBFBD>ģʽ<C4A3><CABD><EFBFBD>ۺ<EFBFBD>
|
||
|
||
__IO uint32_t PERA; //[15:0] <20><><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t HIGHA; //[15:0] <20>ߵ<EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
|
||
|
||
__IO uint32_t DZA; //[9:0] <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƴ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1>HIGHA
|
||
|
||
__IO uint32_t PERB;
|
||
|
||
__IO uint32_t HIGHB;
|
||
|
||
__IO uint32_t DZB;
|
||
|
||
__IO uint32_t INIOUT; //Init Output level<65><6C><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽ
|
||
} PWM_TypeDef;
|
||
|
||
|
||
#define PWM_INIOUT_PWMA_Pos 0
|
||
#define PWM_INIOUT_PWMA_Msk (0x01 << PWM_INIOUT_PWMA_Pos)
|
||
#define PWM_INIOUT_PWMB_Pos 1
|
||
#define PWM_INIOUT_PWMB_Msk (0x01 << PWM_INIOUT_PWMB_Pos)
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t FORCEH;
|
||
|
||
__IO uint32_t ADTRG0A;
|
||
__IO uint32_t ADTRG0B;
|
||
|
||
__IO uint32_t ADTRG1A;
|
||
__IO uint32_t ADTRG1B;
|
||
|
||
__IO uint32_t ADTRG2A;
|
||
__IO uint32_t ADTRG2B;
|
||
|
||
__IO uint32_t ADTRG3A;
|
||
__IO uint32_t ADTRG3B;
|
||
|
||
__IO uint32_t ADTRG4A;
|
||
__IO uint32_t ADTRG4B;
|
||
|
||
__IO uint32_t ADTRG5A;
|
||
__IO uint32_t ADTRG5B;
|
||
|
||
uint32_t RESERVED[3];
|
||
|
||
__IO uint32_t HALT; //ɲ<><C9B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t CHEN;
|
||
|
||
__IO uint32_t IE;
|
||
|
||
__IO uint32_t IF;
|
||
|
||
__IO uint32_t IM; //Interrupt Mask
|
||
|
||
__IO uint32_t IRS; //Interrupt Raw Stat
|
||
} PWMG_TypeDef;
|
||
|
||
|
||
#define PWMG_FORCEH_PWM0_Pos 0
|
||
#define PWMG_FORCEH_PWM0_Msk (0x01 << PWMG_FORCEH_PWM0_Pos)
|
||
#define PWMG_FORCEH_PWM1_Pos 1
|
||
#define PWMG_FORCEH_PWM1_Msk (0x01 << PWMG_FORCEH_PWM1_Pos)
|
||
#define PWMG_FORCEH_PWM2_Pos 2
|
||
#define PWMG_FORCEH_PWM2_Msk (0x01 << PWMG_FORCEH_PWM2_Pos)
|
||
#define PWMG_FORCEH_PWM3_Pos 3
|
||
#define PWMG_FORCEH_PWM3_Msk (0x01 << PWMG_FORCEH_PWM3_Pos)
|
||
#define PWMG_FORCEH_PWM4_Pos 4
|
||
#define PWMG_FORCEH_PWM4_Msk (0x01 << PWMG_FORCEH_PWM4_Pos)
|
||
#define PWMG_FORCEH_PWM5_Pos 5
|
||
#define PWMG_FORCEH_PWM5_Msk (0x01 << PWMG_FORCEH_PWM5_Pos)
|
||
|
||
#define PWMG_ADTRG_VALUE_Pos 0
|
||
#define PWMG_ADTRG_VALUE_Msk (0xFFFF << PWMG_ADTRG0A_VALUE_Pos)
|
||
#define PWMG_ADTRG_EVEN_Pos 16 //1 ż<><C5BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч 0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
|
||
#define PWMG_ADTRG_EVEN_Msk (0x01 << PWMG_ADTRG0A_EVEN_Pos)
|
||
#define PWMG_ADTRG_EN_Pos 17
|
||
#define PWMG_ADTRG_EN_Msk (0x01 << PWMG_ADTRG0A_EN_Pos)
|
||
|
||
#define PWMG_HALT_EN_Pos 0
|
||
#define PWMG_HALT_EN_Msk (0x01 << PWMG_HALT_EN_Pos)
|
||
#define PWMG_HALT_PWM0_Pos 1
|
||
#define PWMG_HALT_PWM0_Msk (0x01 << PWMG_HALT_PWM0_Pos)
|
||
#define PWMG_HALT_PWM1_Pos 2
|
||
#define PWMG_HALT_PWM1_Msk (0x01 << PWMG_HALT_PWM1_Pos)
|
||
#define PWMG_HALT_PWM2_Pos 3
|
||
#define PWMG_HALT_PWM2_Msk (0x01 << PWMG_HALT_PWM2_Pos)
|
||
#define PWMG_HALT_PWM3_Pos 4
|
||
#define PWMG_HALT_PWM3_Msk (0x01 << PWMG_HALT_PWM3_Pos)
|
||
#define PWMG_HALT_PWM4_Pos 5
|
||
#define PWMG_HALT_PWM4_Msk (0x01 << PWMG_HALT_PWM4_Pos)
|
||
#define PWMG_HALT_PWM5_Pos 6
|
||
#define PWMG_HALT_PWM5_Msk (0x01 << PWMG_HALT_PWM5_Pos)
|
||
#define PWMG_HALT_STOPCNT_Pos 7 //1 ɲ<><C9B2>ʱ<EFBFBD><CAB1>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>㣬ֹͣ<CDA3><D6B9><EFBFBD><EFBFBD> 0 ɲ<><C9B2>ʱ<EFBFBD><CAB1>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define PWMG_HALT_STOPCNT_Msk (0x01 << PWMG_HALT_STOPCNT_Pos)
|
||
#define PWMG_HALT_INLVL_Pos 8 //1 ɲ<><C9B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD>ƽ<EFBFBD><C6BD>Ч
|
||
#define PWMG_HALT_INLVL_Msk (0x01 << PWMG_HALT_INLVL_Pos)
|
||
#define PWMG_HALT_OUTLVL_Pos 9 //1 ɲ<><C9B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD>ƽ
|
||
#define PWMG_HALT_OUTLVL_Msk (0x01 << PWMG_HALT_OUTLVL_Pos)
|
||
#define PWMG_HALT_STAT_Pos 10 //1 <20><><EFBFBD><EFBFBD>ɲ<EFBFBD><C9B2>
|
||
#define PWMG_HALT_STAT_Msk (0x01 << PWMG_HALT_STAT_Pos)
|
||
|
||
#define PWMG_CHEN_PWM0A_Pos 0
|
||
#define PWMG_CHEN_PWM0A_Msk (0x01 << PWMG_CHEN_PWM0A_Pos)
|
||
#define PWMG_CHEN_PWM0B_Pos 1
|
||
#define PWMG_CHEN_PWM0B_Msk (0x01 << PWMG_CHEN_PWM0B_Pos)
|
||
#define PWMG_CHEN_PWM1A_Pos 2
|
||
#define PWMG_CHEN_PWM1A_Msk (0x01 << PWMG_CHEN_PWM1A_Pos)
|
||
#define PWMG_CHEN_PWM1B_Pos 3
|
||
#define PWMG_CHEN_PWM1B_Msk (0x01 << PWMG_CHEN_PWM1B_Pos)
|
||
#define PWMG_CHEN_PWM2A_Pos 4
|
||
#define PWMG_CHEN_PWM2A_Msk (0x01 << PWMG_CHEN_PWM2A_Pos)
|
||
#define PWMG_CHEN_PWM2B_Pos 5
|
||
#define PWMG_CHEN_PWM2B_Msk (0x01 << PWMG_CHEN_PWM2B_Pos)
|
||
#define PWMG_CHEN_PWM3A_Pos 6
|
||
#define PWMG_CHEN_PWM3A_Msk (0x01 << PWMG_CHEN_PWM3A_Pos)
|
||
#define PWMG_CHEN_PWM3B_Pos 7
|
||
#define PWMG_CHEN_PWM3B_Msk (0x01 << PWMG_CHEN_PWM3B_Pos)
|
||
#define PWMG_CHEN_PWM4A_Pos 8
|
||
#define PWMG_CHEN_PWM4A_Msk (0x01 << PWMG_CHEN_PWM4A_Pos)
|
||
#define PWMG_CHEN_PWM4B_Pos 9
|
||
#define PWMG_CHEN_PWM4B_Msk (0x01 << PWMG_CHEN_PWM4B_Pos)
|
||
#define PWMG_CHEN_PWM5A_Pos 10
|
||
#define PWMG_CHEN_PWM5A_Msk (0x01 << PWMG_CHEN_PWM5A_Pos)
|
||
#define PWMG_CHEN_PWM5B_Pos 11
|
||
#define PWMG_CHEN_PWM5B_Msk (0x01 << PWMG_CHEN_PWM5B_Pos)
|
||
|
||
|
||
#define PWMG_IE_NEWP0A_Pos 0
|
||
#define PWMG_IE_NEWP0A_Msk (0x01 << PWMG_IE_NEWP0A_Pos)
|
||
#define PWMG_IE_NEWP0B_Pos 1
|
||
#define PWMG_IE_NEWP0B_Msk (0x01 << PWMG_IE_NEWP0B_Pos)
|
||
#define PWMG_IE_NEWP1A_Pos 2
|
||
#define PWMG_IE_NEWP1A_Msk (0x01 << PWMG_IE_NEWP1A_Pos)
|
||
#define PWMG_IE_NEWP1B_Pos 3
|
||
#define PWMG_IE_NEWP1B_Msk (0x01 << PWMG_IE_NEWP1B_Pos)
|
||
#define PWMG_IE_NEWP2A_Pos 4
|
||
#define PWMG_IE_NEWP2A_Msk (0x01 << PWMG_IE_NEWP2A_Pos)
|
||
#define PWMG_IE_NEWP2B_Pos 5
|
||
#define PWMG_IE_NEWP2B_Msk (0x01 << PWMG_IE_NEWP2B_Pos)
|
||
#define PWMG_IE_NEWP3A_Pos 6
|
||
#define PWMG_IE_NEWP3A_Msk (0x01 << PWMG_IE_NEWP3A_Pos)
|
||
#define PWMG_IE_NEWP3B_Pos 7
|
||
#define PWMG_IE_NEWP3B_Msk (0x01 << PWMG_IE_NEWP3B_Pos)
|
||
#define PWMG_IE_NEWP4A_Pos 8
|
||
#define PWMG_IE_NEWP4A_Msk (0x01 << PWMG_IE_NEWP4A_Pos)
|
||
#define PWMG_IE_NEWP4B_Pos 9
|
||
#define PWMG_IE_NEWP4B_Msk (0x01 << PWMG_IE_NEWP4B_Pos)
|
||
#define PWMG_IE_NEWP5A_Pos 10
|
||
#define PWMG_IE_NEWP5A_Msk (0x01 << PWMG_IE_NEWP5A_Pos)
|
||
#define PWMG_IE_NEWP5B_Pos 11
|
||
#define PWMG_IE_NEWP5B_Msk (0x01 << PWMG_IE_NEWP5B_Pos)
|
||
#define PWMG_IE_HEND0A_Pos 12
|
||
#define PWMG_IE_HEND0A_Msk (0x01 << PWMG_IE_HEND0A_Pos)
|
||
#define PWMG_IE_HEND0B_Pos 13
|
||
#define PWMG_IE_HEND0B_Msk (0x01 << PWMG_IE_HEND0B_Pos)
|
||
#define PWMG_IE_HEND1A_Pos 14
|
||
#define PWMG_IE_HEND1A_Msk (0x01 << PWMG_IE_HEND1A_Pos)
|
||
#define PWMG_IE_HEND1B_Pos 15
|
||
#define PWMG_IE_HEND1B_Msk (0x01 << PWMG_IE_HEND1B_Pos)
|
||
#define PWMG_IE_HEND2A_Pos 16
|
||
#define PWMG_IE_HEND2A_Msk (0x01 << PWMG_IE_HEND2A_Pos)
|
||
#define PWMG_IE_HEND2B_Pos 17
|
||
#define PWMG_IE_HEND2B_Msk (0x01 << PWMG_IE_HEND2B_Pos)
|
||
#define PWMG_IE_HEND3A_Pos 18
|
||
#define PWMG_IE_HEND3A_Msk (0x01 << PWMG_IE_HEND3A_Pos)
|
||
#define PWMG_IE_HEND3B_Pos 19
|
||
#define PWMG_IE_HEND3B_Msk (0x01 << PWMG_IE_HEND3B_Pos)
|
||
#define PWMG_IE_HEND4A_Pos 20
|
||
#define PWMG_IE_HEND4A_Msk (0x01 << PWMG_IE_HEND4A_Pos)
|
||
#define PWMG_IE_HEND4B_Pos 21
|
||
#define PWMG_IE_HEND4B_Msk (0x01 << PWMG_IE_HEND4B_Pos)
|
||
#define PWMG_IE_HEND5A_Pos 22
|
||
#define PWMG_IE_HEND5A_Msk (0x01 << PWMG_IE_HEND5A_Pos)
|
||
#define PWMG_IE_HEND5B_Pos 23
|
||
#define PWMG_IE_HEND5B_Msk (0x01 << PWMG_IE_HEND5B_Pos)
|
||
#define PWMG_IE_HALT_Pos 24
|
||
#define PWMG_IE_HALT_Msk (0x01 << PWMG_IE_HALT_Pos)
|
||
|
||
#define PWMG_IF_NEWP0A_Pos 0
|
||
#define PWMG_IF_NEWP0A_Msk (0x01 << PWMG_IF_NEWP0A_Pos)
|
||
#define PWMG_IF_NEWP0B_Pos 1
|
||
#define PWMG_IF_NEWP0B_Msk (0x01 << PWMG_IF_NEWP0B_Pos)
|
||
#define PWMG_IF_NEWP1A_Pos 2
|
||
#define PWMG_IF_NEWP1A_Msk (0x01 << PWMG_IF_NEWP1A_Pos)
|
||
#define PWMG_IF_NEWP1B_Pos 3
|
||
#define PWMG_IF_NEWP1B_Msk (0x01 << PWMG_IF_NEWP1B_Pos)
|
||
#define PWMG_IF_NEWP2A_Pos 4
|
||
#define PWMG_IF_NEWP2A_Msk (0x01 << PWMG_IF_NEWP2A_Pos)
|
||
#define PWMG_IF_NEWP2B_Pos 5
|
||
#define PWMG_IF_NEWP2B_Msk (0x01 << PWMG_IF_NEWP2B_Pos)
|
||
#define PWMG_IF_NEWP3A_Pos 6
|
||
#define PWMG_IF_NEWP3A_Msk (0x01 << PWMG_IF_NEWP3A_Pos)
|
||
#define PWMG_IF_NEWP3B_Pos 7
|
||
#define PWMG_IF_NEWP3B_Msk (0x01 << PWMG_IF_NEWP3B_Pos)
|
||
#define PWMG_IF_NEWP4A_Pos 8
|
||
#define PWMG_IF_NEWP4A_Msk (0x01 << PWMG_IF_NEWP4A_Pos)
|
||
#define PWMG_IF_NEWP4B_Pos 9
|
||
#define PWMG_IF_NEWP4B_Msk (0x01 << PWMG_IF_NEWP4B_Pos)
|
||
#define PWMG_IF_NEWP5A_Pos 10
|
||
#define PWMG_IF_NEWP5A_Msk (0x01 << PWMG_IF_NEWP5A_Pos)
|
||
#define PWMG_IF_NEWP5B_Pos 11
|
||
#define PWMG_IF_NEWP5B_Msk (0x01 << PWMG_IF_NEWP5B_Pos)
|
||
#define PWMG_IF_HEND0A_Pos 12
|
||
#define PWMG_IF_HEND0A_Msk (0x01 << PWMG_IF_HEND0A_Pos)
|
||
#define PWMG_IF_HEND0B_Pos 13
|
||
#define PWMG_IF_HEND0B_Msk (0x01 << PWMG_IF_HEND0B_Pos)
|
||
#define PWMG_IF_HEND1A_Pos 14
|
||
#define PWMG_IF_HEND1A_Msk (0x01 << PWMG_IF_HEND1A_Pos)
|
||
#define PWMG_IF_HEND1B_Pos 15
|
||
#define PWMG_IF_HEND1B_Msk (0x01 << PWMG_IF_HEND1B_Pos)
|
||
#define PWMG_IF_HEND2A_Pos 16
|
||
#define PWMG_IF_HEND2A_Msk (0x01 << PWMG_IF_HEND2A_Pos)
|
||
#define PWMG_IF_HEND2B_Pos 17
|
||
#define PWMG_IF_HEND2B_Msk (0x01 << PWMG_IF_HEND2B_Pos)
|
||
#define PWMG_IF_HEND3A_Pos 18
|
||
#define PWMG_IF_HEND3A_Msk (0x01 << PWMG_IF_HEND3A_Pos)
|
||
#define PWMG_IF_HEND3B_Pos 19
|
||
#define PWMG_IF_HEND3B_Msk (0x01 << PWMG_IF_HEND3B_Pos)
|
||
#define PWMG_IF_HEND4A_Pos 20
|
||
#define PWMG_IF_HEND4A_Msk (0x01 << PWMG_IF_HEND4A_Pos)
|
||
#define PWMG_IF_HEND4B_Pos 21
|
||
#define PWMG_IF_HEND4B_Msk (0x01 << PWMG_IF_HEND4B_Pos)
|
||
#define PWMG_IF_HEND5A_Pos 22
|
||
#define PWMG_IF_HEND5A_Msk (0x01 << PWMG_IF_HEND5A_Pos)
|
||
#define PWMG_IF_HEND5B_Pos 23
|
||
#define PWMG_IF_HEND5B_Msk (0x01 << PWMG_IF_HEND5B_Pos)
|
||
#define PWMG_IF_HALT_Pos 24
|
||
#define PWMG_IF_HALT_Msk (0x01 << PWMG_IF_HALT_Pos)
|
||
|
||
#define PWMG_IM_NEWP0A_Pos 0 //Interrupt Mask
|
||
#define PWMG_IM_NEWP0A_Msk (0x01 << PWMG_IM_NEWP0A_Pos)
|
||
#define PWMG_IM_NEWP0B_Pos 1
|
||
#define PWMG_IM_NEWP0B_Msk (0x01 << PWMG_IM_NEWP0B_Pos)
|
||
#define PWMG_IM_NEWP1A_Pos 2
|
||
#define PWMG_IM_NEWP1A_Msk (0x01 << PWMG_IM_NEWP1A_Pos)
|
||
#define PWMG_IM_NEWP1B_Pos 3
|
||
#define PWMG_IM_NEWP1B_Msk (0x01 << PWMG_IM_NEWP1B_Pos)
|
||
#define PWMG_IM_NEWP2A_Pos 4
|
||
#define PWMG_IM_NEWP2A_Msk (0x01 << PWMG_IM_NEWP2A_Pos)
|
||
#define PWMG_IM_NEWP2B_Pos 5
|
||
#define PWMG_IM_NEWP2B_Msk (0x01 << PWMG_IM_NEWP2B_Pos)
|
||
#define PWMG_IM_NEWP3A_Pos 6
|
||
#define PWMG_IM_NEWP3A_Msk (0x01 << PWMG_IM_NEWP3A_Pos)
|
||
#define PWMG_IM_NEWP3B_Pos 7
|
||
#define PWMG_IM_NEWP3B_Msk (0x01 << PWMG_IM_NEWP3B_Pos)
|
||
#define PWMG_IM_NEWP4A_Pos 8
|
||
#define PWMG_IM_NEWP4A_Msk (0x01 << PWMG_IM_NEWP4A_Pos)
|
||
#define PWMG_IM_NEWP4B_Pos 9
|
||
#define PWMG_IM_NEWP4B_Msk (0x01 << PWMG_IM_NEWP4B_Pos)
|
||
#define PWMG_IM_NEWP5A_Pos 10
|
||
#define PWMG_IM_NEWP5A_Msk (0x01 << PWMG_IM_NEWP5A_Pos)
|
||
#define PWMG_IM_NEWP5B_Pos 11
|
||
#define PWMG_IM_NEWP5B_Msk (0x01 << PWMG_IM_NEWP5B_Pos)
|
||
#define PWMG_IM_HEND0A_Pos 12
|
||
#define PWMG_IM_HEND0A_Msk (0x01 << PWMG_IM_HEND0A_Pos)
|
||
#define PWMG_IM_HEND0B_Pos 13
|
||
#define PWMG_IM_HEND0B_Msk (0x01 << PWMG_IM_HEND0B_Pos)
|
||
#define PWMG_IM_HEND1A_Pos 14
|
||
#define PWMG_IM_HEND1A_Msk (0x01 << PWMG_IM_HEND1A_Pos)
|
||
#define PWMG_IM_HEND1B_Pos 15
|
||
#define PWMG_IM_HEND1B_Msk (0x01 << PWMG_IM_HEND1B_Pos)
|
||
#define PWMG_IM_HEND2A_Pos 16
|
||
#define PWMG_IM_HEND2A_Msk (0x01 << PWMG_IM_HEND2A_Pos)
|
||
#define PWMG_IM_HEND2B_Pos 17
|
||
#define PWMG_IM_HEND2B_Msk (0x01 << PWMG_IM_HEND2B_Pos)
|
||
#define PWMG_IM_HEND3A_Pos 18
|
||
#define PWMG_IM_HEND3A_Msk (0x01 << PWMG_IM_HEND3A_Pos)
|
||
#define PWMG_IM_HEND3B_Pos 19
|
||
#define PWMG_IM_HEND3B_Msk (0x01 << PWMG_IM_HEND3B_Pos)
|
||
#define PWMG_IM_HEND4A_Pos 20
|
||
#define PWMG_IM_HEND4A_Msk (0x01 << PWMG_IM_HEND4A_Pos)
|
||
#define PWMG_IM_HEND4B_Pos 21
|
||
#define PWMG_IM_HEND4B_Msk (0x01 << PWMG_IM_HEND4B_Pos)
|
||
#define PWMG_IM_HEND5A_Pos 22
|
||
#define PWMG_IM_HEND5A_Msk (0x01 << PWMG_IM_HEND5A_Pos)
|
||
#define PWMG_IM_HEND5B_Pos 23
|
||
#define PWMG_IM_HEND5B_Msk (0x01 << PWMG_IM_HEND5B_Pos)
|
||
#define PWMG_IM_HALT_Pos 24
|
||
#define PWMG_IM_HALT_Msk (0x01 << PWMG_IM_HALT_Pos)
|
||
|
||
#define PWMG_IRS_NEWP0A_Pos 0 //Interrupt Raw State
|
||
#define PWMG_IRS_NEWP0A_Msk (0x01 << PWMG_IRS_NEWP0A_Pos)
|
||
#define PWMG_IRS_NEWP0B_Pos 1
|
||
#define PWMG_IRS_NEWP0B_Msk (0x01 << PWMG_IRS_NEWP0B_Pos)
|
||
#define PWMG_IRS_NEWP1A_Pos 2
|
||
#define PWMG_IRS_NEWP1A_Msk (0x01 << PWMG_IRS_NEWP1A_Pos)
|
||
#define PWMG_IRS_NEWP1B_Pos 3
|
||
#define PWMG_IRS_NEWP1B_Msk (0x01 << PWMG_IRS_NEWP1B_Pos)
|
||
#define PWMG_IRS_NEWP2A_Pos 4
|
||
#define PWMG_IRS_NEWP2A_Msk (0x01 << PWMG_IRS_NEWP2A_Pos)
|
||
#define PWMG_IRS_NEWP2B_Pos 5
|
||
#define PWMG_IRS_NEWP2B_Msk (0x01 << PWMG_IRS_NEWP2B_Pos)
|
||
#define PWMG_IRS_NEWP3A_Pos 6
|
||
#define PWMG_IRS_NEWP3A_Msk (0x01 << PWMG_IRS_NEWP3A_Pos)
|
||
#define PWMG_IRS_NEWP3B_Pos 7
|
||
#define PWMG_IRS_NEWP3B_Msk (0x01 << PWMG_IRS_NEWP3B_Pos)
|
||
#define PWMG_IRS_NEWP4A_Pos 8
|
||
#define PWMG_IRS_NEWP4A_Msk (0x01 << PWMG_IRS_NEWP4A_Pos)
|
||
#define PWMG_IRS_NEWP4B_Pos 9
|
||
#define PWMG_IRS_NEWP4B_Msk (0x01 << PWMG_IRS_NEWP4B_Pos)
|
||
#define PWMG_IRS_NEWP5A_Pos 10
|
||
#define PWMG_IRS_NEWP5A_Msk (0x01 << PWMG_IRS_NEWP5A_Pos)
|
||
#define PWMG_IRS_NEWP5B_Pos 11
|
||
#define PWMG_IRS_NEWP5B_Msk (0x01 << PWMG_IRS_NEWP5B_Pos)
|
||
#define PWMG_IRS_HEND0A_Pos 12
|
||
#define PWMG_IRS_HEND0A_Msk (0x01 << PWMG_IRS_HEND0A_Pos)
|
||
#define PWMG_IRS_HEND0B_Pos 13
|
||
#define PWMG_IRS_HEND0B_Msk (0x01 << PWMG_IRS_HEND0B_Pos)
|
||
#define PWMG_IRS_HEND1A_Pos 14
|
||
#define PWMG_IRS_HEND1A_Msk (0x01 << PWMG_IRS_HEND1A_Pos)
|
||
#define PWMG_IRS_HEND1B_Pos 15
|
||
#define PWMG_IRS_HEND1B_Msk (0x01 << PWMG_IRS_HEND1B_Pos)
|
||
#define PWMG_IRS_HEND2A_Pos 16
|
||
#define PWMG_IRS_HEND2A_Msk (0x01 << PWMG_IRS_HEND2A_Pos)
|
||
#define PWMG_IRS_HEND2B_Pos 17
|
||
#define PWMG_IRS_HEND2B_Msk (0x01 << PWMG_IRS_HEND2B_Pos)
|
||
#define PWMG_IRS_HEND3A_Pos 18
|
||
#define PWMG_IRS_HEND3A_Msk (0x01 << PWMG_IRS_HEND3A_Pos)
|
||
#define PWMG_IRS_HEND3B_Pos 19
|
||
#define PWMG_IRS_HEND3B_Msk (0x01 << PWMG_IRS_HEND3B_Pos)
|
||
#define PWMG_IRS_HEND4A_Pos 20
|
||
#define PWMG_IRS_HEND4A_Msk (0x01 << PWMG_IRS_HEND4A_Pos)
|
||
#define PWMG_IRS_HEND4B_Pos 21
|
||
#define PWMG_IRS_HEND4B_Msk (0x01 << PWMG_IRS_HEND4B_Pos)
|
||
#define PWMG_IRS_HEND5A_Pos 22
|
||
#define PWMG_IRS_HEND5A_Msk (0x01 << PWMG_IRS_HEND5A_Pos)
|
||
#define PWMG_IRS_HEND5B_Pos 23
|
||
#define PWMG_IRS_HEND5B_Msk (0x01 << PWMG_IRS_HEND5B_Pos)
|
||
#define PWMG_IRS_HALT_Pos 24
|
||
#define PWMG_IRS_HALT_Msk (0x01 << PWMG_IRS_HALT_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t EN; //[0] ENABLE
|
||
|
||
__IO uint32_t IE; //ֻ<><D6BB>Ϊ1ʱ<31><CAB1>IF[CHx]<5D><>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ܱ<EFBFBD>Ϊ1<CEAA><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һֱ<D2BB><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0
|
||
|
||
__IO uint32_t IM; //<2F><>Ϊ1ʱ<31><CAB1><EFBFBD><EFBFBD>ʹIF[CHx]Ϊ1<CEAA><31>dma_intҲ<74><D2B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˱<EFBFBD>1
|
||
|
||
__IO uint32_t IF; //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
|
||
uint32_t RESERVED[12];
|
||
|
||
struct {
|
||
__IO uint32_t CR;
|
||
|
||
__IO uint32_t AM; //Adress Mode
|
||
|
||
__IO uint32_t SRC;
|
||
|
||
__IO uint32_t SRCSGADDR1; //ֻ<><D6BB>Scatter Gatherģʽ<C4A3><CABD>ʹ<EFBFBD><CAB9>
|
||
|
||
__IO uint32_t SRCSGADDR2; //ֻ<><D6BB>Scatter Gatherģʽ<C4A3><CABD>ʹ<EFBFBD><CAB9>
|
||
|
||
__IO uint32_t SRCSGADDR3; //ֻ<><D6BB>Scatter Gatherģʽ<C4A3><CABD>ʹ<EFBFBD><CAB9>
|
||
|
||
__IO uint32_t SRCSGLEN; //ֻ<><D6BB>Scatter Gatherģʽ<C4A3><CABD>ʹ<EFBFBD><CAB9>
|
||
|
||
__IO uint32_t DST;
|
||
|
||
__IO uint32_t DSTSGADDR1; //ֻ<><D6BB>Scatter Gatherģʽ<C4A3><CABD>ʹ<EFBFBD><CAB9>
|
||
|
||
__IO uint32_t DSTSGADDR2; //ֻ<><D6BB>Scatter Gatherģʽ<C4A3><CABD>ʹ<EFBFBD><CAB9>
|
||
|
||
__IO uint32_t DSTSGADDR3; //ֻ<><D6BB>Scatter Gatherģʽ<C4A3><CABD>ʹ<EFBFBD><CAB9>
|
||
|
||
__IO uint32_t DSTSGLEN; //ֻ<><D6BB>Scatter Gatherģʽ<C4A3><CABD>ʹ<EFBFBD><CAB9>
|
||
|
||
uint32_t RESERVED[4];
|
||
} CH[3];
|
||
} DMA_TypeDef;
|
||
|
||
|
||
#define DMA_IE_CH0_Pos 0
|
||
#define DMA_IE_CH0_Msk (0x01 << DMA_IE_CH0_Pos)
|
||
#define DMA_IE_CH1_Pos 1
|
||
#define DMA_IE_CH1_Msk (0x01 << DMA_IE_CH1_Pos)
|
||
#define DMA_IE_CH2_Pos 2
|
||
#define DMA_IE_CH2_Msk (0x01 << DMA_IE_CH2_Pos)
|
||
#define DMA_IE_CH3_Pos 3
|
||
#define DMA_IE_CH3_Msk (0x01 << DMA_IE_CH3_Pos)
|
||
#define DMA_IE_CH4_Pos 4
|
||
#define DMA_IE_CH4_Msk (0x01 << DMA_IE_CH4_Pos)
|
||
#define DMA_IE_CH5_Pos 5
|
||
#define DMA_IE_CH5_Msk (0x01 << DMA_IE_CH5_Pos)
|
||
#define DMA_IE_CH6_Pos 6
|
||
#define DMA_IE_CH6_Msk (0x01 << DMA_IE_CH6_Pos)
|
||
#define DMA_IE_CH7_Pos 7
|
||
#define DMA_IE_CH7_Msk (0x01 << DMA_IE_CH7_Pos)
|
||
|
||
#define DMA_IM_CH0_Pos 0
|
||
#define DMA_IM_CH0_Msk (0x01 << DMA_IM_CH0_Pos)
|
||
#define DMA_IM_CH1_Pos 1
|
||
#define DMA_IM_CH1_Msk (0x01 << DMA_IM_CH1_Pos)
|
||
#define DMA_IM_CH2_Pos 2
|
||
#define DMA_IM_CH2_Msk (0x01 << DMA_IM_CH2_Pos)
|
||
#define DMA_IM_CH3_Pos 3
|
||
#define DMA_IM_CH3_Msk (0x01 << DMA_IM_CH3_Pos)
|
||
#define DMA_IM_CH4_Pos 4
|
||
#define DMA_IM_CH4_Msk (0x01 << DMA_IM_CH4_Pos)
|
||
#define DMA_IM_CH5_Pos 5
|
||
#define DMA_IM_CH5_Msk (0x01 << DMA_IM_CH5_Pos)
|
||
#define DMA_IM_CH6_Pos 6
|
||
#define DMA_IM_CH6_Msk (0x01 << DMA_IM_CH6_Pos)
|
||
#define DMA_IM_CH7_Pos 7
|
||
#define DMA_IM_CH7_Msk (0x01 << DMA_IM_CH7_Pos)
|
||
|
||
#define DMA_IF_CH0_Pos 0
|
||
#define DMA_IF_CH0_Msk (0x01 << DMA_IF_CH0_Pos)
|
||
#define DMA_IF_CH1_Pos 1
|
||
#define DMA_IF_CH1_Msk (0x01 << DMA_IF_CH1_Pos)
|
||
#define DMA_IF_CH2_Pos 2
|
||
#define DMA_IF_CH2_Msk (0x01 << DMA_IF_CH2_Pos)
|
||
#define DMA_IF_CH3_Pos 3
|
||
#define DMA_IF_CH3_Msk (0x01 << DMA_IF_CH3_Pos)
|
||
#define DMA_IF_CH4_Pos 4
|
||
#define DMA_IF_CH4_Msk (0x01 << DMA_IF_CH4_Pos)
|
||
#define DMA_IF_CH5_Pos 5
|
||
#define DMA_IF_CH5_Msk (0x01 << DMA_IF_CH5_Pos)
|
||
#define DMA_IF_CH6_Pos 6
|
||
#define DMA_IF_CH6_Msk (0x01 << DMA_IF_CH6_Pos)
|
||
#define DMA_IF_CH7_Pos 7
|
||
#define DMA_IF_CH7_Msk (0x01 << DMA_IF_CH7_Pos)
|
||
|
||
#define DMA_CR_LEN_Pos 0 //<2F><>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܳ<EFBFBD><DCB3>ȣ<EFBFBD>0<EFBFBD><30>Ӧ1<D3A6>ֽڣ<D6BD><DAA3><EFBFBD><EFBFBD><EFBFBD>4096<39>ֽ<EFBFBD>
|
||
#define DMA_CR_LEN_Msk (0xFFF << DMA_CR_LEN_Pos)
|
||
#define DMA_CR_RXEN_Pos 16
|
||
#define DMA_CR_RXEN_Msk (0x01 << DMA_CR_RXEN_Pos)
|
||
#define DMA_CR_TXEN_Pos 17
|
||
#define DMA_CR_TXEN_Msk (0x01 << DMA_CR_TXEN_Pos)
|
||
#define DMA_CR_AUTORE_Pos 18 //Auto Restart, ͨ<><CDA8><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define DMA_CR_AUTORE_Msk (0x01 << DMA_CR_AUTORE_Pos)
|
||
|
||
#define DMA_AM_SRCAM_Pos 0 //Address Mode 0 <20><>ַ<EFBFBD>̶<EFBFBD> 1 <20><>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD> 2 scatter gatherģʽ
|
||
#define DMA_AM_SRCAM_Msk (0x03 << DMA_AM_SRCAM_Pos)
|
||
#define DMA_AM_DSTAM_Pos 8
|
||
#define DMA_AM_DSTAM_Msk (0x03 << DMA_AM_DSTAM_Pos)
|
||
#define DMA_AM_BURST_Pos 16
|
||
#define DMA_AM_BURST_Msk (0x01 << DMA_AM_BURST_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t CR; //Control Register
|
||
|
||
__O uint32_t CMD; //Command Register
|
||
|
||
__I uint32_t SR; //Status Register
|
||
|
||
__I uint32_t IF; //Interrupt Flag<61><67><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t IE; //Interrupt Enable
|
||
|
||
uint32_t RESERVED;
|
||
|
||
__IO uint32_t BT0; //Bit Time Register 0
|
||
|
||
__IO uint32_t BT1; //Bit Time Register 1
|
||
|
||
uint32_t RESERVED2[3];
|
||
|
||
__I uint32_t ALC; //Arbitration Lost Capture, <20>ٲö<D9B2>ʧ<EFBFBD><CAA7>
|
||
|
||
__I uint32_t ECC; //Error code capture, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>벶
|
||
|
||
__IO uint32_t EWLIM; //Error Warning Limit, <20><><EFBFBD><EFBFBD><F3B1A8BE><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t RXERR; //RX<52><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t TXERR; //TX<54><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
union {
|
||
struct { //<2F>ڸ<EFBFBD>λʱ<CEBB>ɶ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>²<EFBFBD><C2B2>ɷ<EFBFBD><C9B7><EFBFBD>
|
||
__IO uint32_t ACR[4]; //Acceptance Check Register, <20><><EFBFBD>ռĴ<D5BC><C4B4><EFBFBD>
|
||
|
||
__IO uint32_t AMR[4]; //Acceptance Mask Register, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>μĴ<CEBC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧλд0<D0B4><30>ID<49><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռĴ<D5BC><C4B4><EFBFBD>ƥ<EFBFBD><C6A5>
|
||
|
||
uint32_t RESERVED[5];
|
||
} FILTER;
|
||
|
||
union { //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>¿ɶ<C2BF>д<EFBFBD><D0B4><EFBFBD><EFBFBD>λʱ<CEBB><CAB1><EFBFBD>ɷ<EFBFBD><C9B7><EFBFBD>
|
||
struct {
|
||
__O uint32_t INFO;
|
||
|
||
__O uint32_t DATA[12];
|
||
} TXFRAME;
|
||
|
||
struct {
|
||
__I uint32_t INFO;
|
||
|
||
__I uint32_t DATA[12];
|
||
} RXFRAME;
|
||
};
|
||
};
|
||
|
||
__I uint32_t RMCNT; //Receive Message Count
|
||
|
||
uint32_t RESERVED3[66];
|
||
|
||
struct { //TXFRAME<4D>Ķ<EFBFBD><C4B6>ӿ<EFBFBD>
|
||
__I uint32_t INFO;
|
||
|
||
__I uint32_t DATA[12];
|
||
} TXFRAME_R;
|
||
} CAN_TypeDef;
|
||
|
||
|
||
#define CAN_CR_RST_Pos 0
|
||
#define CAN_CR_RST_Msk (0x01 << CAN_CR_RST_Pos)
|
||
#define CAN_CR_LOM_Pos 1 //Listen Only Mode
|
||
#define CAN_CR_LOM_Msk (0x01 << CAN_CR_LOM_Pos)
|
||
#define CAN_CR_STM_Pos 2 //Self Test Mode, <20><>ģʽ<C4A3>¼<EFBFBD>ʹû<CAB9><C3BB>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD>CAN<41><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҳ<EFBFBD><D2B2><EFBFBD>Գɹ<D4B3><C9B9><EFBFBD><EFBFBD><EFBFBD>
|
||
#define CAN_CR_STM_Msk (0x01 << CAN_CR_STM_Pos)
|
||
#define CAN_CR_AFM_Pos 3 //Acceptance Filter Mode, 1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˲<EFBFBD><CBB2><EFBFBD><EFBFBD><EFBFBD>32λ<32><CEBB> 0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˲<EFBFBD><CBB2><EFBFBD><EFBFBD><EFBFBD>16λ<36><CEBB>
|
||
#define CAN_CR_AFM_Msk (0x01 << CAN_CR_AFM_Pos)
|
||
#define CAN_CR_SLEEP_Pos 4 //д1<D0B4><31><EFBFBD><EFBFBD>˯<EFBFBD><CBAF>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DFBB><EEB6AF><EFBFBD>ж<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>Ѳ<EFBFBD><D1B2>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
|
||
#define CAN_CR_SLEEP_Msk (0x01 << CAN_CR_SLEEP_Pos)
|
||
|
||
#define CAN_CMD_TXREQ_Pos 0 //Transmission Request
|
||
#define CAN_CMD_TXREQ_Msk (0x01 << CAN_CMD_TXREQ_Pos)
|
||
#define CAN_CMD_ABTTX_Pos 1 //Abort Transmission
|
||
#define CAN_CMD_ABTTX_Msk (0x01 << CAN_CMD_ABTTX_Pos)
|
||
#define CAN_CMD_RRB_Pos 2 //Release Receive Buffer
|
||
#define CAN_CMD_RRB_Msk (0x01 << CAN_CMD_RRB_Pos)
|
||
#define CAN_CMD_CLROV_Pos 3 //Clear Data Overrun
|
||
#define CAN_CMD_CLROV_Msk (0x01 << CAN_CMD_CLROV_Pos)
|
||
#define CAN_CMD_SRR_Pos 4 //Self Reception Request
|
||
#define CAN_CMD_SRR_Msk (0x01 << CAN_CMD_SRR_Pos)
|
||
|
||
#define CAN_SR_RXDA_Pos 0 //Receive Data Available<6C><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD>Զ<EFBFBD>ȡ
|
||
#define CAN_SR_RXDA_Msk (0x01 << CAN_SR_RXDA_Pos)
|
||
#define CAN_SR_RXOV_Pos 1 //Receive FIFO Overrun<75><6E><EFBFBD>½<EFBFBD><C2BD>յ<EFBFBD><D5B5><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define CAN_SR_RXOV_Msk (0x01 << CAN_SR_RXOV_Pos)
|
||
#define CAN_SR_TXBR_Pos 2 //Transmit Buffer Release<73><65>0 <20><><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD>ķ<EFBFBD><C4B7>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>д<EFBFBD>µ<EFBFBD><C2B5><EFBFBD>Ϣ 1 <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>µ<EFBFBD><C2B5><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>
|
||
#define CAN_SR_TXBR_Msk (0x01 << CAN_SR_TXBR_Pos)
|
||
#define CAN_SR_TXOK_Pos 3 //Transmit OK<4F><4B>successfully completed
|
||
#define CAN_SR_TXOK_Msk (0x01 << CAN_SR_TXOK_Pos)
|
||
#define CAN_SR_RXBUSY_Pos 4 //Receive Busy<73><79><EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD>
|
||
#define CAN_SR_RXBUSY_Msk (0x01 << CAN_SR_RXBUSY_Pos)
|
||
#define CAN_SR_TXBUSY_Pos 5 //Transmit Busy<73><79><EFBFBD><EFBFBD><EFBFBD>ڷ<EFBFBD><DAB7><EFBFBD>
|
||
#define CAN_SR_TXBUSY_Msk (0x01 << CAN_SR_TXBUSY_Pos)
|
||
#define CAN_SR_ERRWARN_Pos 6 //1 <20><><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ﵽ Warning Limit
|
||
#define CAN_SR_ERRWARN_Msk (0x01 << CAN_SR_ERRWARN_Pos)
|
||
#define CAN_SR_BUSOFF_Pos 7 //1 CAN <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߹ر<DFB9>״̬<D7B4><CCAC>û<EFBFBD>в<EFBFBD><D0B2>뵽<EFBFBD><EBB5BD><EFBFBD>
|
||
#define CAN_SR_BUSOFF_Msk (0x01 << CAN_SR_BUSOFF_Pos)
|
||
|
||
#define CAN_IF_RXDA_Pos 0 //IF.RXDA = SR.RXDA & IE.RXDA
|
||
#define CAN_IF_RXDA_Msk (0x01 << CAN_IF_RXDA_Pos)
|
||
#define CAN_IF_TXBR_Pos 1 //<2F><>IE.TXBR=1ʱ<31><CAB1>SR.TXBR<42><52>0<EFBFBD><30><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>λ
|
||
#define CAN_IF_TXBR_Msk (0x01 << CAN_IF_TXBR_Pos)
|
||
#define CAN_IF_ERRWARN_Pos 2 //<2F><>IE.ERRWARN=1ʱ<31><CAB1>SR.ERRWARN<52><4E>SR.BUSOFF 0-to-1 <20><> 1-to-0<><30><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>λ
|
||
#define CAN_IF_ERRWARN_Msk (0x01 << CAN_IF_ERRWARN_Pos)
|
||
#define CAN_IF_RXOV_Pos 3 //IF.RXOV = SR.RXOV & IE.RXOV
|
||
#define CAN_IF_RXOV_Msk (0x01 << CAN_IF_RXOV_Pos)
|
||
#define CAN_IF_WKUP_Pos 4 //<2F><>IE.WKUP=1ʱ<31><CAB1><EFBFBD><EFBFBD>˯<EFBFBD><CBAF>ģʽ<C4A3>µ<EFBFBD>CAN<41><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><E2B5BD><EFBFBD>ʱӲ<CAB1><D3B2><EFBFBD><EFBFBD>λ
|
||
#define CAN_IF_WKUP_Msk (0x01 << CAN_IF_WKUP_Pos)
|
||
#define CAN_IF_ERRPASS_Pos 5 //
|
||
#define CAN_IF_ERRPASS_Msk (0x01 << CAN_IF_ERRPASS_Pos)
|
||
#define CAN_IF_ARBLOST_Pos 6 //Arbitration Lost<73><74><EFBFBD><EFBFBD>IE.ARBLOST=1ʱ<31><CAB1>CAN<41><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʧ<EFBFBD>ٲñ<D9B2><C3B1>ɽ<EFBFBD><C9BD>շ<EFBFBD>ʱӲ<CAB1><D3B2><EFBFBD><EFBFBD>λ
|
||
#define CAN_IF_ARBLOST_Msk (0x01 << CAN_IF_ARBLOST_Pos)
|
||
#define CAN_IF_BUSERR_Pos 7 //<2F><>IE.BUSERR=1ʱ<31><CAB1>CAN<41><4E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><E2B5BD><EFBFBD>ߴ<EFBFBD><DFB4><EFBFBD>ʱӲ<CAB1><D3B2><EFBFBD><EFBFBD>λ
|
||
#define CAN_IF_BUSERR_Msk (0x01 << CAN_IF_BUSERR_Pos)
|
||
|
||
#define CAN_IE_RXDA_Pos 0
|
||
#define CAN_IE_RXDA_Msk (0x01 << CAN_IE_RXDA_Pos)
|
||
#define CAN_IE_TXBR_Pos 1
|
||
#define CAN_IE_TXBR_Msk (0x01 << CAN_IE_TXBR_Pos)
|
||
#define CAN_IE_ERRWARN_Pos 2
|
||
#define CAN_IE_ERRWARN_Msk (0x01 << CAN_IE_ERRWARN_Pos)
|
||
#define CAN_IE_RXOV_Pos 3
|
||
#define CAN_IE_RXOV_Msk (0x01 << CAN_IE_RXOV_Pos)
|
||
#define CAN_IE_WKUP_Pos 4
|
||
#define CAN_IE_WKUP_Msk (0x01 << CAN_IE_WKUP_Pos)
|
||
#define CAN_IE_ERRPASS_Pos 5
|
||
#define CAN_IE_ERRPASS_Msk (0x01 << CAN_IE_ERRPASS_Pos)
|
||
#define CAN_IE_ARBLOST_Pos 6
|
||
#define CAN_IE_ARBLOST_Msk (0x01 << CAN_IE_ARBLOST_Pos)
|
||
#define CAN_IE_BUSERR_Pos 7
|
||
#define CAN_IE_BUSERR_Msk (0x01 << CAN_IE_BUSERR_Pos)
|
||
|
||
#define CAN_BT0_BRP_Pos 0 //Baud Rate Prescaler<65><72>CANʱ<4E>䵥λ=2*Tsysclk*(BRP+1)
|
||
#define CAN_BT0_BRP_Msk (0x3F << CAN_BT0_BRP_Pos)
|
||
#define CAN_BT0_SJW_Pos 6 //Synchronization Jump Width
|
||
#define CAN_BT0_SJW_Msk (0x03 << CAN_BT0_SJW_Pos)
|
||
|
||
#define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CANʱ<4E>䵥λ * (TSEG1+1)
|
||
#define CAN_BT1_TSEG1_Msk (0x0F << CAN_BT1_TSEG1_Pos)
|
||
#define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CANʱ<4E>䵥λ * (TSEG2+1)
|
||
#define CAN_BT1_TSEG2_Msk (0x07 << CAN_BT1_TSEG2_Pos)
|
||
#define CAN_BT1_SAM_Pos 7 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0: sampled once 1: sampled three times
|
||
#define CAN_BT1_SAM_Msk (0x01 << CAN_BT1_SAM_Pos)
|
||
|
||
#define CAN_ECC_SEGCODE_Pos 0 //Segment Code
|
||
#define CAN_ECC_SEGCODE_Msk (0x1F << CAN_ECC_SEGCODE_Pos)
|
||
#define CAN_ECC_DIR_Pos 5 //0 error occurred during transmission 1 during reception
|
||
#define CAN_ECC_DIR_Msk (0x01 << CAN_ECC_DIR_Pos)
|
||
#define CAN_ECC_ERRCODE_Pos 6 //Error Code<64><65>0 Bit error 1 Form error 2 Stuff error 3 other error
|
||
#define CAN_ECC_ERRCODE_Msk (0x03 << CAN_ECC_ERRCODE_Pos)
|
||
|
||
#define CAN_INFO_DLC_Pos 0 //Data Length Control
|
||
#define CAN_INFO_DLC_Msk (0x0F << CAN_INFO_DLC_Pos)
|
||
#define CAN_INFO_RTR_Pos 6 //Remote Frame<6D><65>1 Զ<><D4B6>֡ 0 <20><><EFBFBD><EFBFBD>֡
|
||
#define CAN_INFO_RTR_Msk (0x01 << CAN_INFO_RTR_Pos)
|
||
#define CAN_INFO_FF_Pos 7 //Frame Format<61><74>0 <20><>֡<D7BC><D6A1>ʽ 1 <20><>չ֡<D5B9><D6A1>ʽ
|
||
#define CAN_INFO_FF_Msk (0x01 << CAN_INFO_FF_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t IE; //[0] Ϊ0<CEAA><30>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>IF[0]ά<><CEAC>Ϊ0
|
||
|
||
__IO uint32_t IF; //[0] <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD>ʱ<EFBFBD><CAB1>1<EFBFBD><31>д1<D0B4><31><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t IM; //[0] <20><><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>Ϊ1ʱ<31><CAB1>LCDC<44><43><EFBFBD>жϲ<D0B6><CFB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD>жϿ<D0B6><CFBF>ƼĴ<C6BC><C4B4><EFBFBD>
|
||
|
||
__IO uint32_t START;
|
||
|
||
__IO uint32_t SRCADDR; //<2F><><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ַ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֶ<EFBFBD><D6B6>루<EFBFBD><EBA3A8><EFBFBD><EFBFBD>ַ<EFBFBD>ĵ<EFBFBD>2λ<32><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30>
|
||
|
||
__IO uint32_t CR0;
|
||
|
||
__IO uint32_t CR1;
|
||
|
||
__IO uint32_t PRECMDV; //<2F><>MPU<50>ӿ<EFBFBD><D3BF>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0>RS<52><53><EFBFBD>͵<EFBFBD><CDB5><EFBFBD>һ<EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵ<EFBFBD>ֵ
|
||
} LCD_TypeDef;
|
||
|
||
|
||
#define LCD_START_GO_Pos 1 //д1<D0B4><31>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
|
||
#define LCD_START_GO_Msk (0x01 << LCD_START_GO_Pos)
|
||
#define LCD_START_BURST_Pos 2
|
||
#define LCD_START_BURST_Msk (0x01 << LCD_START_BURST_Pos)
|
||
|
||
#define LCD_CR0_VPIX_Pos 0 //<2F><>portraitΪ0ʱ<30><CAB1><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30>ʾ1<CABE><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ767
|
||
//<2F><>portraitΪ1ʱ<31><CAB1><EFBFBD><EFBFBD>ʾˮƽ<CBAE><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30>ʾ1<CABE><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ767
|
||
#define LCD_CR0_VPIX_Msk (0x3FF << LCD_CR0_VPIX_Pos)
|
||
#define LCD_CR0_HPIX_Pos 10 //<2F><>portraitΪ0ʱ<30><CAB1><EFBFBD><EFBFBD>ʾˮƽ<CBAE><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30>ʾ1<CABE><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ1023
|
||
//<2F><>portraitΪ1ʱ<31><CAB1><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30>ʾ1<CABE><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ1023
|
||
#define LCD_CR0_HPIX_Msk (0x3FF << LCD_CR0_HPIX_Pos)
|
||
#define LCD_CR0_DCLK_Pos 20 //0 DOTCLKһֱ<D2BB><D6B1>ת 1 DOTCLK<4C>ڿ<EFBFBD><DABF><EFBFBD>ʱͣ<CAB1><CDA3>1
|
||
#define LCD_CR0_DCLK_Msk (0x01 << LCD_CR0_DCLK_Pos)
|
||
#define LCD_CR0_HLOW_Pos 21 //<2F><><EFBFBD><EFBFBD>HSYNC<4E>͵<EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٸ<EFBFBD>DOTCLK<4C><4B><EFBFBD>ڣ<EFBFBD>0<EFBFBD><30>ʾ1<CABE><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define LCD_CR0_HLOW_Msk (0x03 << LCD_CR0_HLOW_Pos)
|
||
|
||
#define LCD_CR1_VFP_Pos 1
|
||
#define LCD_CR1_VFP_Msk (0x07 << LCD_CR1_VFP_Pos)
|
||
#define LCD_CR1_VBP_Pos 4
|
||
#define LCD_CR1_VBP_Msk (0x1F << LCD_CR1_VBP_Pos)
|
||
#define LCD_CR1_HFP_Pos 9
|
||
#define LCD_CR1_HFP_Msk (0x1F << LCD_CR1_HFP_Pos)
|
||
#define LCD_CR1_HBP_Pos 14
|
||
#define LCD_CR1_HBP_Msk (0x7F << LCD_CR1_HBP_Pos)
|
||
#define LCD_CR1_DCLKDIV_Pos 21 //DOTCLK<4C><4B><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ʱ<EFBFBD>ӵķ<D3B5>Ƶ<EFBFBD>ȣ<EFBFBD>0<EFBFBD><30>ʾ2<CABE><32>Ƶ<EFBFBD><C6B5>1<EFBFBD><31>ʾ4<CABE><34>Ƶ ...
|
||
#define LCD_CR1_DCLKDIV_Msk (0x1F << LCD_CR1_DCLKDIV_Pos)
|
||
#define LCD_CR1_DCLKINV_Pos 26 //1 <20><><EFBFBD><EFBFBD>DOTCLK<4C><4B><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DOTCLK<4C>½<EFBFBD><C2BD>ز<EFBFBD><D8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD><DDB5><EFBFBD>
|
||
#define LCD_CR1_DCLKINV_Msk (0x01 << LCD_CR1_DCLKINV_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t DMA_MEM_ADDR;
|
||
|
||
__IO uint32_t BLK; //Block Size and Count
|
||
|
||
__IO uint32_t ARG; //Argument
|
||
|
||
__IO uint32_t CMD; //Command
|
||
|
||
__IO uint32_t RESP[4]; //Response
|
||
|
||
__IO uint32_t DATA;
|
||
|
||
__IO uint32_t STAT;
|
||
|
||
__IO uint32_t CR1;
|
||
|
||
__IO uint32_t CR2;
|
||
|
||
__IO uint32_t IF;
|
||
|
||
__IO uint32_t IFE; //Interrupt Flag Enable
|
||
|
||
__IO uint32_t IE; //Interrupt Enalbe
|
||
|
||
__IO uint32_t CMD12ERR;
|
||
|
||
__IO uint32_t INFO;
|
||
|
||
__IO uint32_t MAXCURR;
|
||
} SDIO_TypeDef;
|
||
|
||
|
||
#define SDIO_BLK_SIZE_Pos 0 //0x200 512<31>ֽ<EFBFBD> 0x400 1024<32>ֽ<EFBFBD> 0x800 2048<34>ֽ<EFBFBD>
|
||
#define SDIO_BLK_SIZE_Msk (0xFFF << SDIO_BLK_SIZE_Pos)
|
||
#define SDIO_BLK_COUNT_Pos 16 //0 Stop Transfer 1 1<><31> 2 2<><32> ... ...
|
||
#define SDIO_BLK_COUNT_Msk (0xFFF << SDIO_BLK_COUNT_Pos)
|
||
|
||
#define SDIO_CMD_DMAEN_Pos 0
|
||
#define SDIO_CMD_DMAEN_Msk (0x01 << SDIO_CMD_DMAEN_Pos)
|
||
#define SDIO_CMD_BLKCNTEN_Pos 1
|
||
#define SDIO_CMD_BLKCNTEN_Msk (0x01 << SDIO_CMD_BLKCNTEN_Pos)
|
||
#define SDIO_CMD_AUTOCMD12_Pos 2
|
||
#define SDIO_CMD_AUTOCMD12_Msk (0x01 << SDIO_CMD_AUTOCMD12_Pos)
|
||
#define SDIO_CMD_DIRREAD_Pos 4 //0 Write, Host to Card 1 Read, Card to Host
|
||
#define SDIO_CMD_DIRREAD_Msk (0x01 << SDIO_CMD_DIRREAD_Pos)
|
||
#define SDIO_CMD_MULTBLK_Pos 5 //0 Single Block 1 Multiple Block
|
||
#define SDIO_CMD_MULTBLK_Msk (0x01 << SDIO_CMD_MULTBLK_Pos)
|
||
#define SDIO_CMD_RESPTYPE_Pos 16 //<2F><>Ӧ<EFBFBD><D3A6><EFBFBD>ͣ<EFBFBD>0 <20><><EFBFBD><EFBFBD>Ӧ 1 136λ<36><CEBB>Ӧ 2 48λ<38><CEBB>Ӧ 3 48λ<38><CEBB>Ӧ<EFBFBD><D3A6>Busy after response
|
||
#define SDIO_CMD_RESPTYPE_Msk (0x03 << SDIO_CMD_RESPTYPE_Pos)
|
||
#define SDIO_CMD_CRCCHECK_Pos 19 //Command CRC Check Enable
|
||
#define SDIO_CMD_CRCCHECK_Msk (0x01 << SDIO_CMD_CRCCHECK_Pos)
|
||
#define SDIO_CMD_IDXCHECK_Pos 20 //Command Index Check Enable
|
||
#define SDIO_CMD_IDXCHECK_Msk (0x01 << SDIO_CMD_IDXCHECK_Pos)
|
||
#define SDIO_CMD_HAVEDATA_Pos 21 //0 No Data Present 1 Data Present
|
||
#define SDIO_CMD_HAVEDATA_Msk (0x01 << SDIO_CMD_HAVEDATA_Pos)
|
||
#define SDIO_CMD_CMDTYPE_Pos 22 //0 NORMAL 1 SUSPEND 2 RESUME 3 ABORT
|
||
#define SDIO_CMD_CMDTYPE_Msk (0x03 << SDIO_CMD_CMDTYPE_Pos)
|
||
#define SDIO_CMD_CMDINDX_Pos 24 //Command Index<65><78>CMD0-63<36><33>ACMD0-63
|
||
#define SDIO_CMD_CMDINDX_Msk (0x3F << SDIO_CMD_CMDINDX_Pos)
|
||
|
||
#define SDIO_CR1_4BIT_Pos 1 //1 4 bit mode 0 1 bit mode
|
||
#define SDIO_CR1_4BIT_Msk (0x01 << SDIO_CR1_4BIT_Pos)
|
||
#define SDIO_CR1_8BIT_Pos 5 //1 8 bit mode is selected 0 8 bit mode is not selected
|
||
#define SDIO_CR1_8BIT_Msk (0x01 << SDIO_CR1_8BIT_Pos)
|
||
#define SDIO_CR1_CDBIT_Pos 6 //0 No Card 1 Card Inserted
|
||
#define SDIO_CR1_CDBIT_Msk (0x01 << SDIO_CR1_CDBIT_Pos)
|
||
#define SDIO_CR1_CDSRC_Pos 7 //Card Detect Source, 1 CR1.CDBITλ 0 SD_Detect<63><74><EFBFBD><EFBFBD>
|
||
#define SDIO_CR1_CDSRC_Msk (0x01 << SDIO_CR1_CDSRC_Pos)
|
||
#define SDIO_CR1_PWRON_Pos 8 //1 Power on 0 Power off
|
||
#define SDIO_CR1_PWRON_Msk (0x01 << SDIO_CR1_PWRON_Pos)
|
||
#define SDIO_CR1_VOLT_Pos 9 //7 3.3V 6 3.0V 5 1.8V
|
||
#define SDIO_CR1_VOLT_Msk (0x07 << SDIO_CR1_VOLT_Pos)
|
||
|
||
#define SDIO_CR2_CLKEN_Pos 0 //Internal Clock Enable
|
||
#define SDIO_CR2_CLKEN_Msk (0x01 << SDIO_CR2_CLKEN_Pos)
|
||
#define SDIO_CR2_CLKRDY_Pos 1 //Internal Clock Stable/Ready
|
||
#define SDIO_CR2_CLKRDY_Msk (0x01 << SDIO_CR2_CLKRDY_Pos)
|
||
#define SDIO_CR2_SDCLKEN_Pos 2 //SDCLK Enable
|
||
#define SDIO_CR2_SDCLKEN_Msk (0x01 << SDIO_CR2_SDCLKEN_Pos)
|
||
#define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 <20><><EFBFBD><EFBFBD>Ƶ 0x01 2<><32>Ƶ 0x02 4<><34>Ƶ 0x04 8<><38>Ƶ 0x08 16<31><36>Ƶ ... 0x80 256<35><36>Ƶ
|
||
#define SDIO_CR2_SDCLKDIV_Msk (0xFF << SDIO_CR2_SDCLKDIV_Pos)
|
||
#define SDIO_CR2_TIMEOUT_Pos 16 //0 TMCLK*2^13 1 TMCLK*2^14 ... 14 TMCLK*2^27
|
||
#define SDIO_CR2_TIMEOUT_Msk (0x0F << SDIO_CR2_TIMEOUT_Pos)
|
||
#define SDIO_CR2_RSTALL_Pos 24 //Software Reset for All
|
||
#define SDIO_CR2_RSTALL_Msk (0x01 << SDIO_CR2_RSTALL_Pos)
|
||
#define SDIO_CR2_RSTCMD_Pos 25 //Software Reset for CMD Line
|
||
#define SDIO_CR2_RSTCMD_Msk (0x01 << SDIO_CR2_RSTCMD_Pos)
|
||
#define SDIO_CR2_RSTDAT_Pos 26 //Software Reset for DAT Line
|
||
#define SDIO_CR2_RSTDAT_Msk (0x01 << SDIO_CR2_RSTDAT_Pos)
|
||
|
||
#define SDIO_IF_CMDDONE_Pos 0
|
||
#define SDIO_IF_CMDDONE_Msk (0x01 << SDIO_IF_CMDDONE_Pos)
|
||
#define SDIO_IF_TRXDONE_Pos 1
|
||
#define SDIO_IF_TRXDONE_Msk (0x01 << SDIO_IF_TRXDONE_Pos)
|
||
#define SDIO_IF_BLKGAP_Pos 2
|
||
#define SDIO_IF_BLKGAP_Msk (0x01 << SDIO_IF_BLKGAP_Pos)
|
||
#define SDIO_IF_DMADONE_Pos 3
|
||
#define SDIO_IF_DMADONE_Msk (0x01 << SDIO_IF_DMADONE_Pos)
|
||
#define SDIO_IF_BUFWRRDY_Pos 4
|
||
#define SDIO_IF_BUFWRRDY_Msk (0x01 << SDIO_IF_BUFWRRDY_Pos)
|
||
#define SDIO_IF_BUFRDRDY_Pos 5
|
||
#define SDIO_IF_BUFRDRDY_Msk (0x01 << SDIO_IF_BUFRDRDY_Pos)
|
||
#define SDIO_IF_CARDINSR_Pos 6
|
||
#define SDIO_IF_CARDINSR_Msk (0x01 << SDIO_IF_CARDINSR_Pos)
|
||
#define SDIO_IF_CARDRMOV_Pos 7
|
||
#define SDIO_IF_CARDRMOV_Msk (0x01 << SDIO_IF_CARDRMOV_Pos)
|
||
#define SDIO_IF_CARD_Pos 8
|
||
#define SDIO_IF_CARD_Msk (0x01 << SDIO_IF_CARD_Pos)
|
||
#define SDIO_IF_ERROR_Pos 15
|
||
#define SDIO_IF_ERROR_Msk (0x01 << SDIO_IF_ERROR_Pos)
|
||
#define SDIO_IF_CMDTIMEOUT_Pos 16
|
||
#define SDIO_IF_CMDTIMEOUT_Msk (0x01 << SDIO_IF_CMDTIMEOUT_Pos)
|
||
#define SDIO_IF_CMDCRCERR_Pos 17
|
||
#define SDIO_IF_CMDCRCERR_Msk (0x01 << SDIO_IF_CMDCRCERR_Pos)
|
||
#define SDIO_IF_CMDENDERR_Pos 18
|
||
#define SDIO_IF_CMDENDERR_Msk (0x01 << SDIO_IF_CMDENDCERR_Pos)
|
||
#define SDIO_IF_CMDIDXERR_Pos 19
|
||
#define SDIO_IF_CMDIDXERR_Msk (0x01 << SDIO_IF_CMDIDXCERR_Pos)
|
||
#define SDIO_IF_DATTIMEOUT_Pos 20
|
||
#define SDIO_IF_DATTIMEOUT_Msk (0x01 << SDIO_IF_DATTIMEOUT_Pos)
|
||
#define SDIO_IF_DATCRCERR_Pos 21
|
||
#define SDIO_IF_DATCRCERR_Msk (0x01 << SDIO_IF_DATCRCERR_Pos)
|
||
#define SDIO_IF_DATENDERR_Pos 22
|
||
#define SDIO_IF_DATENDERR_Msk (0x01 << SDIO_IF_DATENDCERR_Pos)
|
||
#define SDIO_IF_CURLIMERR_Pos 23
|
||
#define SDIO_IF_CURLIMERR_Msk (0x01 << SDIO_IF_CURLIMERR_Pos)
|
||
#define SDIO_IF_CMD12ERR_Pos 24
|
||
#define SDIO_IF_CMD12ERR_Msk (0x01 << SDIO_IF_CMD12ERR_Pos)
|
||
#define SDIO_IF_DMAERR_Pos 25
|
||
#define SDIO_IF_DMAERR_Msk (0x01 << SDIO_IF_DMAERR_Pos)
|
||
#define SDIO_IF_RESPERR_Pos 28
|
||
#define SDIO_IF_RESPERR_Msk (0x01 << SDIO_IF_RESPERR_Pos)
|
||
|
||
#define SDIO_IE_CMDDONE_Pos 0 //Command Complete Status Enable
|
||
#define SDIO_IE_CMDDONE_Msk (0x01 << SDIO_IE_CMDDONE_Pos)
|
||
#define SDIO_IE_TRXDONE_Pos 1 //Transfer Complete Status Enable
|
||
#define SDIO_IE_TRXDONE_Msk (0x01 << SDIO_IE_TRXDONE_Pos)
|
||
#define SDIO_IE_BLKGAP_Pos 2 //Block Gap Event Status Enable
|
||
#define SDIO_IE_BLKGAP_Msk (0x01 << SDIO_IE_BLKGAP_Pos)
|
||
#define SDIO_IE_DMADONE_Pos 3 //DMA Interrupt Status Enable
|
||
#define SDIO_IE_DMADONE_Msk (0x01 << SDIO_IE_DMADONE_Pos)
|
||
#define SDIO_IE_BUFWRRDY_Pos 4 //Buffer Write Ready Status Enable
|
||
#define SDIO_IE_BUFWRRDY_Msk (0x01 << SDIO_IE_BUFWRRDY_Pos)
|
||
#define SDIO_IE_BUFRDRDY_Pos 5 //Buffer Read Ready Status Enable
|
||
#define SDIO_IE_BUFRDRDY_Msk (0x01 << SDIO_IE_BUFRDRDY_Pos)
|
||
#define SDIO_IE_CARDINSR_Pos 6 //Card Insertion Status Enable
|
||
#define SDIO_IE_CARDINSR_Msk (0x01 << SDIO_IE_CARDINSR_Pos)
|
||
#define SDIO_IE_CARDRMOV_Pos 7 //Card Removal Status Enable
|
||
#define SDIO_IE_CARDRMOV_Msk (0x01 << SDIO_IE_CARDRMOV_Pos)
|
||
#define SDIO_IE_CARD_Pos 8
|
||
#define SDIO_IE_CARD_Msk (0x01 << SDIO_IE_CARD_Pos)
|
||
#define SDIO_IE_CMDTIMEOUT_Pos 16 //Command Timeout Error Status Enable
|
||
#define SDIO_IE_CMDTIMEOUT_Msk (0x01 << SDIO_IE_CMDTIMEOUT_Pos)
|
||
#define SDIO_IE_CMDCRCERR_Pos 17 //Command CRC Error Status Enable
|
||
#define SDIO_IE_CMDCRCERR_Msk (0x01 << SDIO_IE_CMDCRCERR_Pos)
|
||
#define SDIO_IE_CMDENDERR_Pos 18 //Command End Bit Error Status Enable
|
||
#define SDIO_IE_CMDENDERR_Msk (0x01 << SDIO_IE_CMDENDCERR_Pos)
|
||
#define SDIO_IE_CMDIDXERR_Pos 19 //Command Index Error Status Enable
|
||
#define SDIO_IE_CMDIDXERR_Msk (0x01 << SDIO_IE_CMDIDXCERR_Pos)
|
||
#define SDIO_IE_DATTIMEOUT_Pos 20 //Data Timeout Error Status Enable
|
||
#define SDIO_IE_DATTIMEOUT_Msk (0x01 << SDIO_IE_DATTIMEOUT_Pos)
|
||
#define SDIO_IE_DATCRCERR_Pos 21 //Data CRC Error Status Enable
|
||
#define SDIO_IE_DATCRCERR_Msk (0x01 << SDIO_IE_DATCRCERR_Pos)
|
||
#define SDIO_IE_DATENDERR_Pos 22 //Data End Bit Error Status Enable
|
||
#define SDIO_IE_DATENDERR_Msk (0x01 << SDIO_IE_DATENDCERR_Pos)
|
||
#define SDIO_IE_CURLIMERR_Pos 23 //Current Limit Error Status Enable
|
||
#define SDIO_IE_CURLIMERR_Msk (0x01 << SDIO_IE_CURLIMERR_Pos)
|
||
#define SDIO_IE_CMD12ERR_Pos 24 //Auto CMD12 Error Status Enable
|
||
#define SDIO_IE_CMD12ERR_Msk (0x01 << SDIO_IE_CMD12ERR_Pos)
|
||
#define SDIO_IE_DMAERR_Pos 25 //ADMA Error Status Enable
|
||
#define SDIO_IE_DMAERR_Msk (0x01 << SDIO_IE_DMAERR_Pos)
|
||
#define SDIO_IE_RESPERR_Pos 28 //Target Response Error Status Enable
|
||
#define SDIO_IE_RESPERR_Msk (0x01 << SDIO_IE_RESPERR_Pos)
|
||
|
||
#define SDIO_IM_CMDDONE_Pos 0
|
||
#define SDIO_IM_CMDDONE_Msk (0x01 << SDIO_IM_CMDDONE_Pos)
|
||
#define SDIO_IM_TRXDONE_Pos 1
|
||
#define SDIO_IM_TRXDONE_Msk (0x01 << SDIO_IM_TRXDONE_Pos)
|
||
#define SDIO_IM_BLKGAP_Pos 2
|
||
#define SDIO_IM_BLKGAP_Msk (0x01 << SDIO_IM_BLKGAP_Pos)
|
||
#define SDIO_IM_DMADONE_Pos 3
|
||
#define SDIO_IM_DMADONE_Msk (0x01 << SDIO_IM_DMADONE_Pos)
|
||
#define SDIO_IM_BUFWRRDY_Pos 4
|
||
#define SDIO_IM_BUFWRRDY_Msk (0x01 << SDIO_IM_BUFWRRDY_Pos)
|
||
#define SDIO_IM_BUFRDRDY_Pos 5
|
||
#define SDIO_IM_BUFRDRDY_Msk (0x01 << SDIO_IM_BUFRDRDY_Pos)
|
||
#define SDIO_IM_CARDINSR_Pos 6
|
||
#define SDIO_IM_CARDINSR_Msk (0x01 << SDIO_IM_CARDINSR_Pos)
|
||
#define SDIO_IM_CARDRMOV_Pos 7
|
||
#define SDIO_IM_CARDRMOV_Msk (0x01 << SDIO_IM_CARDRMOV_Pos)
|
||
#define SDIO_IM_CARD_Pos 8
|
||
#define SDIO_IM_CARD_Msk (0x01 << SDIO_IM_CARD_Pos)
|
||
#define SDIO_IM_CMDTIMEOUT_Pos 16
|
||
#define SDIO_IM_CMDTIMEOUT_Msk (0x01 << SDIO_IM_CMDTIMEOUT_Pos)
|
||
#define SDIO_IM_CMDCRCERR_Pos 17
|
||
#define SDIO_IM_CMDCRCERR_Msk (0x01 << SDIO_IM_CMDCRCERR_Pos)
|
||
#define SDIO_IM_CMDENDERR_Pos 18
|
||
#define SDIO_IM_CMDENDERR_Msk (0x01 << SDIO_IM_CMDENDCERR_Pos)
|
||
#define SDIO_IM_CMDIDXERR_Pos 19
|
||
#define SDIO_IM_CMDIDXERR_Msk (0x01 << SDIO_IM_CMDIDXCERR_Pos)
|
||
#define SDIO_IM_DATTIMEOUT_Pos 20
|
||
#define SDIO_IM_DATTIMEOUT_Msk (0x01 << SDIO_IM_DATTIMEOUT_Pos)
|
||
#define SDIO_IM_DATCRCERR_Pos 21
|
||
#define SDIO_IM_DATCRCERR_Msk (0x01 << SDIO_IM_DATCRCERR_Pos)
|
||
#define SDIO_IM_DATENDERR_Pos 22
|
||
#define SDIO_IM_DATENDERR_Msk (0x01 << SDIO_IM_DATENDCERR_Pos)
|
||
#define SDIO_IM_CURLIMERR_Pos 23
|
||
#define SDIO_IM_CURLIMERR_Msk (0x01 << SDIO_IM_CURLIMERR_Pos)
|
||
#define SDIO_IM_CMD12ERR_Pos 24
|
||
#define SDIO_IM_CMD12ERR_Msk (0x01 << SDIO_IM_CMD12ERR_Pos)
|
||
#define SDIO_IM_DMAERR_Pos 25
|
||
#define SDIO_IM_DMAERR_Msk (0x01 << SDIO_IM_DMAERR_Pos)
|
||
#define SDIO_IM_RESPERR_Pos 28
|
||
#define SDIO_IM_RESPERR_Msk (0x01 << SDIO_IM_RESPERR_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t DATA;
|
||
__IO uint32_t ADDR;
|
||
__IO uint32_t ERASE;
|
||
__IO uint32_t CACHE;
|
||
__IO uint32_t CFG0;
|
||
__IO uint32_t CFG1;
|
||
__IO uint32_t CFG2;
|
||
__IO uint32_t CFG3;
|
||
__IO uint32_t STAT;
|
||
} FLASH_Typedef;
|
||
|
||
|
||
#define FLASH_ERASE_REQ_Pos 31
|
||
#define FLASH_ERASE_REQ_Msk (0x01u<< FLASH_ERASE_REQ_Pos)
|
||
|
||
#define FLASH_CACHE_PROG_Pos 2
|
||
#define FLASH_CACHE_PROG_Msk (0x01 << FLASH_CACHE_PROG_Pos)
|
||
#define FLASH_CACHE_CLEAR_Pos 3
|
||
#define FLASH_CACHE_CLEAR_Msk (0x01 << FLASH_CACHE_CLEAR_Pos)
|
||
|
||
#define FLASH_STAT_ERASE_GOING_Pos 0
|
||
#define FLASH_STAT_ERASE_GOING_Msk (0X01 << FLASH_STAT_ERASE_GOING_Pos)
|
||
#define FLASH_STAT_PROG_GOING_Pos 1
|
||
#define FLASH_STAT_PROG_GOING_Msk (0x01 << FLASH_STAT_PROG_GOING_Pos)
|
||
#define FALSH_STAT_FIFO_EMPTY_Pos 3
|
||
#define FLASH_STAT_FIFO_EMPTY_Msk (0x01 << FALSH_STAT_FIFO_EMPTY_Pos)
|
||
#define FALSH_STAT_FIFO_FULL_Pos 4
|
||
#define FLASH_STAT_FIFO_FULL_Msk (0x01 << FALSH_STAT_FIFO_FULL_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t CR;
|
||
} SRAMC_TypeDef;
|
||
|
||
|
||
#define SRAMC_CR_RWTIME_Pos 0 //<2F><>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٸ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ڡ<EFBFBD>0<EFBFBD><30>ʾ1<CABE><31>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ڡ<EFBFBD><DAA1><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD>Ϊ4
|
||
#define SRAMC_CR_RWTIME_Msk (0x0F << SRAMC_CR_RWTIME_Pos)
|
||
#define SRAMC_CR_BYTEIF_Pos 4 //<2F>ⲿSRAM<41><4D><EFBFBD>ݿ<EFBFBD><DDBF>ȣ<EFBFBD>0 16λ 1 8λ
|
||
#define SRAMC_CR_BYTEIF_Msk (0x01 << SRAMC_CR_BYTEIF_Pos)
|
||
#define SRAMC_CR_HBLBDIS_Pos 5 //1 ADDR[23:22]Ϊ<><CEAA>ַ<EFBFBD><D6B7> 0 ADDR[23]Ϊ<><CEAA><EFBFBD>ֽ<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD>ADDR[22]Ϊ<><CEAA><EFBFBD>ֽ<EFBFBD>ʹ<EFBFBD><CAB9>
|
||
#define SRAMC_CR_HBLBDIS_Msk (0x01 << SRAMC_CR_HBLBDIS_Pos)
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t CR0;
|
||
|
||
__IO uint32_t CR1;
|
||
|
||
__IO uint32_t REFRESH;
|
||
|
||
__IO uint32_t NOPNUM; //[15:0] <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֮ǰ<D6AE><C7B0><EFBFBD><EFBFBD><EFBFBD>Ͷ<EFBFBD><CDB6>ٸ<EFBFBD>NOP<4F><50><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t LATCH;
|
||
|
||
__IO uint32_t REFDONE; //[0] Frefresh Done<6E><65><EFBFBD>ϵ<EFBFBD><CFB5><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
} SDRAMC_TypeDef;
|
||
|
||
|
||
#define SDRAMC_CR0_BURSTLEN_Pos 0 //<2F><><EFBFBD><EFBFBD>ȡ2<C8A1><32><EFBFBD><EFBFBD>ʾBurst LengthΪ4
|
||
#define SDRAMC_CR0_BURSTLEN_Msk (0x07 << SDRAMC_CR0_BURSTLEN_Pos)
|
||
#define SDRAMC_CR0_CASDELAY_Pos 4 //CAS Latency<63><79> 2 2 3 3
|
||
#define SDRAMC_CR0_CASDELAY_Msk (0x07 << SDRAMC_CR0_CASDELAY_Pos)
|
||
|
||
#define SDRAMC_CR1_TRP_Pos 0
|
||
#define SDRAMC_CR1_TRP_Msk (0x07 << SDRAMC_CR1_TRP_Pos)
|
||
#define SDRAMC_CR1_TRCD_Pos 3
|
||
#define SDRAMC_CR1_TRCD_Msk (0x07 << SDRAMC_CR1_TRCD_Pos)
|
||
#define SDRAMC_CR1_TRC_Pos 6
|
||
#define SDRAMC_CR1_TRC_Msk (0x0F << SDRAMC_CR1_TRC_Pos)
|
||
#define SDRAMC_CR1_TRAS_Pos 10
|
||
#define SDRAMC_CR1_TRAS_Msk (0x07 << SDRAMC_CR1_TRAS_Pos)
|
||
#define SDRAMC_CR1_TRRD_Pos 13
|
||
#define SDRAMC_CR1_TRRD_Msk (0x03 << SDRAMC_CR1_TRRD_Pos)
|
||
#define SDRAMC_CR1_TMRD_Pos 15
|
||
#define SDRAMC_CR1_TMRD_Msk (0x07 << SDRAMC_CR1_TMRD_Pos)
|
||
#define SDRAMC_CR1_32BIT_Pos 18 //SDRAMC<4D>Ľӿ<C4BD><D3BF><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>1 32bit 0 16bit
|
||
#define SDRAMC_CR1_32BIT_Msk (0x01 << SDRAMC_CR1_32BIT_Pos)
|
||
#define SDRAMC_CR1_BANK_Pos 19 //SDRAMÿ<4D><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>м<EFBFBD><D0BC><EFBFBD>bank<6E><6B>0 2 banks 1 4 banks
|
||
#define SDRAMC_CR1_BANK_Msk (0x01 << SDRAMC_CR1_BANK_Pos)
|
||
#define SDRAMC_CR1_CELL32BIT_Pos 20 //SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>1 32bit 0 16bit
|
||
#define SDRAMC_CR1_CELL32BIT_Msk (0x01 << SDRAMC_CR1_CELL32BIT_Pos)
|
||
#define SDRAMC_CR1_CELLSIZE_Pos 21 //SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0 64Mb 1 128Mb 2 256Mb 3 16Mb
|
||
#define SDRAMC_CR1_CELLSIZE_Msk (0x03 << SDRAMC_CR1_CELLSIZE_Pos)
|
||
#define SDRAMC_CR1_HIGHSPEED_Pos 23 //<2F><>hclk<6C><6B><EFBFBD><EFBFBD>100MHzʱ<7A><CAB1><EFBFBD><EFBFBD>һλ<D2BB><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ1<CEAA><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0
|
||
#define SDRAMC_CR1_HIGHSPEED_Msk (0x01 << SDRAMC_CR1_HIGHSPEED_Pos)
|
||
|
||
#define SDRAMC_REFRESH_RATE_Pos 0
|
||
#define SDRAMC_REFRESH_RATE_Msk (0xFFF << SDRAMC_REFRESH_RATE_Pos)
|
||
#define SDRAMC_REFRESH_EN_Pos 12
|
||
#define SDRAMC_REFRESH_EN_Msk (0x01 << SDRAMC_REFRESH_EN_Pos)
|
||
|
||
#define SDRAMC_LATCH_INEDGE_Pos 0 //<2F>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<41>ж<EFBFBD><D0B6>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>ݣ<EFBFBD>0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 <20>½<EFBFBD><C2BD><EFBFBD>
|
||
#define SDRAMC_LATCH_INEDGE_Msk (0x01 << SDRAMC_LATCH_INEDGE_Pos)
|
||
#define SDRAMC_LATCH_OUTEDGE_Pos 1 //<2F>ĸ<EFBFBD><C4B8><EFBFBD>ȥ<EFBFBD><C8A5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD>1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0 <20>½<EFBFBD><C2BD><EFBFBD>
|
||
#define SDRAMC_LATCH_OUTEDGE_Msk (0x01 << SDRAMC_LATCH_OUTEDGE_Pos)
|
||
#define SDRAMC_LATCH_WAITST_Pos 2
|
||
#define SDRAMC_LATCH_WAITST_Msk (0x01 << SDRAMC_LATCH_WAITST_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t IE;
|
||
|
||
__IO uint32_t IF; //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t IM;
|
||
|
||
__IO uint32_t CR;
|
||
|
||
__IO uint32_t ADDR;
|
||
|
||
__IO uint32_t CMD;
|
||
} NORFLC_TypeDef;
|
||
|
||
|
||
#define NORFLC_IE_FINISH_Pos 0
|
||
#define NORFLC_IE_FINISH_Msk (0x01 << NORFLC_IE_FINISH_Pos)
|
||
#define NORFLC_IE_TIMEOUT_Pos 1
|
||
#define NORFLC_IE_TIMEOUT_Msk (0x01 << NORFLC_IE_TIMEOUT_Pos)
|
||
|
||
#define NORFLC_IF_FINISH_Pos 0
|
||
#define NORFLC_IF_FINISH_Msk (0x01 << NORFLC_IF_FINISH_Pos)
|
||
#define NORFLC_IF_TIMEOUT_Pos 1
|
||
#define NORFLC_IF_TIMEOUT_Msk (0x01 << NORFLC_IF_TIMEOUT_Pos)
|
||
|
||
#define NORFLC_IM_FINISH_Pos 0
|
||
#define NORFLC_IM_FINISH_Msk (0x01 << NORFLC_IM_FINISH_Pos)
|
||
#define NORFLC_IM_TIMEOUT_Pos 1
|
||
#define NORFLC_IM_TIMEOUT_Msk (0x01 << NORFLC_IM_TIMEOUT_Pos)
|
||
|
||
#define NORFLC_CR_RDTIME_Pos 0 //Oen<65>½<EFBFBD><C2BD>غ<EFBFBD><D8BA><EFBFBD><EFBFBD>ٸ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ں<EFBFBD><DABA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>ݡ<EFBFBD>0<EFBFBD><30>ʾ1<CABE><31>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define NORFLC_CR_RDTIME_Msk (0x1F << NORFLC_CR_RDTIME_Pos)
|
||
#define NORFLC_CR_WRTIME_Pos 5 //<2F><><EFBFBD><EFBFBD>Wen<65>ĵ͵<C4B5>ƽ<EFBFBD><C6BD><EFBFBD>ȡ<EFBFBD>0<EFBFBD><30>ʾ1<CABE><31>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define NORFLC_CR_WRTIME_Msk (0x07 << NORFLC_CR_WRTIME_Pos)
|
||
#define NORFLC_CR_BYTEIF_Pos 8 //<2F>ⲿNOR FLASH<53><48><EFBFBD>ݿ<EFBFBD><DDBF>ȣ<EFBFBD>1 8λ 0 16λ
|
||
#define NORFLC_CR_BYTEIF_Msk (0x01 << NORFLC_CR_BYTEIF_Pos)
|
||
|
||
#define NORFLC_CMD_DATA_Pos 0 //<2F><>PROGRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD>DATA<54><41>Ҫд<D2AA><D0B4>NOR FLASH<53><48><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD>READ<41><44><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD>DATA<54>Ǵ<EFBFBD>NOR FLASH<53><48><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD><EFBFBD>
|
||
#define NORFLC_CMD_DATA_Msk (0xFFFF << NORFLC_CMD_DATA_Pos)
|
||
#define NORFLC_CMD_CMD_Pos 16 //<2F><>Ҫִ<D2AA>е<EFBFBD><D0B5><EFBFBD><EFBFBD>0 READ 1 RESET 2 AUTOMATIC SELECT 3 PROGRAM 4 CHIP ERASE 5 SECTOR ERASE
|
||
#define NORFLC_CMD_CMD_Msk (0x07 << NORFLC_CMD_CMD_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t CR;
|
||
|
||
__O uint32_t DATAIN;
|
||
|
||
__IO uint32_t INIVAL;
|
||
|
||
__I uint32_t RESULT;
|
||
} CRC_TypeDef;
|
||
|
||
|
||
#define CRC_CR_EN_Pos 0
|
||
#define CRC_CR_EN_Msk (0x01 << CRC_CR_EN_Pos)
|
||
#define CRC_CR_OREV_Pos 1 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>ת
|
||
#define CRC_CR_OREV_Msk (0x01 << CRC_CR_OREV_Pos)
|
||
#define CRC_CR_ONOT_Pos 2 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ȡ<EFBFBD><C8A1>
|
||
#define CRC_CR_ONOT_Msk (0x01 << CRC_CR_ONOT_Pos)
|
||
#define CRC_CR_CRC16_Pos 3 //1 CRC16 0 CRC32
|
||
#define CRC_CR_CRC16_Msk (0x01 << CRC_CR_CRC16_Pos)
|
||
#define CRC_CR_IBITS_Pos 4 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чλ<D0A7><CEBB> 0 32λ 1 16λ 2 8λ
|
||
#define CRC_CR_IBITS_Msk (0x03 << CRC_CR_IBITS_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t MINSEC; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t DATHUR; //<2F><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t MONDAY; //<2F><><EFBFBD>ܼ<EFBFBD><DCBC><EFBFBD>
|
||
|
||
__IO uint32_t YEAR; //[11:0] <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֧<EFBFBD><D6A7>1901-2199
|
||
|
||
__IO uint32_t MINSECAL; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t DAYHURAL; //<2F><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t LOAD; //<2F><><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD><EFBFBD>е<EFBFBD>ֵͬ<D6B5><CDAC><EFBFBD><EFBFBD>RTC<54>У<EFBFBD>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t IE;
|
||
|
||
__IO uint32_t IF; //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t EN; //[0] 1 RTCʹ<43><CAB9>
|
||
|
||
__IO uint32_t CFGABLE; //[0] 1 RTC<54><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
__IO uint32_t TRIM; //ʱ<>ӵ<EFBFBD><D3B5><EFBFBD>
|
||
|
||
__IO uint32_t TRIMM; //ʱ<><CAB1><EFBFBD><CEA2><EFBFBD><EFBFBD>
|
||
} RTC_TypeDef;
|
||
|
||
|
||
#define RTC_LOAD_TIME_Pos 0
|
||
#define RTC_LOAD_TIME_Msk (0x01 << RTC_LOAD_TIME_Pos)
|
||
#define RTC_LOAD_ALARM_Pos 1
|
||
#define RTC_LOAD_ALARM_Msk (0x01 << RTC_LOAD_ALARM_Pos)
|
||
|
||
#define RTC_MINSEC_SEC_Pos 0 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ0--59
|
||
#define RTC_MINSEC_SEC_Msk (0x3F << RTC_MINSEC_SEC_Pos)
|
||
#define RTC_MINSEC_MIN_Pos 6 //<2F><><EFBFBD>Ӽ<EFBFBD><D3BC><EFBFBD><EFBFBD><EFBFBD>ȡֵ0--59
|
||
#define RTC_MINSEC_MIN_Msk (0x3F << RTC_MINSEC_MIN_Pos)
|
||
|
||
#define RTC_DATHUR_HOUR_Pos 0 //Сʱ<D0A1><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ0--23
|
||
#define RTC_DATHUR_HOUR_Msk (0x1F << RTC_DATHUR_HOUR_Pos)
|
||
#define RTC_DATHUR_DATE_Pos 5 //date of month<74><68>ȡֵ1--31
|
||
#define RTC_DATHUR_DATE_Msk (0x1F << RTC_DATHUR_DATE_Pos)
|
||
|
||
#define RTC_MONDAY_DAY_Pos 0 //day of week<65><6B>ȡֵ0--6
|
||
#define RTC_MONDAY_DAY_Msk (0x07 << RTC_MONDAY_DAY_Pos)
|
||
#define RTC_MONDAY_MON_Pos 3 //<2F>·ݼ<C2B7><DDBC><EFBFBD><EFBFBD><EFBFBD>ȡֵ1--12
|
||
#define RTC_MONDAY_MON_Msk (0x0F << RTC_MONDAY_MON_Pos)
|
||
|
||
#define RTC_MINSECAL_SEC_Pos 0 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define RTC_MINSECAL_SEC_Msk (0x3F << RTC_MINSECAL_SEC_Pos)
|
||
#define RTC_MINSECAL_MIN_Pos 6 //<2F><><EFBFBD>ӷ<EFBFBD><D3B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
#define RTC_MINSECAL_MIN_Msk (0x3F << RTC_MINSECAL_MIN_Pos)
|
||
|
||
#define RTC_DAYHURAL_HOUR_Pos 0 //<2F><><EFBFBD><EFBFBD>Сʱ<D0A1><CAB1><EFBFBD><EFBFBD>
|
||
#define RTC_DAYHURAL_HOUR_Msk (0x1F << RTC_DAYHURAL_HOUR_Pos)
|
||
#define RTC_DAYHURAL_SUN_Pos 5 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
|
||
#define RTC_DAYHURAL_SUN_Msk (0x01 << RTC_DAYHURAL_SUN_Pos)
|
||
#define RTC_DAYHURAL_MON_Pos 6 //<2F><>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
|
||
#define RTC_DAYHURAL_MON_Msk (0x01 << RTC_DAYHURAL_MON_Pos)
|
||
#define RTC_DAYHURAL_TUE_Pos 7 //<2F>ܶ<EFBFBD><DCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
|
||
#define RTC_DAYHURAL_TUE_Msk (0x01 << RTC_DAYHURAL_TUE_Pos)
|
||
#define RTC_DAYHURAL_WED_Pos 8 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
|
||
#define RTC_DAYHURAL_WED_Msk (0x01 << RTC_DAYHURAL_WED_Pos)
|
||
#define RTC_DAYHURAL_THU_Pos 9 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
|
||
#define RTC_DAYHURAL_THU_Msk (0x01 << RTC_DAYHURAL_THU_Pos)
|
||
#define RTC_DAYHURAL_FRI_Pos 10 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
|
||
#define RTC_DAYHURAL_FRI_Msk (0x01 << RTC_DAYHURAL_FRI_Pos)
|
||
#define RTC_DAYHURAL_SAT_Pos 11 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
|
||
#define RTC_DAYHURAL_SAT_Msk (0x01 << RTC_DAYHURAL_SAT_Pos)
|
||
|
||
#define RTC_IE_SEC_Pos 0 //<2F><><EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
|
||
#define RTC_IE_SEC_Msk (0x01 << RTC_IE_SEC_Pos)
|
||
#define RTC_IE_MIN_Pos 1
|
||
#define RTC_IE_MIN_Msk (0x01 << RTC_IE_MIN_Pos)
|
||
#define RTC_IE_HOUR_Pos 2
|
||
#define RTC_IE_HOUR_Msk (0x01 << RTC_IE_HOUR_Pos)
|
||
#define RTC_IE_DATE_Pos 3
|
||
#define RTC_IE_DATE_Msk (0x01 << RTC_IE_DATE_Pos)
|
||
#define RTC_IE_ALARM_Pos 4
|
||
#define RTC_IE_ALARM_Msk (0x01 << RTC_IE_ALARM_Pos)
|
||
|
||
#define RTC_IF_SEC_Pos 0 //д1<D0B4><31><EFBFBD><EFBFBD>
|
||
#define RTC_IF_SEC_Msk (0x01 << RTC_IF_SEC_Pos)
|
||
#define RTC_IF_MIN_Pos 1
|
||
#define RTC_IF_MIN_Msk (0x01 << RTC_IF_MIN_Pos)
|
||
#define RTC_IF_HOUR_Pos 2
|
||
#define RTC_IF_HOUR_Msk (0x01 << RTC_IF_HOUR_Pos)
|
||
#define RTC_IF_DATE_Pos 3
|
||
#define RTC_IF_DATE_Msk (0x01 << RTC_IF_DATE_Pos)
|
||
#define RTC_IF_ALARM_Pos 4
|
||
#define RTC_IF_ALARM_Msk (0x01 << RTC_IF_ALARM_Pos)
|
||
|
||
#define RTC_TRIM_ADJ_Pos 0 //<2F><><EFBFBD>ڵ<EFBFBD><DAB5><EFBFBD>BASECNT<4E>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD><C4AC>Ϊ32768<36><38><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DECΪ1<CEAA><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD><DAB5><EFBFBD>Ϊ32768-ADJ<44><4A><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ32768+ADJ
|
||
#define RTC_TRIM_ADJ_Msk (0xFF << RTC_TRIM_ADJ_Pos)
|
||
#define RTC_TRIM_DEC_Pos 8
|
||
#define RTC_TRIM_DEC_Msk (0x01 << RTC_TRIM_DEC_Pos)
|
||
|
||
#define RTC_TRIMM_CYCLE_Pos 0 //<2F><><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><CEA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>INCΪ1<CEAA><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>n<EFBFBD><6E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD><DAB5><EFBFBD>Ϊ(32768<36><38>ADJ)+1,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ(32768<36><38>ADJ)-1
|
||
//cycles=0ʱ<30><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><CEA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cycles=1<><31><EFBFBD><EFBFBD>nΪ2<CEAA><32>cycles=7<><37><EFBFBD><EFBFBD>nΪ8<CEAA><38><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD>
|
||
#define RTC_TRIMM_CYCLE_Msk (0x07 << RTC_TRIMM_CYCLE_Pos)
|
||
#define RTC_TRIMM_INC_Pos 3
|
||
#define RTC_TRIMM_INC_Msk (0x01 << RTC_TRIMM_INC_Pos)
|
||
|
||
|
||
|
||
|
||
typedef struct {
|
||
__IO uint32_t LOAD; //ι<><CEB9>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>װ<EFBFBD><D7B0>LOADֵ
|
||
|
||
__I uint32_t VALUE;
|
||
|
||
__IO uint32_t CR;
|
||
|
||
__IO uint32_t IF; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0ʱӲ<CAB1><D3B2><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д1<D0B4><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־
|
||
|
||
__IO uint32_t FEED; //д0x55ι<35><CEB9>
|
||
} WDT_TypeDef;
|
||
|
||
|
||
#define WDT_CR_EN_Pos 0
|
||
#define WDT_CR_EN_Msk (0x01 << WDT_CR_EN_Pos)
|
||
#define WDT_CR_RSTEN_Pos 1
|
||
#define WDT_CR_RSTEN_Msk (0x01 << WDT_CR_RSTEN_Pos)
|
||
|
||
|
||
/******************************************************************************/
|
||
/* Peripheral memory map */
|
||
/******************************************************************************/
|
||
#define RAM_BASE 0x20000000
|
||
#define AHB_BASE 0x40000000
|
||
#define APB_BASE 0x40010000
|
||
|
||
#define NORFLC_BASE 0x60000000
|
||
#define NORFLM_BASE 0x61000000
|
||
|
||
#define SRAMC_BASE 0x68000000
|
||
#define SRAMM_BASE 0x69000000
|
||
|
||
#define SDRAMC_BASE 0x78000000
|
||
#define SDRAMM_BASE 0x70000000
|
||
|
||
/* AHB Peripheral memory map */
|
||
#define SYS_BASE (AHB_BASE + 0x00000)
|
||
|
||
#define DMA_BASE (AHB_BASE + 0x01000)
|
||
|
||
#define LCD_BASE (AHB_BASE + 0x02000)
|
||
|
||
#define CRC_BASE (AHB_BASE + 0x03000)
|
||
|
||
#define SDIO_BASE (AHB_BASE + 0x04000)
|
||
|
||
/* APB Peripheral memory map */
|
||
#define PORT_BASE (APB_BASE + 0x00000)
|
||
|
||
#define GPIOA_BASE (APB_BASE + 0x01000)
|
||
#define GPIOB_BASE (APB_BASE + 0x02000)
|
||
#define GPIOC_BASE (APB_BASE + 0x03000)
|
||
#define GPIOD_BASE (APB_BASE + 0x04000)
|
||
#define GPIOM_BASE (APB_BASE + 0x05000)
|
||
#define GPION_BASE (APB_BASE + 0x06000)
|
||
#define GPIOP_BASE (APB_BASE + 0x08000)
|
||
|
||
#define TIMR0_BASE (APB_BASE + 0x07000)
|
||
#define TIMR1_BASE (APB_BASE + 0x0700C)
|
||
#define TIMR2_BASE (APB_BASE + 0x07018)
|
||
#define TIMR3_BASE (APB_BASE + 0x07024)
|
||
#define TIMR4_BASE (APB_BASE + 0x07030)
|
||
#define TIMR5_BASE (APB_BASE + 0x0703C)
|
||
#define TIMRG_BASE (APB_BASE + 0x07060)
|
||
|
||
#define WDT_BASE (APB_BASE + 0x09000)
|
||
|
||
#define PWM0_BASE (APB_BASE + 0x0A000)
|
||
#define PWM1_BASE (APB_BASE + 0x0A020)
|
||
#define PWM2_BASE (APB_BASE + 0x0A040)
|
||
#define PWM3_BASE (APB_BASE + 0x0A060)
|
||
#define PWM4_BASE (APB_BASE + 0x0A080)
|
||
#define PWM5_BASE (APB_BASE + 0x0A0A0)
|
||
#define PWMG_BASE (APB_BASE + 0x0A180)
|
||
|
||
#define RTC_BASE (APB_BASE + 0x0B000)
|
||
|
||
#define ADC0_BASE (APB_BASE + 0x0C000)
|
||
#define ADC1_BASE (APB_BASE + 0x0D000)
|
||
|
||
#define FLASH_BASE (APB_BASE + 0x0F000)
|
||
|
||
#define UART0_BASE (APB_BASE + 0x10000)
|
||
#define UART1_BASE (APB_BASE + 0x11000)
|
||
#define UART2_BASE (APB_BASE + 0x12000)
|
||
#define UART3_BASE (APB_BASE + 0x13000)
|
||
|
||
#define I2C0_BASE (APB_BASE + 0x18000)
|
||
#define I2C1_BASE (APB_BASE + 0x19000)
|
||
|
||
#define SPI0_BASE (APB_BASE + 0x1C000)
|
||
#define SPI1_BASE (APB_BASE + 0x1D000)
|
||
|
||
#define CAN_BASE (APB_BASE + 0x20000)
|
||
|
||
|
||
/******************************************************************************/
|
||
/* Peripheral declaration */
|
||
/******************************************************************************/
|
||
#define SYS ((SYS_TypeDef *) SYS_BASE)
|
||
|
||
#define PORT ((PORT_TypeDef *) PORT_BASE)
|
||
|
||
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
||
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
||
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
||
#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE)
|
||
#define GPION ((GPIO_TypeDef *) GPION_BASE)
|
||
#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE)
|
||
|
||
#define TIMR0 ((TIMR_TypeDef *) TIMR0_BASE)
|
||
#define TIMR1 ((TIMR_TypeDef *) TIMR1_BASE)
|
||
#define TIMR2 ((TIMR_TypeDef *) TIMR2_BASE)
|
||
#define TIMR3 ((TIMR_TypeDef *) TIMR3_BASE)
|
||
#define TIMR4 ((TIMR_TypeDef *) TIMR4_BASE)
|
||
#define TIMR5 ((TIMR_TypeDef *) TIMR5_BASE)
|
||
#define TIMRG ((TIMRG_TypeDef*) TIMRG_BASE)
|
||
|
||
#define UART0 ((UART_TypeDef *) UART0_BASE)
|
||
#define UART1 ((UART_TypeDef *) UART1_BASE)
|
||
#define UART2 ((UART_TypeDef *) UART2_BASE)
|
||
#define UART3 ((UART_TypeDef *) UART3_BASE)
|
||
|
||
#define SPI0 ((SPI_TypeDef *) SPI0_BASE)
|
||
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
||
|
||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
|
||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
||
|
||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE)
|
||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||
|
||
#define PWM0 ((PWM_TypeDef *) PWM0_BASE)
|
||
#define PWM1 ((PWM_TypeDef *) PWM1_BASE)
|
||
#define PWM2 ((PWM_TypeDef *) PWM2_BASE)
|
||
#define PWM3 ((PWM_TypeDef *) PWM3_BASE)
|
||
#define PWM4 ((PWM_TypeDef *) PWM4_BASE)
|
||
#define PWM5 ((PWM_TypeDef *) PWM5_BASE)
|
||
#define PWMG ((PWMG_TypeDef *) PWMG_BASE)
|
||
|
||
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
|
||
|
||
#define DMA ((DMA_TypeDef *) DMA_BASE)
|
||
|
||
#define CAN ((CAN_TypeDef *) CAN_BASE)
|
||
|
||
#define LCD ((LCD_TypeDef *) LCD_BASE)
|
||
|
||
#define CRC ((CRC_TypeDef *) CRC_BASE)
|
||
|
||
#define RTC ((RTC_TypeDef *) RTC_BASE)
|
||
|
||
#define WDT ((WDT_TypeDef *) WDT_BASE)
|
||
|
||
#define FLASH ((FLASH_Typedef*) FLASH_BASE)
|
||
|
||
#define SRAMC ((SRAMC_TypeDef*) SRAMC_BASE)
|
||
|
||
#define NORFLC ((NORFLC_TypeDef*) NORFLC_BASE)
|
||
|
||
#define SDRAMC ((SDRAMC_TypeDef*) SDRAMC_BASE)
|
||
|
||
|
||
|
||
typedef void (* Func_void_void) (void);
|
||
|
||
|
||
#include "SWM320_port.h"
|
||
#include "SWM320_gpio.h"
|
||
#include "SWM320_exti.h"
|
||
#include "SWM320_timr.h"
|
||
#include "SWM320_uart.h"
|
||
#include "SWM320_spi.h"
|
||
#include "SWM320_i2c.h"
|
||
#include "SWM320_pwm.h"
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#include "SWM320_adc.h"
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#include "SWM320_dma.h"
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#include "SWM320_lcd.h"
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#include "SWM320_can.h"
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#include "SWM320_sdio.h"
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||
#include "SWM320_flash.h"
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||
#include "SWM320_norflash.h"
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||
#include "SWM320_sdram.h"
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#include "SWM320_sram.h"
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#include "SWM320_crc.h"
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#include "SWM320_rtc.h"
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#include "SWM320_wdt.h"
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#endif //__SWM320_H__
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