381 lines
10 KiB
C
381 lines
10 KiB
C
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-02-26 Yilin Sun Initial version.
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "fsl_ctimer.h"
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#define MCX_PWM_MATCH_COUNT 4
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#ifdef RT_USING_PWM
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typedef struct
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{
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struct rt_device_pwm pwm_device;
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CTIMER_Type *ct_instance;
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uint32_t counter_period_ps;
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} mcx_pwm_obj_t;
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static CTIMER_Type *mcx_pwm_instances[] = CTIMER_BASE_PTRS;
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static mcx_pwm_obj_t mcx_pwm_list[ARRAY_SIZE(mcx_pwm_instances)];
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static int mcx_pwm_current_period_channel(mcx_pwm_obj_t *pwm)
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{
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CTIMER_Type *ct = (CTIMER_Type *)pwm->ct_instance;
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uint32_t mcr = ct->MCR;
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for (uint8_t i = 0; i < 4; i++)
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{
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if (mcr & (1U << (3 * i + CTIMER_MCR_MR0R_SHIFT)))
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{
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return i;
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}
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}
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return -1;
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}
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static int mcx_pwm_first_free_channel(mcx_pwm_obj_t *pwm)
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{
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CTIMER_Type *ct = (CTIMER_Type *)pwm->ct_instance;
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int pc = mcx_pwm_current_period_channel(pwm);
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uint32_t pwmc = ct->PWMC;
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for (uint8_t i = 0; i < 4; i++)
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{
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if (pwmc & (1U << i))
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{
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/* Skip this channel if there's an active PWM output */
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continue;
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}
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if (i == pc)
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{
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/* Skip this channel if this channel is the current period channel */
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continue;
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}
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return i;
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}
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/* There are no free channels left. */
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return -1;
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}
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static int mcx_pwm_period_set(mcx_pwm_obj_t *pwm, uint32_t period_ns)
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{
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CTIMER_Type *ct = (CTIMER_Type *)pwm->ct_instance;
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int p_channel = mcx_pwm_current_period_channel(pwm);
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if (p_channel < 0)
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{
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return -EINVAL;
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}
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/* Store new values in shadow registers */
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ct->MSR[p_channel] = period_ns * 1000 / pwm->counter_period_ps;
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/* Enable period channel interrupt to check a reload event occurs.
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* Since interrupts are not configured from NVIC, so no ISR will occur.
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* Check IR[MRnINT] for reload point.
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*/
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uint32_t mcr_mask = (CTIMER_MCR_MR0RL_MASK << p_channel) | (CTIMER_MCR_MR0I_MASK << (3 * p_channel));
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for (uint8_t i = 0; i < 4; i++)
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{
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if (ct->PWMC & (1U << i))
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{
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/* Channel PWM output is enabled, calculate new values and store into shadow registers */
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uint32_t new_mr = ct->MR[i] * ct->MSR[p_channel] / ct->MR[p_channel];
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ct->MSR[i] = new_mr;
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/* Update MRnRL map */
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mcr_mask |= CTIMER_MCR_MR0RL_MASK << i;
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}
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}
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/* Reload MRs on next counter reset, enable reload MR interrupt */
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ct->MCR |= mcr_mask;
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while ((ct->IR & (CTIMER_IR_MR0INT_MASK << p_channel)) == 0U)
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{
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/* -- */
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}
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/* Disable reload channel interrupt and MSR synchronization */
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ct->MCR &= ~mcr_mask;
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/* Clear interrupt flags. */
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ct->IR |= (CTIMER_IR_MR0INT_MASK << p_channel);
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return 0;
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}
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static int mcx_pwm_period_get(mcx_pwm_obj_t *pwm, uint32_t *period_ns)
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{
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CTIMER_Type *ct = (CTIMER_Type *)pwm->ct_instance;
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int p_channel = mcx_pwm_current_period_channel(pwm);
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if (p_channel < 0)
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{
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return -1;
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}
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*period_ns = ct->MR[p_channel] * pwm->counter_period_ps / 1000;
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return 0;
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}
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static int mcx_pwm_pulse_set(mcx_pwm_obj_t *pwm, uint8_t channel, uint32_t pulse_ns)
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{
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CTIMER_Type *ct = (CTIMER_Type *)pwm->ct_instance;
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int p_channel = mcx_pwm_current_period_channel(pwm);
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if (p_channel < 0)
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{
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return -1;
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}
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/* Up-counting counters, the polarity is inversed */
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ct->MSR[channel] = ct->MR[p_channel] - pulse_ns * 1000 / pwm->counter_period_ps;
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/* Reload MRn on the next cycle */
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ct->MCR |= (CTIMER_MCR_MR0RL_MASK << channel);
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/* Wait for new duty cycle loaded into the MRn */
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while (ct->MR[channel] != ct->MSR[channel])
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{
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/* -- */
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}
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/* Disable shadow register updates */
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ct->MCR &= ~(CTIMER_MCR_MR0RL_MASK << channel);
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return 0;
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}
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static int mcx_pwm_pulse_get(mcx_pwm_obj_t *pwm, uint8_t channel, uint32_t *pulse_ns)
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{
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CTIMER_Type *ct = (CTIMER_Type *)pwm->ct_instance;
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int p_channel = mcx_pwm_current_period_channel(pwm);
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if (p_channel < 0)
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{
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return -1;
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}
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/* Up-counting counters, the polarity is inversed */
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*pulse_ns = (ct->MR[p_channel] - ct->MR[channel]) * pwm->counter_period_ps / 1000;
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return 0;
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}
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static rt_err_t mcx_drv_pwm_get(mcx_pwm_obj_t *pwm, struct rt_pwm_configuration *configuration)
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{
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if (mcx_pwm_period_get(pwm, &configuration->period) < 0)
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{
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return -RT_EFAULT;
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}
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if (mcx_pwm_pulse_get(pwm, configuration->channel, &configuration->pulse) < 0)
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{
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return -RT_EFAULT;
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}
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return RT_EOK;
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}
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static rt_err_t mcx_drv_pwm_set(mcx_pwm_obj_t *pwm, struct rt_pwm_configuration *configuration)
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{
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CTIMER_Type *ct = pwm->ct_instance;
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uint32_t period = configuration->period * 1000 / pwm->counter_period_ps;
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uint8_t channel = configuration->channel;
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if ((ct->TCR & CTIMER_TCR_CEN_MASK) == 0U)
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{
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/* There's two conditions for a all-zero TCR: either a reset condition or timer is stopped. */
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/* In either case, we need to initialize the timer instance (AHB RST CTRL). */
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/* TODO: Do not use SDK functions */
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ctimer_config_t ct_cfg =
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{
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.mode = kCTIMER_TimerMode,
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.prescale = 1U,
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};
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/* Frequency: 150MHz max., we got 32bit counters, we can take that. */
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/* Approx. maximum period: 28.6 seconds. */
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CTIMER_Init(ct, &ct_cfg);
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/* Current timer is not running, we are the first channel being configured. */
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ct->TC = 0U; /* Reset counter */
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ct->PC = 0U; /* Reset prescaler counter */
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ct->PR = 0U; /* Prescaler, divide by 1 to get best resolution */
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ct->MCR = 0U; /* Reset interrupt and reset condition */
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ct->EMR = 0U; /* Do nothing on match event and output 0 as default state */
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ct->PWMC = 0U; /* Disable all PWM channels, outputs will be controlled by EMn */
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/* Here, we have a favoritism of using channel 3 as period channel, unless channel 3 is used for output */
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if (channel != 3)
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{
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ct->MR[3] = period;
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ct->MCR |= CTIMER_MCR_MR3R_MASK;
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}
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else
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{
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/* Use channel 2 as period channel. */
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ct->MR[2] = period;
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ct->MCR |= CTIMER_MCR_MR2R_MASK;
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}
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/* Start counter */
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ct->TCR |= CTIMER_TCR_CEN_MASK;
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}
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else
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{
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/*
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* Due to the nature of the CTimer, one of the 4 match channels is needed for period control (frequency)
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* To find out which one is the current period channel, check the MRxR bit for each match output.
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* If we are configuring the same match being used as periodic channel, configure the next free match as period
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* then current channel can be re-used. If all 4 channels are in use then the function will fail with an errno.
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*/
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/* The timer is running, check whether we need to re-locate the period channel */
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int p_channel = mcx_pwm_current_period_channel(pwm);
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if (p_channel < 0)
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{
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return -RT_EINVAL;
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}
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if (p_channel == channel)
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{
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/* We need to re-locate the period channel */
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int f_channel = mcx_pwm_first_free_channel(pwm);
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if (f_channel < 0)
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{
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/* There's no free channel, bail out. */
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return -RT_EBUSY;
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}
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/* Transfer the period channel to first free channel */
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/* Step 1: Copy current period to first free channel */
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ct->MR[f_channel] = ct->MR[p_channel];
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/* Step 2: Enable reset for new period channel */
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/* Note: it's safe doing it here since both old and new channel MRs contains same value */
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ct->MCR |= (CTIMER_MCR_MR0R_MASK << (3 * f_channel));
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/* Step 3: Disable reset for old period channel */
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ct->MCR &= ~(CTIMER_MCR_MR0R_MASK << (3 * p_channel));
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/* The old period channel is now available for PWM output */
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p_channel = f_channel;
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}
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if (mcx_pwm_period_set(pwm, configuration->period) < 0)
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{
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return -RT_EINVAL;
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}
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}
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if (mcx_pwm_pulse_set(pwm, channel, configuration->pulse) < 0)
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{
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return -RT_EINVAL;
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}
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return 0;
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}
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static rt_err_t mcx_drv_pwm_enable(mcx_pwm_obj_t *pwm, struct rt_pwm_configuration *configuration)
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{
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CTIMER_Type *ct = (CTIMER_Type *)pwm->ct_instance;
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ct->PWMC |= (1U << configuration->channel);
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return 0;
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}
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static rt_err_t mcx_drv_pwm_disable(mcx_pwm_obj_t *pwm, struct rt_pwm_configuration *configuration)
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{
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CTIMER_Type *ct = (CTIMER_Type *)pwm->ct_instance;
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ct->PWMC &= ~(1U << configuration->channel);
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return 0;
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}
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static rt_err_t mcx_drv_pwm_control(struct rt_device_pwm *device, int cmd, void *args)
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{
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mcx_pwm_obj_t *pwm = device->parent.user_data;
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)args;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return mcx_drv_pwm_enable(pwm, configuration);
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case PWM_CMD_DISABLE:
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return mcx_drv_pwm_disable(pwm, configuration);
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case PWM_CMD_SET:
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return mcx_drv_pwm_set(pwm, configuration);
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case PWM_CMD_GET:
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return mcx_drv_pwm_get(pwm, configuration);
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default:
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return -RT_EINVAL;
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}
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return RT_EOK;
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}
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static struct rt_pwm_ops mcx_pwm_ops =
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{
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.control = mcx_drv_pwm_control,
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};
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int mcx_pwm_init(void)
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{
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rt_err_t ret;
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char name_buf[8];
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for (uint8_t i = 0; i < ARRAY_SIZE(mcx_pwm_instances); i++)
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{
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mcx_pwm_list[i].ct_instance = mcx_pwm_instances[i];
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mcx_pwm_list[i].counter_period_ps = 1000000000000ULL / CLOCK_GetCTimerClkFreq(i);
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rt_snprintf(name_buf, sizeof(name_buf), "pwm%d", i);
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ret = rt_device_pwm_register(&mcx_pwm_list[i].pwm_device, name_buf, &mcx_pwm_ops, &mcx_pwm_list[i]);
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if (ret != RT_EOK)
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{
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return ret;
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}
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}
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return RT_EOK;
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}
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INIT_DEVICE_EXPORT(mcx_pwm_init);
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#endif /* RT_USING_PWM */
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