212 lines
6.4 KiB
C
212 lines
6.4 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first implementation
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* 2019-03-11 JiCheng Change clock setting for RT1020
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*/
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#include <stdint.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "drv_uart.h"
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#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
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static struct rt_memheap system_heap;
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#endif
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const clock_enet_pll_config_t enetPllConfig =
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{
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.enableClkOutput500M = true,
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};
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/* SYS PLL configuration for RUN mode */
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const clock_sys_pll_config_t sysPllConfig = { .loopDivider = 1U };
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/* USB1 PLL configuration for RUN mode */
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const clock_usb_pll_config_t usb1PllConfig = { .loopDivider = 0U };
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static void BOARD_BootClockGate(void)
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{
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// /* Disable all unused peripheral clock */
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// CCM->CCGR0 = 0x00C0000FU;
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// CCM->CCGR1 = 0x30000000U;
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// CCM->CCGR2 = 0x003F0030U;
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// CCM->CCGR3 = 0xF0000330U;
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// CCM->CCGR4 = 0x0000FF3CU;
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// CCM->CCGR5 = 0xF000330FU;
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// CCM->CCGR6 = 0x00FC0300U;
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}
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static void BOARD_BootClockRUN(void)
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{
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/* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */
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CLOCK_SetXtalFreq(24000000U);
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CLOCK_SetRtcXtalFreq(32768U);
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CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */
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CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
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/* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to max 500Mhz */
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DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
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#if defined (CPU_MIMXRT1021DAF5A) || defined (CPU_MIMXRT1021DAG5A)
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CLOCK_InitEnetPll(&enetPllConfig); /* Configure ENET PLL to 500M for AHBCLK */
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#elif defined (CPU_MIMXRT1021CAF4A) || defined (CPU_MIMXRT1021CAG4A)
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CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL */
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CLOCK_InitSysPfd(kCLOCK_Pfd3, 24);/* PLL2_PFD3 = 396MHz for AHB CLOOK ROOT */
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#endif
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#ifndef SKIP_USB_PLL_INIT
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CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
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#endif
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#if defined (CPU_MIMXRT1021DAF5A) || defined (CPU_MIMXRT1021DAG5A)
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CLOCK_SetDiv(kCLOCK_ArmDiv, 0x0); /* Set ARM PODF to 0, divide by 2 */
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CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */
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CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */
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CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL6, 500M */
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CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
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#elif defined (CPU_MIMXRT1021CAF4A) || defined (CPU_MIMXRT1021CAG4A)
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CLOCK_SetDiv(kCLOCK_ArmDiv, 0x0); /* Set ARM PODF to 0, divide by 1 */
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CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */
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CLOCK_SetDiv(kCLOCK_IpgDiv, 0x2); /* Set IPG PODF to 2, divede by 3 */
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CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x2); /* Set PRE_PERIPH_CLK to PLL2_PFD3, 396MHz */
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CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
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#endif
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/* Disable unused clock */
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BOARD_BootClockGate();
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/* Power down all unused PLL */
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CLOCK_DeinitAudioPll();
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/* iomuxc clock (iomuxc_clk_enable): 0x03u */
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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/* Update core clock */
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SystemCoreClockUpdate();
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}
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/* MPU configuration. */
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static void BOARD_ConfigMPU(void)
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{
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/* Disable I cache and D cache */
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SCB_DisableICache();
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SCB_DisableDCache();
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/* Disable MPU */
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ARM_MPU_Disable();
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/* Region 0 setting */
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MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 1 setting */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 2 setting */
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// spi flash: normal type, cacheable, no bufferable, no shareable
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 3 setting */
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MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 4 setting */
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MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 5 setting */
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MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 6 setting */
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MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
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#if defined(SDRAM_MPU_INIT)
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/* Region 7 setting */
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MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
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/* Region 8 setting */
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MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
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#endif
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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/* Enable I cache and D cache */
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SCB_EnableDCache();
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SCB_EnableICache();
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}
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/**
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* This is the timer interrupt service routine.
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*
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*/
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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void SystemInitHook(void)
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{
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BOARD_ConfigMPU();
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#if defined(RT_USING_SDRAM)
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extern int imxrt_sdram_init(void);
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imxrt_sdram_init();
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#endif
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}
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/**
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* This function will initial rt1021 board.
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*/
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void rt_hw_board_init()
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{
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BOARD_BootClockRUN();
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SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#ifdef RT_USING_HEAP
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#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
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rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END);
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rt_system_heap_init((void *)SDRAM_BEGIN, (void *)SDRAM_END);
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rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
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rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE);
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#else
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rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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#endif
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}
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/*@}*/
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