491 lines
24 KiB
C
491 lines
24 KiB
C
//*****************************************************************************
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//
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// am_reg_clkgen.h
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//! @file
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//!
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//! @brief Register macros for the CLKGEN module
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_REG_CLKGEN_H
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#define AM_REG_CLKGEN_H
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//*****************************************************************************
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//
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// Instance finder. (1 instance(s) available)
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//
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//*****************************************************************************
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#define AM_REG_CLKGEN_NUM_MODULES 1
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#define AM_REG_CLKGENn(n) \
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(REG_CLKGEN_BASEADDR + 0x00000000 * n)
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//*****************************************************************************
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//
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// Register offsets.
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//
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//*****************************************************************************
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#define AM_REG_CLKGEN_CALXT_O 0x00000000
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#define AM_REG_CLKGEN_CALRC_O 0x00000004
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#define AM_REG_CLKGEN_ACALCTR_O 0x00000008
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#define AM_REG_CLKGEN_OCTRL_O 0x0000000C
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#define AM_REG_CLKGEN_CLKOUT_O 0x00000010
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#define AM_REG_CLKGEN_CCTRL_O 0x00000018
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#define AM_REG_CLKGEN_STATUS_O 0x0000001C
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#define AM_REG_CLKGEN_HFADJ_O 0x00000020
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#define AM_REG_CLKGEN_CLOCKEN_O 0x00000028
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#define AM_REG_CLKGEN_CLOCKEN2_O 0x0000002C
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#define AM_REG_CLKGEN_CLOCKEN3_O 0x00000030
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#define AM_REG_CLKGEN_UARTEN_O 0x00000034
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#define AM_REG_CLKGEN_CLKKEY_O 0x00000014
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#define AM_REG_CLKGEN_INTEN_O 0x00000100
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#define AM_REG_CLKGEN_INTSTAT_O 0x00000104
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#define AM_REG_CLKGEN_INTCLR_O 0x00000108
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#define AM_REG_CLKGEN_INTSET_O 0x0000010C
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//*****************************************************************************
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//
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// Key values.
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//
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//*****************************************************************************
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#define AM_REG_CLKGEN_CLKKEY_KEYVAL 0x00000047
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//*****************************************************************************
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//
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// CLKGEN_INTEN - CLKGEN Interrupt Register: Enable
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//
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//*****************************************************************************
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// RTC Alarm interrupt
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#define AM_REG_CLKGEN_INTEN_ALM_S 3
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#define AM_REG_CLKGEN_INTEN_ALM_M 0x00000008
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#define AM_REG_CLKGEN_INTEN_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
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// XT Oscillator Fail interrupt
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#define AM_REG_CLKGEN_INTEN_OF_S 2
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#define AM_REG_CLKGEN_INTEN_OF_M 0x00000004
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#define AM_REG_CLKGEN_INTEN_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Autocalibration Complete interrupt
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#define AM_REG_CLKGEN_INTEN_ACC_S 1
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#define AM_REG_CLKGEN_INTEN_ACC_M 0x00000002
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#define AM_REG_CLKGEN_INTEN_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Autocalibration Fail interrupt
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#define AM_REG_CLKGEN_INTEN_ACF_S 0
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#define AM_REG_CLKGEN_INTEN_ACF_M 0x00000001
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#define AM_REG_CLKGEN_INTEN_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// CLKGEN_INTSTAT - CLKGEN Interrupt Register: Status
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//
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//*****************************************************************************
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// RTC Alarm interrupt
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#define AM_REG_CLKGEN_INTSTAT_ALM_S 3
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#define AM_REG_CLKGEN_INTSTAT_ALM_M 0x00000008
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#define AM_REG_CLKGEN_INTSTAT_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
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// XT Oscillator Fail interrupt
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#define AM_REG_CLKGEN_INTSTAT_OF_S 2
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#define AM_REG_CLKGEN_INTSTAT_OF_M 0x00000004
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#define AM_REG_CLKGEN_INTSTAT_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Autocalibration Complete interrupt
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#define AM_REG_CLKGEN_INTSTAT_ACC_S 1
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#define AM_REG_CLKGEN_INTSTAT_ACC_M 0x00000002
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#define AM_REG_CLKGEN_INTSTAT_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Autocalibration Fail interrupt
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#define AM_REG_CLKGEN_INTSTAT_ACF_S 0
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#define AM_REG_CLKGEN_INTSTAT_ACF_M 0x00000001
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#define AM_REG_CLKGEN_INTSTAT_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// CLKGEN_INTCLR - CLKGEN Interrupt Register: Clear
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//
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//*****************************************************************************
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// RTC Alarm interrupt
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#define AM_REG_CLKGEN_INTCLR_ALM_S 3
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#define AM_REG_CLKGEN_INTCLR_ALM_M 0x00000008
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#define AM_REG_CLKGEN_INTCLR_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
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// XT Oscillator Fail interrupt
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#define AM_REG_CLKGEN_INTCLR_OF_S 2
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#define AM_REG_CLKGEN_INTCLR_OF_M 0x00000004
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#define AM_REG_CLKGEN_INTCLR_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Autocalibration Complete interrupt
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#define AM_REG_CLKGEN_INTCLR_ACC_S 1
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#define AM_REG_CLKGEN_INTCLR_ACC_M 0x00000002
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#define AM_REG_CLKGEN_INTCLR_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Autocalibration Fail interrupt
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#define AM_REG_CLKGEN_INTCLR_ACF_S 0
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#define AM_REG_CLKGEN_INTCLR_ACF_M 0x00000001
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#define AM_REG_CLKGEN_INTCLR_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// CLKGEN_INTSET - CLKGEN Interrupt Register: Set
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//
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//*****************************************************************************
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// RTC Alarm interrupt
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#define AM_REG_CLKGEN_INTSET_ALM_S 3
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#define AM_REG_CLKGEN_INTSET_ALM_M 0x00000008
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#define AM_REG_CLKGEN_INTSET_ALM(n) (((uint32_t)(n) << 3) & 0x00000008)
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// XT Oscillator Fail interrupt
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#define AM_REG_CLKGEN_INTSET_OF_S 2
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#define AM_REG_CLKGEN_INTSET_OF_M 0x00000004
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#define AM_REG_CLKGEN_INTSET_OF(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Autocalibration Complete interrupt
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#define AM_REG_CLKGEN_INTSET_ACC_S 1
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#define AM_REG_CLKGEN_INTSET_ACC_M 0x00000002
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#define AM_REG_CLKGEN_INTSET_ACC(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Autocalibration Fail interrupt
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#define AM_REG_CLKGEN_INTSET_ACF_S 0
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#define AM_REG_CLKGEN_INTSET_ACF_M 0x00000001
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#define AM_REG_CLKGEN_INTSET_ACF(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// CLKGEN_CALXT - XT Oscillator Control
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//
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//*****************************************************************************
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// XT Oscillator calibration value
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#define AM_REG_CLKGEN_CALXT_CALXT_S 0
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#define AM_REG_CLKGEN_CALXT_CALXT_M 0x000007FF
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#define AM_REG_CLKGEN_CALXT_CALXT(n) (((uint32_t)(n) << 0) & 0x000007FF)
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//*****************************************************************************
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//
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// CLKGEN_CALRC - RC Oscillator Control
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//
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//*****************************************************************************
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// LFRC Oscillator calibration value
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#define AM_REG_CLKGEN_CALRC_CALRC_S 0
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#define AM_REG_CLKGEN_CALRC_CALRC_M 0x0003FFFF
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#define AM_REG_CLKGEN_CALRC_CALRC(n) (((uint32_t)(n) << 0) & 0x0003FFFF)
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//*****************************************************************************
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//
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// CLKGEN_ACALCTR - Autocalibration Counter
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//
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//*****************************************************************************
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// Autocalibration Counter result.
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#define AM_REG_CLKGEN_ACALCTR_ACALCTR_S 0
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#define AM_REG_CLKGEN_ACALCTR_ACALCTR_M 0x00FFFFFF
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#define AM_REG_CLKGEN_ACALCTR_ACALCTR(n) (((uint32_t)(n) << 0) & 0x00FFFFFF)
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//*****************************************************************************
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//
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// CLKGEN_OCTRL - Oscillator Control
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//
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//*****************************************************************************
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// Autocalibration control
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#define AM_REG_CLKGEN_OCTRL_ACAL_S 8
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#define AM_REG_CLKGEN_OCTRL_ACAL_M 0x00000700
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#define AM_REG_CLKGEN_OCTRL_ACAL(n) (((uint32_t)(n) << 8) & 0x00000700)
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#define AM_REG_CLKGEN_OCTRL_ACAL_DIS 0x00000000
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#define AM_REG_CLKGEN_OCTRL_ACAL_1024SEC 0x00000200
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#define AM_REG_CLKGEN_OCTRL_ACAL_512SEC 0x00000300
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#define AM_REG_CLKGEN_OCTRL_ACAL_XTFREQ 0x00000600
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#define AM_REG_CLKGEN_OCTRL_ACAL_EXTFREQ 0x00000700
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// Selects the RTC oscillator (1 => LFRC, 0 => XT)
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#define AM_REG_CLKGEN_OCTRL_OSEL_S 7
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#define AM_REG_CLKGEN_OCTRL_OSEL_M 0x00000080
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#define AM_REG_CLKGEN_OCTRL_OSEL(n) (((uint32_t)(n) << 7) & 0x00000080)
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#define AM_REG_CLKGEN_OCTRL_OSEL_RTC_XT 0x00000000
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#define AM_REG_CLKGEN_OCTRL_OSEL_RTC_LFRC 0x00000080
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// Oscillator switch on failure function
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#define AM_REG_CLKGEN_OCTRL_FOS_S 6
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#define AM_REG_CLKGEN_OCTRL_FOS_M 0x00000040
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#define AM_REG_CLKGEN_OCTRL_FOS(n) (((uint32_t)(n) << 6) & 0x00000040)
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#define AM_REG_CLKGEN_OCTRL_FOS_DIS 0x00000000
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#define AM_REG_CLKGEN_OCTRL_FOS_EN 0x00000040
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// Stop the LFRC Oscillator to the RTC
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#define AM_REG_CLKGEN_OCTRL_STOPRC_S 1
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#define AM_REG_CLKGEN_OCTRL_STOPRC_M 0x00000002
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#define AM_REG_CLKGEN_OCTRL_STOPRC(n) (((uint32_t)(n) << 1) & 0x00000002)
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#define AM_REG_CLKGEN_OCTRL_STOPRC_EN 0x00000000
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#define AM_REG_CLKGEN_OCTRL_STOPRC_STOP 0x00000002
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// Stop the XT Oscillator to the RTC
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#define AM_REG_CLKGEN_OCTRL_STOPXT_S 0
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#define AM_REG_CLKGEN_OCTRL_STOPXT_M 0x00000001
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#define AM_REG_CLKGEN_OCTRL_STOPXT(n) (((uint32_t)(n) << 0) & 0x00000001)
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#define AM_REG_CLKGEN_OCTRL_STOPXT_EN 0x00000000
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#define AM_REG_CLKGEN_OCTRL_STOPXT_STOP 0x00000001
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//*****************************************************************************
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//
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// CLKGEN_CLKOUT - CLKOUT Frequency Select
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//
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//*****************************************************************************
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// Enable the CLKOUT signal
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#define AM_REG_CLKGEN_CLKOUT_CKEN_S 7
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#define AM_REG_CLKGEN_CLKOUT_CKEN_M 0x00000080
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#define AM_REG_CLKGEN_CLKOUT_CKEN(n) (((uint32_t)(n) << 7) & 0x00000080)
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#define AM_REG_CLKGEN_CLKOUT_CKEN_DIS 0x00000000
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#define AM_REG_CLKGEN_CLKOUT_CKEN_EN 0x00000080
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// CLKOUT signal select. Note that HIGH_DRIVE should be selected if any high
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// frequencies (such as from HFRC) are selected for CLKOUT.
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_S 0
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_M 0x0000003F
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#define AM_REG_CLKGEN_CLKOUT_CKSEL(n) (((uint32_t)(n) << 0) & 0x0000003F)
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC 0x00000000
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2 0x00000001
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV4 0x00000002
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8 0x00000003
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV16 0x00000004
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV32 0x00000005
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_RTC_1Hz 0x00000010
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2M 0x00000016
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT 0x00000017
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_CG_100Hz 0x00000018
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC 0x00000019
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 0x0000001A
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 0x0000001B
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16 0x0000001C
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 0x0000001D
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 0x0000001E
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 0x0000001F
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV512 0x00000020
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_FLASH_CLK 0x00000022
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 0x00000023
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 0x00000024
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 0x00000025
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K 0x00000026
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV256 0x00000027
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8K 0x00000028
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV64K 0x00000029
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 0x0000002A
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 0x0000002B
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz 0x0000002C
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K 0x0000002D
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M 0x0000002E
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K 0x0000002F
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M 0x00000030
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M 0x00000031
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE 0x00000032
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 0x00000033
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE 0x00000035
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 0x00000036
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 0x00000037
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#define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE 0x00000039
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//*****************************************************************************
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//
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// CLKGEN_CCTRL - HFRC Clock Control
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//
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//*****************************************************************************
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// Core Clock divisor
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#define AM_REG_CLKGEN_CCTRL_CORESEL_S 0
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#define AM_REG_CLKGEN_CCTRL_CORESEL_M 0x00000001
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#define AM_REG_CLKGEN_CCTRL_CORESEL(n) (((uint32_t)(n) << 0) & 0x00000001)
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#define AM_REG_CLKGEN_CCTRL_CORESEL_HFRC 0x00000000
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#define AM_REG_CLKGEN_CCTRL_CORESEL_HFRC_DIV2 0x00000001
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//*****************************************************************************
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//
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// CLKGEN_STATUS - Clock Generator Status
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//
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//*****************************************************************************
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// XT Oscillator is enabled but not oscillating
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#define AM_REG_CLKGEN_STATUS_OSCF_S 1
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#define AM_REG_CLKGEN_STATUS_OSCF_M 0x00000002
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#define AM_REG_CLKGEN_STATUS_OSCF(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Current RTC oscillator (1 => LFRC, 0 => XT)
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#define AM_REG_CLKGEN_STATUS_OMODE_S 0
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#define AM_REG_CLKGEN_STATUS_OMODE_M 0x00000001
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#define AM_REG_CLKGEN_STATUS_OMODE(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// CLKGEN_HFADJ - HFRC Adjustment
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//
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//*****************************************************************************
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// Gain control for HFRC adjustment
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#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_S 21
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#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_M 0x00E00000
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#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN(n) (((uint32_t)(n) << 21) & 0x00E00000)
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#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1 0x00000000
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#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2 0x00200000
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#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_4 0x00400000
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#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_8 0x00600000
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#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_16 0x00800000
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#define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_32 0x00A00000
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// XT warmup period for HFRC adjustment
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#define AM_REG_CLKGEN_HFADJ_HFWARMUP_S 20
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#define AM_REG_CLKGEN_HFADJ_HFWARMUP_M 0x00100000
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#define AM_REG_CLKGEN_HFADJ_HFWARMUP(n) (((uint32_t)(n) << 20) & 0x00100000)
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#define AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC 0x00000000
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#define AM_REG_CLKGEN_HFADJ_HFWARMUP_2SEC 0x00100000
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// Target HFRC adjustment value.
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#define AM_REG_CLKGEN_HFADJ_HFXTADJ_S 8
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#define AM_REG_CLKGEN_HFADJ_HFXTADJ_M 0x000FFF00
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#define AM_REG_CLKGEN_HFADJ_HFXTADJ(n) (((uint32_t)(n) << 8) & 0x000FFF00)
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// Repeat period for HFRC adjustment
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#define AM_REG_CLKGEN_HFADJ_HFADJCK_S 1
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#define AM_REG_CLKGEN_HFADJ_HFADJCK_M 0x0000000E
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#define AM_REG_CLKGEN_HFADJ_HFADJCK(n) (((uint32_t)(n) << 1) & 0x0000000E)
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#define AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC 0x00000000
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#define AM_REG_CLKGEN_HFADJ_HFADJCK_16SEC 0x00000002
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#define AM_REG_CLKGEN_HFADJ_HFADJCK_32SEC 0x00000004
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#define AM_REG_CLKGEN_HFADJ_HFADJCK_64SEC 0x00000006
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#define AM_REG_CLKGEN_HFADJ_HFADJCK_128SEC 0x00000008
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#define AM_REG_CLKGEN_HFADJ_HFADJCK_256SEC 0x0000000A
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#define AM_REG_CLKGEN_HFADJ_HFADJCK_512SEC 0x0000000C
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#define AM_REG_CLKGEN_HFADJ_HFADJCK_1024SEC 0x0000000E
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// HFRC adjustment control
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#define AM_REG_CLKGEN_HFADJ_HFADJEN_S 0
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#define AM_REG_CLKGEN_HFADJ_HFADJEN_M 0x00000001
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#define AM_REG_CLKGEN_HFADJ_HFADJEN(n) (((uint32_t)(n) << 0) & 0x00000001)
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#define AM_REG_CLKGEN_HFADJ_HFADJEN_DIS 0x00000000
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#define AM_REG_CLKGEN_HFADJ_HFADJEN_EN 0x00000001
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//*****************************************************************************
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//
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// CLKGEN_CLOCKEN - Clock Enable Status
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//
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//*****************************************************************************
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// Clock enable status
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_S 0
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_M 0xFFFFFFFF
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_ADC_CLKEN 0x00000001
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER_CLKEN 0x00000002
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER0A_CLKEN 0x00000004
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER0B_CLKEN 0x00000008
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER1A_CLKEN 0x00000010
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER1B_CLKEN 0x00000020
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER2A_CLKEN 0x00000040
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER2B_CLKEN 0x00000080
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER3A_CLKEN 0x00000100
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER3B_CLKEN 0x00000200
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR0_CLKEN 0x00000400
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR1_CLKEN 0x00000800
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR2_CLKEN 0x00001000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR3_CLKEN 0x00002000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR4_CLKEN 0x00004000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR5_CLKEN 0x00008000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC0_CLKEN 0x00010000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC1_CLKEN 0x00020000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC2_CLKEN 0x00040000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC3_CLKEN 0x00080000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC4_CLKEN 0x00100000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC5_CLKEN 0x00200000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOSLAVE_CLKEN 0x00400000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_PDM_CLKEN 0x00800000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_PDMIFC_CLKEN 0x01000000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_RSTGEN_CLKEN 0x02000000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_SRAM_WIPE_CLKEN 0x04000000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_STIMER_CLKEN 0x08000000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_STIMER_CNT_CLKEN 0x10000000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_TPIU_CLKEN 0x20000000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_UART0_HCLK_CLKEN 0x40000000
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#define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_UART0HF_CLKEN 0x80000000
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//*****************************************************************************
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//
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// CLKGEN_CLOCKEN2 - Clock Enable Status
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//
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//*****************************************************************************
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// Clock enable status 2
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#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_S 0
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#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_M 0xFFFFFFFF
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#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_UART1_HCLK_CLKEN 0x00000001
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#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_UART1HF_CLKEN 0x00000002
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#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_WDT_CLKEN 0x00000004
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#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_XT_32KHz_EN 0x40000000
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#define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_FRCHFRC 0x80000000
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//*****************************************************************************
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//
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// CLKGEN_CLOCKEN3 - Clock Enable Status
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//
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//*****************************************************************************
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// Clock enable status 3
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_S 0
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_M 0xFFFFFFFF
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_xtal_en 0x01000000
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_hfrc_en 0x02000000
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFADJEN 0x04000000
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_en_out 0x08000000
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_RTC_SOURCE 0x10000000
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_XTAL_EN 0x20000000
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_EN 0x40000000
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#define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_FLASHCLK_EN 0x80000000
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//*****************************************************************************
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//
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// CLKGEN_UARTEN - UART Enable
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//
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//*****************************************************************************
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// UART1 system clock control
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#define AM_REG_CLKGEN_UARTEN_UART1EN_S 8
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#define AM_REG_CLKGEN_UARTEN_UART1EN_M 0x00000300
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#define AM_REG_CLKGEN_UARTEN_UART1EN(n) (((uint32_t)(n) << 8) & 0x00000300)
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#define AM_REG_CLKGEN_UARTEN_UART1EN_DIS 0x00000000
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#define AM_REG_CLKGEN_UARTEN_UART1EN_EN 0x00000100
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#define AM_REG_CLKGEN_UARTEN_UART1EN_REDUCE_FREQ 0x00000200
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#define AM_REG_CLKGEN_UARTEN_UART1EN_EN_POWER_SAV 0x00000300
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// UART0 system clock control
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#define AM_REG_CLKGEN_UARTEN_UART0EN_S 0
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#define AM_REG_CLKGEN_UARTEN_UART0EN_M 0x00000003
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#define AM_REG_CLKGEN_UARTEN_UART0EN(n) (((uint32_t)(n) << 0) & 0x00000003)
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#define AM_REG_CLKGEN_UARTEN_UART0EN_DIS 0x00000000
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#define AM_REG_CLKGEN_UARTEN_UART0EN_EN 0x00000001
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#define AM_REG_CLKGEN_UARTEN_UART0EN_REDUCE_FREQ 0x00000002
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#define AM_REG_CLKGEN_UARTEN_UART0EN_EN_POWER_SAV 0x00000003
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#endif // AM_REG_CLKGEN_H
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