266 lines
6.8 KiB
C
266 lines
6.8 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*
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*/
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#include "drv_uart.h"
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#include "fsl_uart.h"
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static struct rt_serial_device _k64_serial; //abstracted serial for RTT
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struct k64_serial_device
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{
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/* UART base address */
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UART_Type *baseAddress;
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/* UART IRQ Number */
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int irq_num;
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/* device config */
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struct serial_configure config;
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};
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//hardware abstract device
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static struct k64_serial_device _k64_node =
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{
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(UART_Type *)UART0,
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UART0_RX_TX_IRQn,
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};
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static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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unsigned int reg_C1 = 0,reg_C3 = 0,reg_C4 = 0,reg_BDH = 0,reg_BDL = 0,reg_S2 = 0,reg_BRFA=0;
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unsigned int cal_SBR = 0;
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UART_Type *uart_reg;
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/* ref : drivers\system_MK60F12.c Line 64 ,BusClock = 60MHz
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* calculate baud_rate
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*/
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uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
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/*
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* set bit order
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*/
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if (cfg->bit_order == BIT_ORDER_LSB)
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reg_S2 &= ~(UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT);
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else if (cfg->bit_order == BIT_ORDER_MSB)
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reg_S2 |= UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT;
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/*
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* set data_bits
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*/
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if (cfg->data_bits == DATA_BITS_8)
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reg_C1 &= ~(UART_C1_M_MASK<<UART_C1_M_SHIFT);
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else if (cfg->data_bits == DATA_BITS_9)
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reg_C1 |= UART_C1_M_MASK<<UART_C1_M_SHIFT;
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/*
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* set parity
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*/
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if (cfg->parity == PARITY_NONE)
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{
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reg_C1 &= ~(UART_C1_PE_MASK);
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}
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else
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{
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/* first ,set parity enable bit */
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reg_C1 |= (UART_C1_PE_MASK);
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/* second ,determine parity odd or even*/
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if (cfg->parity == PARITY_ODD)
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reg_C1 |= UART_C1_PT_MASK;
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if (cfg->parity == PARITY_EVEN)
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reg_C1 &= ~(UART_C1_PT_MASK);
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}
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/*
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* set NZR mode
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* not tested
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*/
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if (cfg->invert != NRZ_NORMAL)
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{
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/* not in normal mode ,set inverted polarity */
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reg_C3 |= UART_C3_TXINV_MASK;
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}
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switch ((unsigned int)uart_reg)
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{
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/*
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* if you're using other board
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* set clock and pin map for UARTx
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*/
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case UART0_BASE:
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/* calc SBR */
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cal_SBR = SystemCoreClock / (16 * cfg->baud_rate);
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/* check to see if sbr is out of range of register bits */
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if ((cal_SBR > 0x1FFF) || (cal_SBR < 1))
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{
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/* unsupported baud rate for given source clock input*/
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return -RT_ERROR;
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}
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/* calc baud_rate */
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reg_BDH = (cal_SBR & 0x1FFF) >> 8 & 0x00FF;
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reg_BDL = cal_SBR & 0x00FF;
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/* fractional divider */
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reg_BRFA = ((SystemCoreClock * 32) / (cfg->baud_rate * 16)) - (cal_SBR * 32);
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reg_C4 = (unsigned char)(reg_BRFA & 0x001F);
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SIM->SOPT5 &= ~ SIM_SOPT5_UART0RXSRC(0);
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SIM->SOPT5 |= SIM_SOPT5_UART0RXSRC(0);
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SIM->SOPT5 &= ~ SIM_SOPT5_UART0TXSRC(0);
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SIM->SOPT5 |= SIM_SOPT5_UART0TXSRC(0);
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// set UART0 clock
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// Enable UART gate clocking
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// Enable PORTE gate clocking
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CLOCK_EnableClock(kCLOCK_Uart0);
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CLOCK_EnableClock(kCLOCK_PortB);
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// set UART0 pin
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PORTB->PCR[16] &= ~(3UL << 8);
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PORTB->PCR[16] |= (3UL << 8); // Pin mux configured as ALT3
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PORTB->PCR[17] &= ~(3UL << 8);
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PORTB->PCR[17] |= (3UL << 8); // Pin mux configured as ALT3
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break;
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default:
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return -RT_ERROR;
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}
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uart_reg->BDH = reg_BDH;
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uart_reg->BDL = reg_BDL;
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uart_reg->C1 = reg_C1;
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uart_reg->C4 = reg_C4;
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uart_reg->S2 = reg_S2;
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uart_reg->S2 = 0;
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uart_reg->C3 = 0;
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uart_reg->RWFIFO = UART_RWFIFO_RXWATER(1);
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uart_reg->TWFIFO = UART_TWFIFO_TXWATER(0);
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uart_reg->C2 = UART_C2_RE_MASK | //Receiver enable
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UART_C2_TE_MASK; //Transmitter enable
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return RT_EOK;
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}
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static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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UART_Type *uart_reg;
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int uart_irq_num = 0;
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uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
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uart_irq_num = ((struct k64_serial_device *)serial->parent.user_data)->irq_num;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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uart_reg->C2 &= ~UART_C2_RIE_MASK;
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//disable NVIC
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NVIC->ICER[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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uart_reg->C2 |= UART_C2_RIE_MASK;
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//enable NVIC,we are sure uart's NVIC vector is in NVICICPR1
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NVIC->ICPR[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
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NVIC->ISER[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
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break;
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case RT_DEVICE_CTRL_SUSPEND:
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/* suspend device */
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uart_reg->C2 &= ~(UART_C2_RE_MASK | //Receiver enable
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UART_C2_TE_MASK); //Transmitter enable
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break;
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case RT_DEVICE_CTRL_RESUME:
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/* resume device */
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uart_reg->C2 = UART_C2_RE_MASK | //Receiver enable
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UART_C2_TE_MASK; //Transmitter enable
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break;
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}
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return RT_EOK;
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}
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static int _putc(struct rt_serial_device *serial, char c)
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{
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UART_Type *uart_reg;
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uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
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while (!(uart_reg->S1 & UART_S1_TDRE_MASK));
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uart_reg->D = (c & 0xFF);
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return 1;
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}
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static int _getc(struct rt_serial_device *serial)
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{
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UART_Type *uart_reg;
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uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
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if (uart_reg->S1 & UART_S1_RDRF_MASK)
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return (uart_reg->D);
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else
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return -1;
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}
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static const struct rt_uart_ops _k64_ops =
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{
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_configure,
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_control,
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_putc,
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_getc,
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};
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void UART0_RX_TX_IRQHandler(void)
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{
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rt_interrupt_enter();
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rt_hw_serial_isr((struct rt_serial_device*)&_k64_serial, RT_SERIAL_EVENT_RX_IND);
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rt_interrupt_leave();
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}
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void rt_hw_uart_init(void)
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{
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struct serial_configure config;
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/* fake configuration */
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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config.bufsz = RT_SERIAL_RB_BUFSZ;
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_k64_serial.ops = &_k64_ops;
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_k64_serial.config = config;
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rt_hw_serial_register(&_k64_serial, "uart0",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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(void*)&_k64_node);
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}
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void rt_hw_console_output(const char *str)
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{
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while(*str != '\0')
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{
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if (*str == '\n')
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_putc(&_k64_serial,'\r');
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_putc(&_k64_serial,*str);
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str++;
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}
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}
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