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2168ed8e7d
PCI/PCIe have better performance and more devices support, such as NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by IOMMU that the virtualiztion and userspace driver will more safety. PCI/PCIe device could hot plugging, no design modifications SoC required, PCI/PCIe on Embedded SoC is popular now. We make a simple framework to support them. Feature Lists: 1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC. 2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC. 3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework. 4.Endpoint: a simple EP framework for PCI FPGA or NTB function. 5.OFW: we only support work on OFW SoC, ACPI support in the future maybe. Host controller: 1. Common PCI host controller on ECAM. 2. Generic PCI host controller on ECAM. Signed-off-by: GuEe-GUI <2991707448@qq.com>
47 lines
1.1 KiB
C
47 lines
1.1 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-24 GuEe-GUI first version
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*/
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#include <drivers/pci.h>
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void rt_pci_msi_init(struct rt_pci_device *pdev)
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{
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if (pdev && (pdev->msi_cap = rt_pci_find_capability(pdev, PCIY_MSI)))
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{
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rt_uint16_t ctrl;
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rt_pci_read_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, &ctrl);
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if (ctrl & PCIM_MSICTRL_MSI_ENABLE)
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{
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rt_pci_write_config_u16(pdev, pdev->msi_cap + PCIR_MSI_CTRL, ctrl & ~PCIM_MSICTRL_MSI_ENABLE);
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}
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if (!(ctrl & PCIM_MSICTRL_64BIT))
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{
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pdev->no_64bit_msi = RT_TRUE;
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}
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}
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}
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void rt_pci_msix_init(struct rt_pci_device *pdev)
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{
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if (pdev && (pdev->msix_cap = rt_pci_find_capability(pdev, PCIY_MSIX)))
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{
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rt_uint16_t ctrl;
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rt_pci_read_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, &ctrl);
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if (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE)
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{
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rt_pci_write_config_u16(pdev, pdev->msix_cap + PCIR_MSIX_CTRL, ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE);
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}
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}
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}
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