mirror of
https://github.com/RT-Thread/rt-thread.git
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fe2b124345
Support for ARM64 ASID to enhance virtual memory management efficiency by reducing the need for TLB flushes during address space switches. These changes improve performance especially for multi-process systems. Changes: - Added `ARCH_USING_ASID` configuration in `libcpu/aarch64/Kconfig`. - Defined ASID-related constants in `mmu.h`. - Updated `TLBI_ARG` macro to include ASID manipulation. - Implemented ASID allocation mechanism with spinlock synchronization. - Enhanced TLB invalidation to support ASID-specific operations. - Modified `rt_hw_aspace_switch` to use ASIDs when switching address spaces. - Adjusted debug logging and function documentation to reflect ASID usage. - Refactored AArch64 MMU and TLB handling for ASID integration. Signed-off-by: Shell <smokewood@qq.com>
219 lines
6.8 KiB
C
219 lines
6.8 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-05-12 RT-Thread the first version
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* 2023-08-15 Shell Support more mapping attribution
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*/
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#ifndef __MMU_H_
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#define __MMU_H_
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#ifndef __ASSEMBLY__
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#include <rtthread.h>
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#include <mm_aspace.h>
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/* normal memory wra mapping type */
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#define NORMAL_MEM 0
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/* normal nocache memory mapping type */
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#define NORMAL_NOCACHE_MEM 1
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/* device mapping type */
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#define DEVICE_MEM 2
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struct mem_desc
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{
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unsigned long vaddr_start;
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unsigned long vaddr_end;
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unsigned long paddr_start;
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unsigned long attr;
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struct rt_varea varea;
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};
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#endif /* !__ASSEMBLY__ */
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#define RT_HW_MMU_PROT_READ 1
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#define RT_HW_MMU_PROT_WRITE 2
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#define RT_HW_MMU_PROT_EXECUTE 4
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#define RT_HW_MMU_PROT_KERNEL 8
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#define RT_HW_MMU_PROT_USER 16
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#define RT_HW_MMU_PROT_CACHE 32
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#define MMU_ASID_SHIFT 48
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#define MMU_NG_SHIFT 11 /* not global bit */
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#define MMU_AF_SHIFT 10
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#define MMU_SHARED_SHIFT 8
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#define MMU_AP_SHIFT 6
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#define MMU_MA_SHIFT 2
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#define MMU_AP_MASK (0x3 << MMU_AP_SHIFT)
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/* we dont support feat detecting for now, so 8-bit is used to fallback */
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#define MMU_SUPPORTED_ASID_BITS 8
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#define MMU_AP_KAUN 0UL /* kernel r/w, user none */
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#define MMU_AP_KAUA 1UL /* kernel r/w, user r/w */
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#define MMU_AP_KRUN 2UL /* kernel r, user none */
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#define MMU_AP_KRUR 3UL /* kernel r, user r */
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#define MMU_ATTR_AF (1ul << MMU_AF_SHIFT) /* the access flag */
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#define MMU_ATTR_DBM (1ul << 51) /* the dirty bit modifier */
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#define MMU_MAP_CUSTOM(ap, mtype, nglobal) \
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((0x1UL << MMU_AF_SHIFT) | (0x2UL << MMU_SHARED_SHIFT) | \
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((ap) << MMU_AP_SHIFT) | ((mtype) << MMU_MA_SHIFT)) | \
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((rt_ubase_t)(nglobal) << MMU_NG_SHIFT)
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#define MMU_MAP_K_ROCB MMU_MAP_CUSTOM(MMU_AP_KRUN, NORMAL_MEM, 0)
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#define MMU_MAP_K_RO MMU_MAP_CUSTOM(MMU_AP_KRUN, NORMAL_NOCACHE_MEM, 0)
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#define MMU_MAP_K_RWCB MMU_MAP_CUSTOM(MMU_AP_KAUN, NORMAL_MEM, 0)
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#define MMU_MAP_K_RW MMU_MAP_CUSTOM(MMU_AP_KAUN, NORMAL_NOCACHE_MEM, 0)
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#define MMU_MAP_K_DEVICE MMU_MAP_CUSTOM(MMU_AP_KAUN, DEVICE_MEM, 0)
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#define MMU_MAP_U_ROCB MMU_MAP_CUSTOM(MMU_AP_KRUR, NORMAL_MEM, 1)
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#define MMU_MAP_U_RO MMU_MAP_CUSTOM(MMU_AP_KRUR, NORMAL_NOCACHE_MEM, 1)
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#define MMU_MAP_U_RWCB MMU_MAP_CUSTOM(MMU_AP_KAUA, NORMAL_MEM, 1)
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#define MMU_MAP_U_RW MMU_MAP_CUSTOM(MMU_AP_KAUA, NORMAL_NOCACHE_MEM, 1)
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#define MMU_MAP_U_DEVICE MMU_MAP_CUSTOM(MMU_AP_KAUA, DEVICE_MEM, 1)
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#define MMU_MAP_TRACE(attr) ((attr) & ~(MMU_ATTR_AF | MMU_ATTR_DBM))
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#define ARCH_SECTION_SHIFT 21
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#define ARCH_SECTION_SIZE (1 << ARCH_SECTION_SHIFT)
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#define ARCH_SECTION_MASK (ARCH_SECTION_SIZE - 1)
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#define ARCH_PAGE_SHIFT 12
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#define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT)
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#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
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#define ARCH_PAGE_TBL_SHIFT 12
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#define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT)
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#define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1)
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#define ARCH_VADDR_WIDTH 48
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#define ARCH_ADDRESS_WIDTH_BITS 64
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#define MMU_MAP_ERROR_VANOTALIGN -1
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#define MMU_MAP_ERROR_PANOTALIGN -2
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#define MMU_MAP_ERROR_NOPAGE -3
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#define MMU_MAP_ERROR_CONFLICT -4
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#define ARCH_MAP_FAILED ((void *)0x1ffffffffffff)
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#define ARCH_EARLY_MAP_SIZE (0x40000000)
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/* this is big enough for even 16TB first-time mapping */
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#define ARCH_PAGE_INIT_THRESHOLD (0x10000000)
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#ifndef __ASSEMBLY__
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struct rt_aspace;
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void rt_hw_mmu_ktbl_set(unsigned long tbl);
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void rt_hw_mem_setup_early(unsigned long *tbl0, unsigned long *tbl1,
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unsigned long size, unsigned long pv_off);
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void rt_hw_mmu_setup(struct rt_aspace *aspace, struct mem_desc *mdesc,
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int desc_nr);
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int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, size_t size, size_t *vtable, size_t pv_off);
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void *rt_hw_mmu_map(struct rt_aspace *aspace, void *v_addr, void *p_addr,
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size_t size, size_t attr);
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void rt_hw_mmu_unmap(struct rt_aspace *aspace, void *v_addr, size_t size);
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void rt_hw_aspace_switch(struct rt_aspace *aspace);
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void *rt_hw_mmu_v2p(struct rt_aspace *aspace, void *vaddr);
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void rt_hw_mmu_kernel_map_init(struct rt_aspace *aspace, rt_size_t vaddr_start,
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rt_size_t size);
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void *rt_hw_mmu_pgtbl_create(void);
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void rt_hw_mmu_pgtbl_delete(void *pgtbl);
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void *rt_hw_mmu_tbl_get(void);
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static inline void *rt_hw_mmu_kernel_v2p(void *v_addr)
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{
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rt_ubase_t par;
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void *paddr;
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__asm__ volatile("at s1e1w, %0"::"r"(v_addr):"memory");
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__asm__ volatile("mrs %0, par_el1":"=r"(par)::"memory");
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if (par & 0x1)
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{
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paddr = ARCH_MAP_FAILED;
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}
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else
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{
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#define MMU_ADDRESS_MASK 0x0000fffffffff000UL
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par &= MMU_ADDRESS_MASK;
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par |= (rt_ubase_t)v_addr & ARCH_PAGE_MASK;
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paddr = (void *)par;
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}
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return paddr;
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}
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/**
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* @brief Add permission from attribution
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*
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* @param attr architecture specified mmu attribution
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* @param prot protect that will be added
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* @return size_t returned attribution
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*/
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rt_inline size_t rt_hw_mmu_attr_add_perm(size_t attr, rt_base_t prot)
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{
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switch (prot)
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{
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/* remove write permission for user */
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case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
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attr = (attr & ~MMU_AP_MASK) | (MMU_AP_KAUA << MMU_AP_SHIFT);
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break;
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default:
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RT_ASSERT(0);
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}
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return attr;
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}
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/**
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* @brief Remove permission from attribution
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*
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* @param attr architecture specified mmu attribution
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* @param prot protect that will be removed
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* @return size_t returned attribution
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*/
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rt_inline size_t rt_hw_mmu_attr_rm_perm(size_t attr, rt_base_t prot)
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{
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switch (prot)
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{
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/* remove write permission for user */
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case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
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if (attr & 0x40)
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attr |= 0x80;
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break;
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default:
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RT_ASSERT(0);
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}
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return attr;
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}
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/**
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* @brief Test permission from attribution
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*
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* @param attr architecture specified mmu attribution
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* @param prot protect that will be test
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* @return rt_bool_t RT_TRUE if the prot is allowed, otherwise RT_FALSE
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*/
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rt_inline rt_bool_t rt_hw_mmu_attr_test_perm(size_t attr, rt_base_t prot)
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{
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rt_bool_t rc;
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switch (prot)
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{
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/* test write permission for user */
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case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
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if ((attr & MMU_AP_MASK) == (MMU_AP_KAUA << MMU_AP_SHIFT))
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rc = RT_TRUE;
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else
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rc = RT_FALSE;
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break;
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default:
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RT_ASSERT(0);
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}
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return rc;
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}
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int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
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enum rt_mmu_cntl cmd);
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#endif /* !__ASSEMBLY__ */
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#endif
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