367 lines
8.1 KiB
C
367 lines
8.1 KiB
C
/*
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* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file csi_reg.h
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* @brief CSI Header File for reg.
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#ifndef _CSI_REG_H_
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#define _CSI_REG_H_
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#include<csi_gcc.h>
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/**
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\brief Enable IRQ Interrupts
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\details Enables IRQ interrupts by setting the IE-bit in the PSR.
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Can only be executed in Privileged modes.
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*/
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__ALWAYS_INLINE void __enable_irq(void)
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{
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__ASM volatile("psrset ie");
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}
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/**
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\brief Disable IRQ Interrupts
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\details Disables IRQ interrupts by clearing the IE-bit in the PSR.
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Can only be executed in Privileged modes.
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*/
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__ALWAYS_INLINE void __disable_irq(void)
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{
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__ASM volatile("psrclr ie");
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}
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/**
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\brief Get PSR
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\details Returns the content of the PSR Register.
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\return PSR Register value
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*/
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__ALWAYS_INLINE uint32_t __get_PSR(void)
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{
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uint32_t result;
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__ASM volatile("mfcr %0, psr" : "=r"(result));
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return (result);
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}
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/**
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\brief Set PSR
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\details Writes the given value to the PSR Register.
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\param [in] psr PSR Register value to set
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*/
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__ALWAYS_INLINE void __set_PSR(uint32_t psr)
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{
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__ASM volatile("mtcr %0, psr" : : "r"(psr));
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}
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/**
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\brief Get SP
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\details Returns the content of the SP Register.
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\return SP Register value
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*/
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__ALWAYS_INLINE uint32_t __get_SP(void)
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{
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uint32_t result;
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__ASM volatile("mov %0, sp" : "=r"(result));
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return (result);
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}
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/**
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\brief Set SP
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\details Writes the given value to the SP Register.
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\param [in] sp SP Register value to set
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*/
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__ALWAYS_INLINE void __set_SP(uint32_t sp)
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{
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__ASM volatile("mov sp, %0" : : "r"(sp): "sp");
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}
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/**
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\brief Get VBR Register
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\details Returns the content of the VBR Register.
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\return VBR Register value
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*/
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__ALWAYS_INLINE uint32_t __get_VBR(void)
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{
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uint32_t result;
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__ASM volatile("mfcr %0, vbr" : "=r"(result));
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return (result);
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}
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/**
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\brief Set VBR
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\details Writes the given value to the VBR Register.
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\param [in] vbr VBR Register value to set
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*/
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__ALWAYS_INLINE void __set_VBR(uint32_t vbr)
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{
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__ASM volatile("mtcr %0, vbr" : : "r"(vbr));
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}
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/**
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\brief Get EPC Register
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\details Returns the content of the EPC Register.
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\return EPC Register value
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*/
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__ALWAYS_INLINE uint32_t __get_EPC(void)
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{
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uint32_t result;
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__ASM volatile("mfcr %0, epc" : "=r"(result));
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return (result);
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}
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/**
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\brief Set EPC
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\details Writes the given value to the EPC Register.
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\param [in] epc EPC Register value to set
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*/
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__ALWAYS_INLINE void __set_EPC(uint32_t epc)
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{
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__ASM volatile("mtcr %0, epc" : : "r"(epc));
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}
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/**
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\brief Get EPSR
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\details Returns the content of the EPSR Register.
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\return EPSR Register value
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*/
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__ALWAYS_INLINE uint32_t __get_EPSR(void)
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{
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uint32_t result;
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__ASM volatile("mfcr %0, epsr" : "=r"(result));
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return (result);
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}
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/**
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\brief Set EPSR
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\details Writes the given value to the EPSR Register.
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\param [in] epsr EPSR Register value to set
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*/
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__ALWAYS_INLINE void __set_EPSR(uint32_t epsr)
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{
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__ASM volatile("mtcr %0, epsr" : : "r"(epsr));
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}
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/**
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\brief Get CPUID Register
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\details Returns the content of the CPUID Register.
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\return CPUID Register value
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*/
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__ALWAYS_INLINE uint32_t __get_CPUID(void)
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{
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uint32_t result;
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__ASM volatile("mfcr %0, cr<13, 0>" : "=r"(result));
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return (result);
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}
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#if (__SOFTRESET_PRESENT == 1U)
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/**
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\brief Set SRCR
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\details Assigns the given value to the SRCR.
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\param [in] srcr SRCR value to set
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*/
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__ALWAYS_INLINE void __set_SRCR(uint32_t srcr)
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{
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__ASM volatile("mtcr %0, cr<31, 0>\n" : : "r"(srcr));
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}
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#endif /* __SOFTRESET_PRESENT == 1U */
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#if (__MGU_PRESENT == 1U)
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/**
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\brief Get CCR
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\details Returns the current value of the CCR.
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\return CCR Register value
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*/
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__ALWAYS_INLINE uint32_t __get_CCR(void)
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{
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register uint32_t result;
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__ASM volatile("mfcr %0, cr<18, 0>\n" : "=r"(result));
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return (result);
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}
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/**
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\brief Set CCR
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\details Assigns the given value to the CCR.
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\param [in] ccr CCR value to set
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*/
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__ALWAYS_INLINE void __set_CCR(uint32_t ccr)
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{
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__ASM volatile("mtcr %0, cr<18, 0>\n" : : "r"(ccr));
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}
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/**
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\brief Get CAPR
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\details Returns the current value of the CAPR.
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\return CAPR Register value
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*/
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__ALWAYS_INLINE uint32_t __get_CAPR(void)
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{
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register uint32_t result;
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__ASM volatile("mfcr %0, cr<19, 0>\n" : "=r"(result));
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return (result);
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}
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/**
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\brief Set CAPR
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\details Assigns the given value to the CAPR.
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\param [in] capr CAPR value to set
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*/
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__ALWAYS_INLINE void __set_CAPR(uint32_t capr)
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{
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__ASM volatile("mtcr %0, cr<19, 0>\n" : : "r"(capr));
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}
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/**
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\brief Set PACR
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\details Assigns the given value to the PACR.
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\param [in] pacr PACR value to set
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*/
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__ALWAYS_INLINE void __set_PACR(uint32_t pacr)
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{
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__ASM volatile("mtcr %0, cr<20, 0>\n" : : "r"(pacr));
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}
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/**
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\brief Get PACR
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\details Returns the current value of PACR.
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\return PACR value
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*/
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__ALWAYS_INLINE uint32_t __get_PACR(void)
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{
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uint32_t result;
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__ASM volatile("mfcr %0, cr<20, 0>" : "=r"(result));
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return (result);
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}
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/**
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\brief Set PRSR
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\details Assigns the given value to the PRSR.
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\param [in] prsr PRSR value to set
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*/
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__ALWAYS_INLINE void __set_PRSR(uint32_t prsr)
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{
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__ASM volatile("mtcr %0, cr<21, 0>\n" : : "r"(prsr));
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}
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/**
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\brief Get PRSR
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\details Returns the current value of PRSR.
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\return PRSR value
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*/
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__ALWAYS_INLINE uint32_t __get_PRSR(void)
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{
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uint32_t result;
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__ASM volatile("mfcr %0, cr<21, 0>" : "=r"(result));
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return (result);
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}
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#endif /* __MGU_PRESENT == 1U */
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/**
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\brief Get user sp
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\details Returns the current value of user r14.
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\return UR14 value
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*/
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__ALWAYS_INLINE uint32_t __get_UR14(void)
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{
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uint32_t result;
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__ASM volatile("mfcr %0, cr<14, 1>" : "=r"(result));
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return (result);
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}
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/**
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\brief Enable interrupts and exceptions
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\details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR.
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Can only be executed in Privileged modes.
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*/
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__ALWAYS_INLINE void __enable_excp_irq(void)
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{
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__ASM volatile("psrset ee, ie");
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}
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/**
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\brief Disable interrupts and exceptions
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\details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR.
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Can only be executed in Privileged modes.
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*/
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__ALWAYS_INLINE void __disable_excp_irq(void)
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{
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__ASM volatile("psrclr ee, ie");
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}
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#if (__GSR_GCR_PRESENT == 1U)
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/**
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\brief Get GSR
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\details Returns the content of the GSR Register.
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\return GSR Register value
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*/
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__ALWAYS_INLINE uint32_t __get_GSR(void)
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{
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uint32_t result;
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__ASM volatile("mfcr %0, cr<12, 0>" : "=r"(result));
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return (result);
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}
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/**
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\brief Get GCR
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\details Returns the content of the GCR Register.
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\return GCR Register value
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*/
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__ALWAYS_INLINE uint32_t __get_GCR(void)
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{
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uint32_t result;
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__ASM volatile("mfcr %0, cr<11, 0>" : "=r"(result));
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return (result);
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}
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/**
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\brief Set GCR
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\details Writes the given value to the GCR Register.
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\param [in] gcr GCR Register value to set
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*/
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__ALWAYS_INLINE void __set_GCR(uint32_t gcr)
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{
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__ASM volatile("mtcr %0, cr<11, 0>" : : "r"(gcr));
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}
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#endif /* (__GSR_GCR_PRESENT == 1U) */
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#endif /* _CSI_REG_H_ */
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