1534 lines
48 KiB
C
1534 lines
48 KiB
C
//*****************************************************************************
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//
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// lpc.c - Driver for the Low Pin Count (LPC) module.
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//
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// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup lpc_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_lpc.h"
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#include "inc/hw_sysctl.h"
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#include "inc/hw_types.h"
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#include "driverlib/debug.h"
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#include "driverlib/interrupt.h"
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#include "driverlib/lpc.h"
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//*****************************************************************************
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//
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//! \internal
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//! Checks an LPC Channel.
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//!
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//! \param ulChannel is the LPC channel identifier.
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//!
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//! This function determines if a channel identifier is valid. This function
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//! does not check for Channel 7 (COMx).
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//!
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//! \return Returns \b true if the channel identifier is valid and \b false
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//! otherwise.
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//
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//*****************************************************************************
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#ifdef DEBUG
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static tBoolean
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LPCChannelValid(unsigned long ulChannel)
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{
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return((ulChannel == LPC_CHAN_CH0) ||
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(ulChannel == LPC_CHAN_CH1) ||
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(ulChannel == LPC_CHAN_CH2) ||
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(ulChannel == LPC_CHAN_CH3) ||
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(ulChannel == LPC_CHAN_CH4) ||
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(ulChannel == LPC_CHAN_CH5) ||
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(ulChannel == LPC_CHAN_CH6) ||
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(ulChannel == LPC_CHAN_CH7));
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}
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#endif // #ifdef DEBUG
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//*****************************************************************************
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//
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//! Sets the configuration of the LPC module.
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//!
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//! \param ulBase is the base address of the LPC module.
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//! \param ulConfig specifies the configuration of the LPC module.
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//!
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//! This function configures the LPC module for basic operation. The
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//! configuration of individual channels is handled in a separate function.
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//!
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//! The \e ulConfig parameter is the logical OR of the following values:
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//! - \b LPC_CFG_WAKE - Force assertion of the LPC0CLKRUN signal when the
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//! LPC bus is powered down (LPC0PD is asserted).
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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LPCConfigSet(unsigned long ulBase, unsigned long ulConfig)
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{
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unsigned long ulTemp;
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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ASSERT((ulConfig & ~(LPC_CFG_WAKE)) == 0);
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//
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// Configure the appropriate LPC Control Register fields.
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//
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ulTemp = HWREG(ulBase + LPC_O_CTL);
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ulTemp &= ~LPC_CTL_WAKE;
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ulTemp |= (ulConfig & LPC_CTL_WAKE);
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HWREG(ulBase + LPC_O_CTL) = ulTemp;
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}
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//*****************************************************************************
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//
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//! Gets the current configuration of the LPC module.
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//!
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//! \param ulBase is the base address of the LPC module.
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//!
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//! This function queries the control register of the LPC module and returns
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//! a bit-mapped value.
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//!
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//! \sa The description of the LPCConfigSet() function provides detailed
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//! information for the bit-mapped configuration values that are returned.
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//!
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//! \return Returns the bit-mapped LPC module configration value.
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//
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//*****************************************************************************
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unsigned long
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LPCConfigGet(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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//
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// Return the configuration value
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//
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return((HWREG(ulBase + LPC_O_CTL) & LPC_CTL_WAKE));
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}
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//*****************************************************************************
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//
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//! Sets the Status Block Address for the LPC peripheral.
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//!
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//! \param ulBase is the base address of the LPC module.
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//! \param ulAddress is the host address to use for the block status.
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//! \param bEnabled indicates whether the block address feature should
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//! be enabled.
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//!
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//! This function sets the LPC block address register and optionally enables
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//! it.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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LPCStatusBlockAddressSet(unsigned long ulBase, unsigned long ulAddress,
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tBoolean bEnabled)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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ASSERT((ulAddress & ~0xFFFFFFFE) == 0);
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//
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// Set (and optionally enable) the Status Block Address
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//
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HWREG(ulBase + LPC_O_STSADDR) = (ulAddress | (bEnabled ? 1 : 0));
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}
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//*****************************************************************************
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//
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//! Gets the Status Block Address for the LPC peripheral.
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//!
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//! \param ulBase is the base address of the LPC module.
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//!
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//! This function returns the LPC block address register. The LSB is used
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//! to indicate whether this feature has been enabled or not.
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//!
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//! \return None.
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//
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//*****************************************************************************
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unsigned
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LPCStatusBlockAddressGet(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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//
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// Return the Status Block Address, including the enable bit.
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//
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return(HWREG(ulBase + LPC_O_STSADDR));
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}
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//*****************************************************************************
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//
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//! Returns the status of the LPC module.
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//!
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//! \param ulBase is the base address of the LPC module.
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//! \param pulCount is a pointer to storage for the channel count.
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//! \param pulPoolSize is a pointer to storage for the register pool size.
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//!
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//! This function reads the value of the LPC Status register, calculates the
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//! number of channels and buffer pool size, and then returns the raw status
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//! value.
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//!
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//! \return Returns the contents of the LPC Status register.
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//
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//*****************************************************************************
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unsigned long
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LPCStatusGet(unsigned long ulBase, unsigned long *pulCount,
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unsigned long *pulPoolSize)
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{
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unsigned long ulStatus;
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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//
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// Get a snapshot of the status register.
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//
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ulStatus = HWREG(ulBase + LPC_O_STS);
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//
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// Extract the channel count from the status, including COMx channel.
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//
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if(pulCount)
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{
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*pulCount = (((ulStatus & LPC_STS_CHCNT_M) >> LPC_STS_CHCNT_S) + 1);
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}
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//
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// Extract/Calculate the register pool size.
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//
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if(pulPoolSize)
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{
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*pulPoolSize = (((ulStatus & LPC_STS_POOLSZ_M) >> 16) * 256);
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}
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//
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// Return the raw status.
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//
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return(ulStatus);
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}
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//*****************************************************************************
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//
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//! Generates a pulse on the SCIn signal.
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//!
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//! \param ulBase is the base address of the LPC module.
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//! \param ulCount is the number used to generate the pulse width value.
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//!
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//! This function generates a pulse on the SCIn interrupt pin. The width of
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//! the pulse is (2 << \e ulCount) LPC Clock Periods, where \e ulCount can take
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//! on the value of 0, 1, 2, or 3. So, the pulse width is 2, 4, 8, or 16 clock
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//! periods.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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LPCSCIAssert(unsigned long ulBase, unsigned long ulCount)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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ASSERT(ulCount <= 3);
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//
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// Wait for any previous pulse to be completed, by checking the SCI bit
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// (which is a self-clearing bit that is used to generate the pulse).
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//
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while(HWREG(ulBase + LPC_O_CTL) & LPC_CTL_SCI)
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{
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}
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//
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// Set the count value first, prior to enabling the pulse.
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//
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HWREG(ulBase + LPC_O_CTL) &= ~LPC_CTL_SCICNT_M;
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HWREG(ulBase + LPC_O_CTL) |= (ulCount << 10);
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//
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// Now, generate the pulse by setting the SCI bit.
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//
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HWREG(ulBase + LPC_O_CTL) |= LPC_CTL_SCI;
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}
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//*****************************************************************************
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//
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//! Configure the LPC IRQ operation.
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//!
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//! \param ulBase is the base address of the LPC module.
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//! \param bIRQPulse is a flag to indicate the manual IRQ bits should be
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//! cleared after they have been sent (in an SIRQ frame).
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//! \param bIRQOnChange is a flag to indicate that an SIRQ frame should be
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//! sent whenever any IRQ bits (manual/auto) change status.
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//!
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//! This function configures the LPC IRQs. If the \e bIRQPulse parameter is
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//! \b true, then manual IRQ values are cleared after they are sent. If the
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//! \e bIRQOnChange parameter is true, then IRQ values (manual and/or
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//! automatic) are sent when a change is detected.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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LPCIRQConfig(unsigned long ulBase, tBoolean bIRQPulse, tBoolean bIRQOnChange)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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//
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// Setup IRQ pulse configuration.
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//
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if(bIRQPulse)
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{
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HWREG(ulBase + LPC_O_IRQCTL) |= LPC_IRQCTL_PULSE;
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}
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else
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{
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HWREG(ulBase + LPC_O_IRQCTL) &= ~LPC_IRQCTL_PULSE;
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}
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//
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// Setup IRQ on-change configuration.
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//
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if(bIRQOnChange)
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{
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HWREG(ulBase + LPC_O_IRQCTL) |= LPC_IRQCTL_ONCHG;
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}
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else
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{
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HWREG(ulBase + LPC_O_IRQCTL) &= ~LPC_IRQCTL_ONCHG;
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}
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}
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//*****************************************************************************
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//
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//! Set the manual LPC IRQ bits.
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//!
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//! \param ulBase specifies the LPC module base address.
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//! \param ulIRQ specifies the IRQ bits that should be set.
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//!
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//! This function sets the IRQ bits that are sent in the SERIRQ frame. The
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//! value in the \e ulIRQ register is OR-ed into the existing manual IRQ
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//! setting. The value for the \e ulIRQ parameter can be any combination of
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//! the following values: \b LPC_IRQ15, \b LPC_IRQ14, \b LPC_IRQ13,
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//! \b LPC_IRQ12, \b LPC_IRQ11, \b LPC_IRQ10, \b LPC_IRQ9, \b LPC_IRQ8,
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//! \b LPC_IRQ7, \b LPC_IRQ6, \b LPC_IRQ5, \b LPC_IRQ4, \b LPC_IRQ3,
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//! \b LPC_IRQ2, \b LPC_IRQ1, or \b LPC_IRQ0.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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LPCIRQSet(unsigned long ulBase, unsigned long ulIRQ)
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{
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unsigned long ulTemp;
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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//
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// Get the current IRQ configuration, mask off the bits that we are to
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// be operating on, set/clear them as appropriate, then rewrite the
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// register.
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//
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ulTemp = HWREG(ulBase + LPC_O_IRQCTL);
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ulTemp |= (ulIRQ & 0xFFFF0000);
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HWREG(ulBase + LPC_O_IRQCTL) = ulTemp;
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}
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//*****************************************************************************
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//
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//! Clear the manual LPC IRQ bits.
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//!
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//! \param ulBase specifies the LPC module base address.
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//! \param ulIRQ specifies the IRQ bits that should be cleared.
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//!
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//! This function clears the IRQ bits that are sent in the SERIRQ frame. The
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//! value in the \e ulIRQ register is OR-ed into the existing manual IRQ
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//! setting. The value for the \e ulIRQ parameter can be any combination of
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//! the following values: \b LPC_IRQ15, \b LPC_IRQ14, \b LPC_IRQ13,
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//! \b LPC_IRQ12, \b LPC_IRQ11, \b LPC_IRQ10, \b LPC_IRQ9, \b LPC_IRQ8,
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//! \b LPC_IRQ7, \b LPC_IRQ6, \b LPC_IRQ5, \b LPC_IRQ4, \b LPC_IRQ3,
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//! \b LPC_IRQ2, \b LPC_IRQ1, or \b LPC_IRQ0.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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LPCIRQClear(unsigned long ulBase, unsigned long ulIRQ)
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{
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unsigned long ulTemp;
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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//
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// Get the current IRQ configuration, mask off the bits that we are to
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// be operating on, set/clear them as appropriate, then rewrite the
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// register.
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//
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ulTemp = HWREG(ulBase + LPC_O_IRQCTL);
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ulTemp &= ~(ulIRQ & 0xFFFF0000);
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HWREG(ulBase + LPC_O_IRQCTL) = ulTemp;
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}
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//*****************************************************************************
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//
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//! Get the configuration and status of the IRQ signals
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//!
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//! \param ulBase specifies the LPC module base address.
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//!
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//! This function returns the LPC module's SERIRQ status. The value returned
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//! is a combination of the following values: \b LPC_IRQ15, \b LPC_IRQ14,
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//! \b LPC_IRQ13, \b LPC_IRQ12, \b LPC_IRQ11, \b LPC_IRQ10, \b LPC_IRQ9,
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//! \b LPC_IRQ8, \b LPC_IRQ7, \b LPC_IRQ6, \b LPC_IRQ5, \b LPC_IRQ4,
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//! \b LPC_IRQ3, \b LPC_IRQ2, \b LPC_IRQ1, \b LPC_IRQ0, \b LPC_IRQ_BUSY, or
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//! \b LPC_IRQ_CONT.
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//!
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//! \return None.
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//
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//*****************************************************************************
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unsigned long
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LPCIRQGet(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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//
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// Simply read the registers and return the values.
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//
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return(HWREG(ulBase + LPC_O_IRQST));
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}
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//*****************************************************************************
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//
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//! Trigger a manual SIRQ frame.
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//!
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//! \param ulBase specifies the LPC module base address.
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//!
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//! This function forces the sending of an SIRQ frame using whatever values are
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//! currently set (auto and/or manual).
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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LPCIRQSend(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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//
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// Set the bit to force the sending of an SIRQ frame.
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//
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HWREG(ulBase + LPC_O_IRQCTL) |= LPC_IRQCTL_SND;
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}
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|
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//*****************************************************************************
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//
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//! Registers an interrupt handler for the LPC module.
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//!
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//! \param ulBase specifies the LPC module base address.
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//! \param pfnHandler is a pointer to the function to be called when the
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//! LPC interrupt occurs.
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//!
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//! This function registers the handler to be called when an LPC interrupt
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//! occurs. This function enables the global interrupt in the interrupt
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//! controller; specific LPC interrupts must be enabled via LPCIntEnable(). If
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//! necessary, it is the interrupt handler's responsibility to clear the
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//! interrupt source via LPCIntClear().
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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LPCIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == LPC0_BASE);
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ASSERT(pfnHandler != 0);
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//
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// Register the interrupt handler.
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//
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IntRegister(INT_LPC0, pfnHandler);
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//
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// Enable the LPC interrupt.
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//
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IntEnable(INT_LPC0);
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}
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|
|
//*****************************************************************************
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//
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//! Unregisters an interrupt handler for the LPC module.
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//!
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//! \param ulBase specifies the LPC module base address.
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//!
|
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//! This function unregisters the handler to be called when an LPC interrupt
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//! occurs. This fucntion also masks off the interrupt in the interrupt
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//! controller so that the interrupt handler is no longer called.
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//!
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//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
|
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void
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LPCIntUnregister(unsigned long ulBase)
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{
|
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//
|
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// Check the arguments.
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//
|
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ASSERT(ulBase == LPC0_BASE);
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|
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//
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// Disable the LPC interrupt.
|
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//
|
|
IntDisable(INT_LPC0);
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|
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//
|
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// Unregister the interrupt handler.
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//
|
|
IntUnregister(INT_LPC0);
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|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables individual LPC interrupt sources.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
|
|
//!
|
|
//! This function enables the indicated LPC interrupt sources. Only the
|
|
//! sources that are enabled can be reflected to the processor interrupt;
|
|
//! disabled sources have no effect on the processor.
|
|
//!
|
|
//! The \e ulIntFlags parameter can be any of the following values:
|
|
//! \b LPC_INT_RST, \b LPC_INT_SLEEP, \b LPC_INT_COMx, \b LPC_INT_SIRQ,
|
|
//! \b LPC_INT_CHx_EP_TO_HOST, \b LPC_INT_CHx_EP_FROM_DATA,
|
|
//! \b LPC_INT_CHx_EP_FROM_CMD, \b LPC_INT_CHx_MB_HOST_WON,
|
|
//! \b LPC_INT_CHx_MB_HOST_WRITE, \b LPC_INT_CHx_MB_HOST_READ, or
|
|
//! \b LPC_INT_CHx_MB_MCU_LOST, where \b CHx can be \b CH6, \b CH5, \b CH4,
|
|
//! \b CH3, \b CH2, \b CH1, or \b CH0.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
|
|
//
|
|
// Get the current mask value.
|
|
//
|
|
HWREG(ulBase + LPC_O_IM) |= ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables individual LPC interrupt sources.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
|
|
//!
|
|
//! This funciton disables the indicated LPC interrupt sources. Only the
|
|
//! sources that are enabled can be reflected to the processor interrupt;
|
|
//! disabled sources have no effect on the processor.
|
|
//!
|
|
//! \sa The description of the LPCIntEnable() function provides detailed
|
|
//! information for the bit-mapped values in \e ulIntFlags.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
|
|
//
|
|
// Disable the specified interrupts.
|
|
//
|
|
HWREG(ulBase + LPC_O_IM) &= ~ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current interrupt status.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param bMasked is \b false if the raw interrupt status is required or
|
|
//! \b true if the masked interrupt status is required.
|
|
//!
|
|
//! This function returns the interrupt status for the LPC module. Either the
|
|
//! raw interrupt status or the status of interrupts that are allowed to
|
|
//! reflect to the processor can be returned.
|
|
//!
|
|
//! The interpretation of the LPC_INT_CHx fields varies based on the type
|
|
//! value programed for the specific Channel.
|
|
//!
|
|
//! \sa The description of the LPCIntEnable() function provides detailed
|
|
//! information for the bit-mapped values returned by this function.
|
|
//!
|
|
//! \return The current interrupt status.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
LPCIntStatus(unsigned long ulBase, tBoolean bMasked)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
|
|
//
|
|
// Return either the interrupt status or the raw interrupt status as
|
|
// requested.
|
|
//
|
|
if(bMasked)
|
|
{
|
|
return(HWREG(ulBase + LPC_O_MIS));
|
|
}
|
|
else
|
|
{
|
|
return(HWREG(ulBase + LPC_O_RIS));
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears LPC interrupt sources.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
|
|
//!
|
|
//! The specified LPC interrupt sources are cleared so that they no longer
|
|
//! assert. This function must be called in the interrupt handler to keep the
|
|
//! interrupts from being recognized again immediately upon exit.
|
|
//!
|
|
//! \sa The description of the LPCIntEnable() function provides detailed
|
|
//! information for the bit-mapped values in \e ulIntFlags.
|
|
//!
|
|
//! \note Because there is a write buffer in the Cortex-M processor, it may
|
|
//! take several clock cycles before the interrupt source is actually cleared.
|
|
//! Therefore, it is recommended that the interrupt source be cleared early in
|
|
//! the interrupt handler (as opposed to the very last action) to avoid
|
|
//! returning from the interrupt handler before the interrupt source is
|
|
//! actually cleared. Failure to do so may result in the interrupt handler
|
|
//! being immediately reentered (because the interrupt controller still sees
|
|
//! the interrupt source asserted).
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCIntClear(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
|
|
//
|
|
// Clear the requested interrupt sources.
|
|
//
|
|
HWREG(ulBase + LPC_O_IC) = ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables an LPC Channel.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulChannel specifies the LPC channel to enable.
|
|
//!
|
|
//! The specified LPC Channel is enabled.
|
|
//!
|
|
//! The value for the \e ulChannel parameter can be any one of the following
|
|
//! values: \b LPC_CHAN_CH0, \b LPC_CHAN_CH1, \b LPC_CHAN_CH2,
|
|
//! \b LPC_CHAN_CH3, \b LPC_CHAN_CH4, \b LPC_CHAN_CH5, \b LPC_CHAN_CH6 or
|
|
//! \b LPC_CHAN_CH7.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCChannelEnable(unsigned long ulBase, unsigned long ulChannel)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(LPCChannelValid(ulChannel));
|
|
|
|
//
|
|
// Enable the specified channel.
|
|
//
|
|
HWREG(ulBase + LPC_O_CTL) |= (1 << ulChannel);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables an LPC Channel.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulChannel specifies the LPC channel to disable.
|
|
//!
|
|
//! This function disables the specified LPC Channel.
|
|
//!
|
|
//! \sa The description of the LPCChannelEnable() function provides detailed
|
|
//! information for the values that can be usd for the \e ulChannel parameter.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCChannelDisable(unsigned long ulBase, unsigned long ulChannel)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(LPCChannelValid(ulChannel));
|
|
|
|
//
|
|
// Disable the specified channel.
|
|
//
|
|
HWREG(ulBase + LPC_O_CTL) &= ~(1 << ulChannel);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the configuration of an LPC Channel as an endpoint.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulChannel specifies the LPC channel to configure.
|
|
//! \param ulConfig specifies configuration options required for the endpoint.
|
|
//! \param ulOffset specifies the offset from the beginning of the buffer pool
|
|
//! for this endpoint's data.
|
|
//! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this
|
|
//! channel.
|
|
//!
|
|
//! This function enables the specified LPC Channel as an endpoint.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCChannelConfigEPSet(unsigned long ulBase, unsigned long ulChannel,
|
|
unsigned long ulConfig, unsigned long ulAddress,
|
|
unsigned long ulOffset)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(LPCChannelValid(ulChannel));
|
|
ASSERT((ulConfig & ~(LPC_CH0CTL_IRQSEL1_M | LPC_CH0CTL_IRQSEL0_M |
|
|
LPC_CH0CTL_IRQEN1 | LPC_CH0CTL_IRQEN0_M)) == 0);
|
|
ASSERT((ulOffset & 3) == 0);
|
|
ASSERT(ulOffset < ((((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >>
|
|
16) * 256) - 4));
|
|
|
|
//
|
|
// Convert the byte offset address into a half-word
|
|
// offset address and add into the control word.
|
|
//
|
|
ulConfig |= (((ulOffset >> 1) << LPC_CH0CTL_OFFSET_S) &
|
|
LPC_CH0CTL_OFFSET_M);
|
|
|
|
//
|
|
// Write the final control value into the control word for
|
|
// the channel.
|
|
//
|
|
HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)) = ulConfig;
|
|
|
|
//
|
|
// Setup the IO and/or MEM address to match for this channel.
|
|
//
|
|
HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)) = ulAddress;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the configuration of an LPC Channel as a mailbox.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulChannel specifies the LPC channel to configure.
|
|
//! \param ulConfig specifies configuration options required for the endpoint.
|
|
//! \param ulOffset specifies the offset from the beginning of the buffer pool
|
|
//! for this endpoint's data.
|
|
//! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this
|
|
//! channel.
|
|
//!
|
|
//! This function enables the specified LPC Channel as a mailbox.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCChannelConfigMBSet(unsigned long ulBase, unsigned long ulChannel,
|
|
unsigned long ulConfig, unsigned long ulAddress,
|
|
unsigned long ulOffset)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(LPCChannelValid(ulChannel));
|
|
ASSERT((ulConfig & ~(LPC_CH0CTL_IRQSEL1_M | LPC_CH0CTL_IRQSEL1_M |
|
|
LPC_CH0CTL_IRQSEL0_M |
|
|
LPC_CH0CTL_IRQEN2 | LPC_CH0CTL_IRQEN1 |
|
|
LPC_CH0CTL_IRQEN0_M |
|
|
LPC_CH0CTL_ARBDIS | LPC_CH0CTL_AMASK_M)) == 0);
|
|
ASSERT((ulOffset & 3) == 0);
|
|
ASSERT(ulOffset < ((((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >>
|
|
16) * 256) - 4));
|
|
|
|
//
|
|
// Convert the byte offset address into a half-word
|
|
// offset address and add into the control word.
|
|
//
|
|
ulConfig |= (((ulOffset >> 1) << LPC_CH0CTL_OFFSET_S) &
|
|
LPC_CH0CTL_OFFSET_M);
|
|
|
|
//
|
|
// Set the configuration bit that enables Mailbox mode.
|
|
//
|
|
ulConfig |= LPC_CH0CTL_TYPE;
|
|
|
|
//
|
|
// Write the final control value into the control word for
|
|
// the channel.
|
|
//
|
|
HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)) = ulConfig;
|
|
|
|
//
|
|
// Setup the IO and/or MEM address to match for this channel.
|
|
//
|
|
HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)) = ulAddress;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the configuration of an LPC Channel as a COMx.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulChannel specifies the LPC channel to configure.
|
|
//! \param ulConfig specifies configuration options required for the endpoint.
|
|
//! \param ulOffset specifies the offset from the beginning of the buffer pool
|
|
//! for this endpoint's data.
|
|
//! \param ulAddress specifies the LPC bus address (IO and/or MEM) for this
|
|
//! channel.
|
|
//! \param ulCOMxMode specifies the COMx mode to be used.
|
|
//!
|
|
//! The specified LPC Channel is enabled as a COMx.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCChannelConfigCOMxSet(unsigned long ulBase, unsigned long ulChannel,
|
|
unsigned long ulConfig, unsigned long ulAddress,
|
|
unsigned long ulOffset, unsigned long ulCOMxMode)
|
|
{
|
|
unsigned long ulTemp;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(LPCChannelValid(ulChannel));
|
|
ASSERT(ulChannel == LPC_CHAN_COMx);
|
|
ASSERT((ulConfig & ~(LPC_CH7CTL_IRQSEL1_M | LPC_CH7CTL_IRQSEL0_M |
|
|
LPC_CH7CTL_CX | LPC_CH7CTL_IRQEN1 |
|
|
LPC_CH7CTL_IRQEN0_M)) == 0);
|
|
ASSERT((ulOffset & 3) == 0);
|
|
ASSERT(ulOffset < ((((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >>
|
|
16) * 256) - 4));
|
|
ASSERT((ulCOMxMode & ~LPC_DMACX_CXACT_M) == 0);
|
|
|
|
//
|
|
// Convert the byte offset address into a half-word
|
|
// offset address and add into the control word.
|
|
//
|
|
ulConfig |= (((ulOffset >> 1) << LPC_CH0CTL_OFFSET_S) &
|
|
LPC_CH0CTL_OFFSET_M);
|
|
|
|
//
|
|
// Write the final control value into the control word for
|
|
// the channel.
|
|
//
|
|
HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10)) = ulConfig;
|
|
|
|
//
|
|
// Setup the IO and/or MEM address to match for this channel.
|
|
//
|
|
HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10)) = ulAddress;
|
|
|
|
//
|
|
// Configure the COMx Mode for this channel.
|
|
//
|
|
ulTemp = HWREG(ulBase + LPC_O_DMACX);
|
|
ulTemp &= ~LPC_DMACX_CXACT_M;
|
|
ulTemp |= ulCOMxMode;
|
|
ulTemp |= LPC_DMACX_COMX;
|
|
HWREG(ulBase + LPC_O_DMACX) = ulTemp;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the configuration of an LPC Channel.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulChannel specifies the LPC channel to configure.
|
|
//! \param pulOffset is a pointer to storage for the channel pool offset.
|
|
//! \param pulAddress is a pointer to storage for the channel bus address.
|
|
//! \param pulCOMxMode is a pointer to storage for the channel COMx mode.
|
|
//!
|
|
//! This function determines and returns the configuration for the specified
|
|
//! channel.
|
|
//!
|
|
//! \return Returns the bit-mapped channel control register value.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
LPCChannelConfigGet(unsigned long ulBase, unsigned long ulChannel,
|
|
unsigned long *pulAddress, unsigned long *pulOffset,
|
|
unsigned long *pulCOMxMode)
|
|
{
|
|
unsigned long ulConfig;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(LPCChannelValid(ulChannel));
|
|
|
|
//
|
|
// Read the channel control register.
|
|
//
|
|
ulConfig = HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10));
|
|
|
|
//
|
|
// Get the buffer pool offset value.
|
|
//
|
|
if(pulOffset)
|
|
{
|
|
*pulOffset = ((ulConfig & LPC_CH0CTL_OFFSET_M) >>
|
|
(LPC_CH0CTL_OFFSET_S - 1));
|
|
}
|
|
|
|
//
|
|
// Get the IO/Memory address that this endpoint responds to.
|
|
//
|
|
if(pulAddress)
|
|
{
|
|
*pulAddress = HWREG(ulBase + LPC_O_CH0ADR + (ulChannel * 0x10));
|
|
}
|
|
|
|
//
|
|
// Configure the COMx Mode for this channel.
|
|
//
|
|
if(pulCOMxMode && (ulChannel == LPC_CHAN_COMx))
|
|
{
|
|
*pulCOMxMode = (HWREG(ulBase + LPC_O_DMACX) & 0x00070000);
|
|
}
|
|
|
|
//
|
|
// Return the raw config value.
|
|
//
|
|
return(ulConfig);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the absolute base address of the channel pool.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulChannel specifies the LPC channel to configure.
|
|
//!
|
|
//! Thos function calculates the absolute address of the channel pool from the
|
|
//! channel configuration setting and returns it.
|
|
//!
|
|
//! \return Returns the absolute base address of the channel pool.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
LPCChannelPoolAddressGet(unsigned long ulBase, unsigned long ulChannel)
|
|
{
|
|
unsigned long ulAddress;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(LPCChannelValid(ulChannel));
|
|
|
|
//
|
|
// Read the channel control register.
|
|
//
|
|
ulAddress = HWREG(ulBase + LPC_O_CH0CTL + (ulChannel * 0x10));
|
|
|
|
//
|
|
// Mask off the channel offset portion and shift it into a byte
|
|
// offset (stored as half-word offset).
|
|
//
|
|
ulAddress = ((ulAddress & LPC_CH0CTL_OFFSET_M) >>
|
|
(LPC_CH0CTL_OFFSET_S - 1));
|
|
|
|
//
|
|
// Add the LPC and Buffer Pool base address to get the final
|
|
// address to return.
|
|
//
|
|
ulAddress += (ulBase + LPC_O_POOL);
|
|
|
|
//
|
|
// Return the address to the calling routine.
|
|
//
|
|
return(ulAddress);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Reads the status word from an LPC Channel.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulChannel specifies the LPC Channel.
|
|
//!
|
|
//! This function reads the status word from an LPC channel and returns it to
|
|
//! the caller.
|
|
//!
|
|
//! \return content of the channel status register.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
LPCChannelStatusGet(unsigned long ulBase, unsigned long ulChannel)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(LPCChannelValid(ulChannel));
|
|
|
|
//
|
|
// Read the half-word status from the LPC Channel
|
|
//
|
|
return (HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the user bits in the status word (16-bits) of an LPC Channel.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulChannel specifies the LPC Channel.
|
|
//! \param ulStatus is the user bit values to set.
|
|
//!
|
|
//! This function sets the selected user bits of the status word for an LPC
|
|
//! channel.
|
|
//!
|
|
//! \return None
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel,
|
|
unsigned long ulStatus)
|
|
{
|
|
unsigned long ulTemp;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(LPCChannelValid(ulChannel));
|
|
ASSERT((ulStatus & (~LPC_CH0ST_USER_M)) == 0);
|
|
|
|
//
|
|
// Read the status from the LPC Channel, and set new values for
|
|
// the user bits.
|
|
//
|
|
ulTemp = HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10));
|
|
ulTemp |= ulStatus;
|
|
HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)) = ulTemp;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears the user bits in the status word (16-bits) of an LPC Channel.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulChannel specifies the LPC Channel.
|
|
//! \param ulStatus is the user bit values to clear.
|
|
//!
|
|
//! This function sets the selected user bits of the status word for an LPC
|
|
//! channel.
|
|
//!
|
|
//! \return None
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCChannelStatusClear(unsigned long ulBase, unsigned long ulChannel,
|
|
unsigned long ulStatus)
|
|
{
|
|
unsigned long ulTemp;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(LPCChannelValid(ulChannel));
|
|
ASSERT((ulStatus & (~LPC_CH0ST_USER_M)) == 0);
|
|
|
|
//
|
|
// Read the status from the LPC Channel, and set new values for
|
|
// the user bits.
|
|
//
|
|
ulTemp = HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10));
|
|
ulTemp &= ~ulStatus;
|
|
HWREG(ulBase + LPC_O_CH0ST + (ulChannel * 0x10)) = ulTemp;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the configuration of DMA for LPC channels.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulConfig specifies the DMA channel configuration.
|
|
//! \param ulMask specifies the configuration mask to be used.
|
|
//!
|
|
//! This function sets the specified DMA channel operation based on the
|
|
//! \e ulConfig parameter.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCChannelDMAConfigSet(unsigned long ulBase, unsigned long ulConfig,
|
|
unsigned long ulMask)
|
|
{
|
|
unsigned long ulTemp;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT((ulConfig & ~0x000000FF) == 0);
|
|
ASSERT((ulConfig & 0x00000003) != 0x00000003);
|
|
ASSERT((ulConfig & 0x0000000C) != 0x0000000C);
|
|
ASSERT((ulConfig & 0x00000030) != 0x00000030);
|
|
ASSERT((ulConfig & 0x000000C0) != 0x000000C0);
|
|
ASSERT((ulMask & ~0x000000FF) == 0);
|
|
|
|
//
|
|
// Get the current mask value.
|
|
//
|
|
ulTemp = HWREG(ulBase + LPC_O_DMACX);
|
|
ulTemp &= ~ulMask;
|
|
ulTemp |= (ulConfig & ulMask);
|
|
HWREG(ulBase + LPC_O_DMACX) = ulTemp;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the configuration of DMA for LPC channels.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//!
|
|
//! This function returns the configuration of the LPC DMA channels.
|
|
//!
|
|
//! \return Returns the bit-mapped DMA channel configuration.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
LPCChannelDMAConfigGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
|
|
//
|
|
// Get the current mask value.
|
|
//
|
|
return(HWREG(ulBase + LPC_O_DMACX) & 0x000000FF);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Reads a byte from the LPC channel pool.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulOffset specifies the offset from the beginning of the LPC channel
|
|
//! pool.
|
|
//!
|
|
//! This function reads a byte from the channel pool.
|
|
//!
|
|
//! \return Returns the byte read from the pool memory.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned char
|
|
LPCByteRead(unsigned long ulBase, unsigned long ulOffset)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >>
|
|
16) * 256));
|
|
|
|
//
|
|
// Return the byte from the LPC Buffer Pool.
|
|
//
|
|
return(HWREGB(ulBase + LPC_O_POOL + ulOffset));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Writes a byte to the LPC channel pool.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulOffset specifies the offset from the beginning of the LPC channel
|
|
//! pool.
|
|
//! \param ucData specifies the byte to write.
|
|
//!
|
|
//! This function writes a byte to the channel pool.
|
|
//!
|
|
//! \return None
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCByteWrite(unsigned long ulBase, unsigned long ulOffset,
|
|
unsigned char ucData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >>
|
|
16) * 256));
|
|
|
|
//
|
|
// Write the byte to the LPC Buffer Pool.
|
|
//
|
|
HWREGB(ulBase + LPC_O_POOL + ulOffset) = ucData;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Reads a half-word from the LPC channel pool.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulOffset specifies the offset from the beginning of the LPC channel
|
|
//! pool.
|
|
//!
|
|
//! This function reads a half-word from the channel pool. The \e ulOffset
|
|
//! specified must be half-word aligned.
|
|
//!
|
|
//! \return Returns the half-word read from the pool memory.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned short
|
|
LPCHalfWordRead(unsigned long ulBase, unsigned long ulOffset)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT((ulOffset & 1) == 0);
|
|
ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >>
|
|
16) * 256));
|
|
|
|
//
|
|
// Return the half-word from the LPC Buffer Pool.
|
|
//
|
|
return(HWREGH(ulBase + LPC_O_POOL + ulOffset));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Writes a half-word to the LPC channel pool.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulOffset specifies the offset from the beginning of the LPC channel
|
|
//! pool.
|
|
//! \param usData specifies the byte to write.
|
|
//!
|
|
//! This function writes a half-word to the channel pool. The \e ulOffset
|
|
//! specified must be half-word aligned.
|
|
//!
|
|
//! \return None
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCHalfWordWrite(unsigned long ulBase, unsigned long ulOffset,
|
|
unsigned short usData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT((ulOffset & 1) == 0);
|
|
ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >>
|
|
16) * 256));
|
|
|
|
//
|
|
// Write the half-word to the LPC Buffer Pool.
|
|
//
|
|
HWREGH(ulBase + LPC_O_POOL + ulOffset) = usData;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Reads a word from the LPC channel pool.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulOffset specifies the offset from the beginning of the LPC channel
|
|
//! pool.
|
|
//!
|
|
//! This function reads a word from the channel pool. The \e ulOffset
|
|
//! specified must be word aligned.
|
|
//!
|
|
//! \return Returns the word read from the pool memory.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
LPCWordRead(unsigned long ulBase, unsigned long ulOffset)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT((ulOffset & 3) == 0);
|
|
ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >>
|
|
16) * 256));
|
|
|
|
//
|
|
// Return the word from the LPC Buffer Pool.
|
|
//
|
|
return(HWREG(ulBase + LPC_O_POOL + ulOffset));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Writes a word to the LPC channel pool.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulOffset specifies the offset from the beginning of the LPC channel
|
|
//! pool.
|
|
//! \param ulData specifies the word to write.
|
|
//!
|
|
//! This function writes a word to the channel pool. The \e ulOffset
|
|
//! specified must be word aligned.
|
|
//!
|
|
//! \return None
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCWordWrite(unsigned long ulBase, unsigned long ulOffset,
|
|
unsigned long ulData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT((ulOffset & 1) == 0);
|
|
ASSERT(ulOffset < (((HWREG(ulBase + LPC_O_STS) & LPC_STS_POOLSZ_M) >>
|
|
16) * 256));
|
|
|
|
//
|
|
// Write the word to the LPC Buffer Pool.
|
|
//
|
|
HWREG(ulBase + LPC_O_POOL + ulOffset) = ulData;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables individual COMx interrupt sources.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
|
|
//!
|
|
//! This function enables the indicated COMx interrupt sources to trigger the
|
|
//! COMx interrupt in the primary LPC interrupt registers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCCOMxIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT((ulIntFlags & ~(LPC_DMACX_CXEM | LPC_DMACX_CXTXEM |
|
|
LPC_DMACX_CXRXEM)) == 0);
|
|
|
|
//
|
|
// Get the current mask value.
|
|
//
|
|
HWREG(ulBase + LPC_O_DMACX) |= ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables individual COMx interrupt sources.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
|
|
//!
|
|
//! This function disables the indicated COMx interrupt sources from triggering
|
|
//! the COMx interrupt in the primary LPC interrupt registers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCCOMxIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT((ulIntFlags & ~(LPC_DMACX_CXEM | LPC_DMACX_CXTXEM |
|
|
LPC_DMACX_CXRXEM)) == 0);
|
|
|
|
//
|
|
// Disable the specified interrupts.
|
|
//
|
|
HWREG(ulBase + LPC_O_DMACX) &= ~ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current COMx interrupt status.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param bMasked is \b false if the raw interrupt status is required or
|
|
//! \b true if the masked interrupt status is required.
|
|
//!
|
|
//! This function returns the interrupt status for the COMx module.
|
|
//!
|
|
//! \return The current interrupt status.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
LPCCOMxIntStatus(unsigned long ulBase, tBoolean bMasked)
|
|
{
|
|
unsigned long ulStatus;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
|
|
//
|
|
// Return either the interrupt status or the raw interrupt status as
|
|
// requested.
|
|
//
|
|
ulStatus = HWREG(ulBase + LPC_O_DMACX);
|
|
if(bMasked)
|
|
{
|
|
ulStatus = ulStatus & (ulStatus << 4);
|
|
}
|
|
return(ulStatus & (LPC_DMACX_CXRES | LPC_DMACX_CXTXRES |
|
|
LPC_DMACX_CXRXRES));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears COMx interrupt sources.
|
|
//!
|
|
//! \param ulBase specifies the LPC module base address.
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
|
|
//!
|
|
//! This function clears the specified COMx interrupt sources so that they no
|
|
//! longer assert.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
LPCCOMxIntClear(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == LPC0_BASE);
|
|
ASSERT((ulIntFlags & ~(LPC_DMACX_CXRES | LPC_DMACX_CXTXRES |
|
|
LPC_DMACX_CXRXRES)) == 0);
|
|
|
|
//
|
|
// Clear the requested interrupt sources.
|
|
//
|
|
HWREG(ulBase + LPC_O_DMACX) |= ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|