377 lines
22 KiB
C
377 lines
22 KiB
C
/*!
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\file gd32f4xx_tli.h
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\brief definitions for the TLI
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\version 2016-08-15, V1.0.0, firmware for GD32F4xx
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\version 2018-12-12, V2.0.0, firmware for GD32F4xx
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\version 2020-09-30, V2.1.0, firmware for GD32F4xx
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F4XX_TLI_H
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#define GD32F4XX_TLI_H
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#include "gd32f4xx.h"
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/* TLI definitions */
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#define TLI TLI_BASE /*!< TLI base address */
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/* TLI layer definitions */
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#define LAYER0 TLI_BASE /*!< TLI layer0 base address */
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#define LAYER1 (TLI_BASE+0x80) /*!< TLI layer1 base address */
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/* registers definitions */
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#define TLI_SPSZ REG32(TLI + 0x08U) /*!< TLI synchronous pulse size register */
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#define TLI_BPSZ REG32(TLI + 0x0CU) /*!< TLI back-porch size register */
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#define TLI_ASZ REG32(TLI + 0x10U) /*!< TLI active size register */
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#define TLI_TSZ REG32(TLI + 0x14U) /*!< TLI total size register */
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#define TLI_CTL REG32(TLI + 0x18U) /*!< TLI control register */
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#define TLI_RL REG32(TLI + 0x24U) /*!< TLI reload Layer register */
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#define TLI_BGC REG32(TLI + 0x2CU) /*!< TLI background color register */
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#define TLI_INTEN REG32(TLI + 0x34U) /*!< TLI interrupt enable register */
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#define TLI_INTF REG32(TLI + 0x38U) /*!< TLI interrupt flag register */
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#define TLI_INTC REG32(TLI + 0x3CU) /*!< TLI interrupt flag clear register */
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#define TLI_LM REG32(TLI + 0x40U) /*!< TLI line mark register */
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#define TLI_CPPOS REG32(TLI + 0x44U) /*!< TLI current pixel position register */
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#define TLI_STAT REG32(TLI + 0x48U) /*!< TLI status register */
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#define TLI_LxCTL(layerx) REG32((layerx) + 0x84U) /*!< TLI layer x control register */
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#define TLI_LxHPOS(layerx) REG32((layerx) + 0x88U) /*!< TLI layer x horizontal position parameters register */
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#define TLI_LxVPOS(layerx) REG32((layerx) + 0x8CU) /*!< TLI layer x vertical position parameters register */
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#define TLI_LxCKEY(layerx) REG32((layerx) + 0x90U) /*!< TLI layer x color key register */
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#define TLI_LxPPF(layerx) REG32((layerx) + 0x94U) /*!< TLI layer x packeted pixel format register */
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#define TLI_LxSA(layerx) REG32((layerx) + 0x98U) /*!< TLI layer x specified alpha register */
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#define TLI_LxDC(layerx) REG32((layerx) + 0x9CU) /*!< TLI layer x default color register */
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#define TLI_LxBLEND(layerx) REG32((layerx) + 0xA0U) /*!< TLI layer x blending register */
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#define TLI_LxFBADDR(layerx) REG32((layerx) + 0xACU) /*!< TLI layer x frame base address register */
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#define TLI_LxFLLEN(layerx) REG32((layerx) + 0xB0U) /*!< TLI layer x frame line length register */
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#define TLI_LxFTLN(layerx) REG32((layerx) + 0xB4U) /*!< TLI layer x frame total line number register */
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#define TLI_LxLUT(layerx) REG32((layerx) + 0xC4U) /*!< TLI layer x look up table register */
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/* bits definitions */
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/* TLI_SPSZ */
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#define TLI_SPSZ_VPSZ BITS(0,11) /*!< size of the vertical synchronous pulse */
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#define TLI_SPSZ_HPSZ BITS(16,27) /*!< size of the horizontal synchronous pulse */
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/* TLI_BPSZ */
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#define TLI_BPSZ_VBPSZ BITS(0,11) /*!< size of the vertical back porch plus synchronous pulse */
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#define TLI_BPSZ_HBPSZ BITS(16,27) /*!< size of the horizontal back porch plus synchronous pulse */
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/* TLI_ASZ */
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#define TLI_ASZ_VASZ BITS(0,11) /*!< size of the vertical active area width plus back porch and synchronous pulse */
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#define TLI_ASZ_HASZ BITS(16,27) /*!< size of the horizontal active area width plus back porch and synchronous pulse */
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/* TLI_SPSZ */
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#define TLI_TSZ_VTSZ BITS(0,11) /*!< vertical total size of the display, including active area, back porch, synchronous pulse and front porch */
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#define TLI_TSZ_HTSZ BITS(16,27) /*!< horizontal total size of the display, including active area, back porch, synchronous pulse and front porch */
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/* TLI_CTL */
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#define TLI_CTL_TLIEN BIT(0) /*!< TLI enable bit */
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#define TLI_CTL_BDB BITS(4,6) /*!< blue channel dither bits number */
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#define TLI_CTL_GDB BITS(8,10) /*!< green channel dither bits number */
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#define TLI_CTL_RDB BITS(12,14) /*!< red channel dither bits number */
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#define TLI_CTL_DFEN BIT(16) /*!< dither function enable */
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#define TLI_CTL_CLKPS BIT(28) /*!< pixel clock polarity selection */
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#define TLI_CTL_DEPS BIT(29) /*!< data enable polarity selection */
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#define TLI_CTL_VPPS BIT(30) /*!< vertical pulse polarity selection */
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#define TLI_CTL_HPPS BIT(31) /*!< horizontal pulse polarity selection */
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/* TLI_RL */
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#define TLI_RL_RQR BIT(0) /*!< request reload */
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#define TLI_RL_FBR BIT(1) /*!< frame blank reload */
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/* TLI_BGC */
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#define TLI_BGC_BVB BITS(0,7) /*!< background value blue */
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#define TLI_BGC_BVG BITS(8,15) /*!< background value green */
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#define TLI_BGC_BVR BITS(16,23) /*!< background value red */
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/* TLI_INTEN */
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#define TLI_INTEN_LMIE BIT(0) /*!< line mark interrupt enable */
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#define TLI_INTEN_FEIE BIT(1) /*!< FIFO error interrupt enable */
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#define TLI_INTEN_TEIE BIT(2) /*!< transaction error interrupt enable */
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#define TLI_INTEN_LCRIE BIT(3) /*!< layer configuration reloaded interrupt enable */
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/* TLI_INTF */
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#define TLI_INTF_LMF BIT(0) /*!< line mark flag */
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#define TLI_INTF_FEF BIT(1) /*!< FIFO error flag */
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#define TLI_INTF_TEF BIT(2) /*!< transaction error flag */
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#define TLI_INTF_LCRF BIT(3) /*!< layer configuration reloaded flag */
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/* TLI_INTC */
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#define TLI_INTC_LMC BIT(0) /*!< line mark flag clear */
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#define TLI_INTC_FEC BIT(1) /*!< FIFO error flag clear */
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#define TLI_INTC_TEC BIT(2) /*!< transaction error flag clear */
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#define TLI_INTC_LCRC BIT(3) /*!< layer configuration reloaded flag clear */
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/* TLI_LM */
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#define TLI_LM_LM BITS(0,10) /*!< line mark value */
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/* TLI_CPPOS */
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#define TLI_CPPOS_VPOS BITS(0,15) /*!< vertical position */
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#define TLI_CPPOS_HPOS BITS(16,31) /*!< horizontal position */
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/* TLI_STAT */
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#define TLI_STAT_VDE BIT(0) /*!< current VDE status */
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#define TLI_STAT_HDE BIT(1) /*!< current HDE status */
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#define TLI_STAT_VS BIT(2) /*!< current VS status of the TLI */
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#define TLI_STAT_HS BIT(3) /*!< current HS status of the TLI */
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/* TLI_LxCTL */
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#define TLI_LxCTL_LEN BIT(0) /*!< layer enable */
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#define TLI_LxCTL_CKEYEN BIT(1) /*!< color keying enable */
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#define TLI_LxCTL_LUTEN BIT(4) /*!< LUT enable */
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/* TLI_LxHPOS */
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#define TLI_LxHPOS_WLP BITS(0,11) /*!< window left position */
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#define TLI_LxHPOS_WRP BITS(16,27) /*!< window right position */
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/* TLI_LxVPOS */
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#define TLI_LxVPOS_WTP BITS(0,11) /*!< window top position */
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#define TLI_LxVPOS_WBP BITS(16,27) /*!< window bottom position */
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/* TLI_LxCKEY */
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#define TLI_LxCKEY_CKEYB BITS(0,7) /*!< color key blue */
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#define TLI_LxCKEY_CKEYG BITS(8,15) /*!< color key green */
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#define TLI_LxCKEY_CKEYR BITS(16,23) /*!< color key red */
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/* TLI_LxPPF */
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#define TLI_LxPPF_PPF BITS(0,2) /*!< packeted pixel format */
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/* TLI_LxSA */
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#define TLI_LxSA_SA BITS(0,7) /*!< specified alpha */
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/* TLI_LxDC */
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#define TLI_LxDC_DCB BITS(0,7) /*!< the default color blue */
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#define TLI_LxDC_DCG BITS(8,15) /*!< the default color green */
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#define TLI_LxDC_DCR BITS(16,23) /*!< the default color red */
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#define TLI_LxDC_DCA BITS(24,31) /*!< the default color alpha */
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/* TLI_LxBLEND */
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#define TLI_LxBLEND_ACF2 BITS(0,2) /*!< alpha calculation factor 2 of blending method */
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#define TLI_LxBLEND_ACF1 BITS(8,10) /*!< alpha calculation factor 1 of blending method */
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/* TLI_LxFBADDR */
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#define TLI_LxFBADDR_FBADD BITS(0,31) /*!< frame buffer base address */
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/* TLI_LxFLLEN */
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#define TLI_LxFLLEN_FLL BITS(0,13) /*!< frame line length */
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#define TLI_LxFLLEN_STDOFF BITS(16,29) /*!< frame buffer stride offset */
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/* TLI_LxFTLN */
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#define TLI_LxFTLN_FTLN BITS(0,10) /*!< frame total line number */
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/* TLI_LxLUT */
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#define TLI_LxLUT_TB BITS(0,7) /*!< blue channel of a LUT entry */
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#define TLI_LxLUT_TG BITS(8,15) /*!< green channel of a LUT entry */
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#define TLI_LxLUT_TR BITS(16,23) /*!< red channel of a LUT entry */
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#define TLI_LxLUT_TADD BITS(24,31) /*!< look up table write address */
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/* constants definitions */
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/* TLI parameter struct definitions */
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typedef struct
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{
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uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */
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uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */
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uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */
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uint16_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */
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uint32_t activesz_vasz; /*!< size of the vertical active area width plus back porch and synchronous pulse */
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uint32_t activesz_hasz; /*!< size of the horizontal active area width plus back porch and synchronous pulse */
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uint32_t totalsz_vtsz; /*!< vertical total size of the display */
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uint32_t totalsz_htsz; /*!< horizontal total size of the display */
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uint32_t backcolor_red; /*!< background value red */
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uint32_t backcolor_green; /*!< background value green */
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uint32_t backcolor_blue; /*!< background value blue */
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uint32_t signalpolarity_hs; /*!< horizontal pulse polarity selection */
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uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */
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uint32_t signalpolarity_de; /*!< data enable polarity selection */
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uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */
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}tli_parameter_struct;
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/* TLI layer parameter struct definitions */
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typedef struct
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{
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uint16_t layer_window_rightpos; /*!< window right position */
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uint16_t layer_window_leftpos; /*!< window left position */
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uint16_t layer_window_bottompos; /*!< window bottom position */
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uint16_t layer_window_toppos; /*!< window top position */
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uint32_t layer_ppf; /*!< packeted pixel format */
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uint8_t layer_sa; /*!< specified alpha */
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uint8_t layer_default_alpha; /*!< the default color alpha */
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uint8_t layer_default_red; /*!< the default color red */
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uint8_t layer_default_green; /*!< the default color green */
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uint8_t layer_default_blue; /*!< the default color blue */
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uint32_t layer_acf1; /*!< alpha calculation factor 1 of blending method */
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uint32_t layer_acf2; /*!< alpha calculation factor 2 of blending method */
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uint32_t layer_frame_bufaddr; /*!< frame buffer base address */
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uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */
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uint16_t layer_frame_line_length; /*!< frame line length */
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uint16_t layer_frame_total_line_number; /*!< frame total line number */
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}tli_layer_parameter_struct;
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/* TLI layer LUT parameter struct definitions */
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typedef struct
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{
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uint32_t layer_table_addr; /*!< look up table write address */
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uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */
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uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */
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uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */
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}tli_layer_lut_parameter_struct;
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/* packeted pixel format */
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typedef enum
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{
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LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */
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LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */
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LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */
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LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */
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LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */
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LAYER_PPF_L8, /*!< layerx pixel format L8 */
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LAYER_PPF_AL44, /*!< layerx pixel format AL44 */
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LAYER_PPF_AL88 /*!< layerx pixel format AL88 */
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}tli_layer_ppf_enum;
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/* TLI flags */
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#define TLI_FLAG_VDE TLI_STAT_VDE /*!< current VDE status */
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#define TLI_FLAG_HDE TLI_STAT_HDE /*!< current HDE status */
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#define TLI_FLAG_VS TLI_STAT_VS /*!< current VS status of the TLI */
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#define TLI_FLAG_HS TLI_STAT_HS /*!< current HS status of the TLI */
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#define TLI_FLAG_LM BIT(0) | BIT(31) /*!< line mark interrupt flag */
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#define TLI_FLAG_FE BIT(1) | BIT(31) /*!< FIFO error interrupt flag */
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#define TLI_FLAG_TE BIT(2) | BIT(31) /*!< transaction error interrupt flag */
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#define TLI_FLAG_LCR BIT(3) | BIT(31) /*!< layer configuration reloaded interrupt flag */
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/* TLI interrupt enable or disable */
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#define TLI_INT_LM BIT(0) /*!< line mark interrupt */
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#define TLI_INT_FE BIT(1) /*!< FIFO error interrupt */
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#define TLI_INT_TE BIT(2) /*!< transaction error interrupt */
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#define TLI_INT_LCR BIT(3) /*!< layer configuration reloaded interrupt */
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/* TLI interrupt flag */
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#define TLI_INT_FLAG_LM BIT(0) /*!< line mark interrupt flag */
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#define TLI_INT_FLAG_FE BIT(1) /*!< FIFO error interrupt flag */
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#define TLI_INT_FLAG_TE BIT(2) /*!< transaction error interrupt flag */
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#define TLI_INT_FLAG_LCR BIT(3) /*!< layer configuration reloaded interrupt flag */
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/* layer reload configure */
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#define TLI_FRAME_BLANK_RELOAD_EN ((uint8_t)0x00U) /*!< the layer configuration will be reloaded at frame blank */
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#define TLI_REQUEST_RELOAD_EN ((uint8_t)0x01U) /*!< the layer configuration will be reloaded after this bit sets */
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/* dither function */
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#define TLI_DITHER_DISABLE ((uint8_t)0x00U) /*!< dither function disable */
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#define TLI_DITHER_ENABLE ((uint8_t)0x01U) /*!< dither function enable */
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/* horizontal pulse polarity selection */
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#define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */
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#define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */
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/* vertical pulse polarity selection */
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#define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */
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#define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */
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/* pixel clock polarity selection */
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#define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */
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#define TLI_PIXEL_CLOCK_INVERTEDTLI TLI_CTL_CLKPS /*!< pixel clock is inverted TLI clock */
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/* data enable polarity selection */
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#define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */
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#define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */
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/* alpha calculation factor 1 of blending method */
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#define LxBLEND_ACF1(regval) (BITS(8,10) & ((uint32_t)(regval)<<8))
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#define LAYER_ACF1_SA LxBLEND_ACF1(4) /*!< normalization specified alpha */
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#define LAYER_ACF1_PASA LxBLEND_ACF1(6) /*!< normalization pixel alpha * normalization specified alpha */
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/* alpha calculation factor 2 of blending method */
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#define LxBLEND_ACF2(regval) (BITS(0,2) & ((uint32_t)(regval)))
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#define LAYER_ACF2_SA LxBLEND_ACF2(5) /*!< normalization specified alpha */
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#define LAYER_ACF2_PASA LxBLEND_ACF2(7) /*!< normalization pixel alpha * normalization specified alpha */
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/* function declarations */
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/* initialization functions, TLI enable or disable, TLI reload mode configuration */
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/* deinitialize TLI registers */
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void tli_deinit(void);
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/* initialize the parameters of TLI parameter structure with the default values, it is suggested
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that call this function after a tli_parameter_struct structure is defined */
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void tli_struct_para_init(tli_parameter_struct *tli_struct);
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/* initialize TLI */
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void tli_init(tli_parameter_struct *tli_struct);
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/* configure TLI dither function */
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void tli_dither_config(uint8_t dither_stat);
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/* enable TLI */
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void tli_enable(void);
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/* disable TLI */
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void tli_disable(void);
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/* configurate TLI reload mode */
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void tli_reload_config(uint8_t reload_mod);
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/* TLI layer configuration functions */
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/* initialize the parameters of TLI layer structure with the default values, it is suggested
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that call this function after a tli_layer_parameter_struct structure is defined */
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void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct);
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/* initialize TLI layer */
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void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct);
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/* reconfigure window position */
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void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y);
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/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested
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that call this function after a tli_layer_lut_parameter_struct structure is defined */
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void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct);
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/* initialize TLI layer LUT */
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void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct);
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/* initialize TLI layer color key */
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void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey);
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/* enable TLI layer */
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void tli_layer_enable(uint32_t layerx);
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/* disable TLI layer */
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void tli_layer_disable(uint32_t layerx);
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/* enable TLI layer color keying */
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void tli_color_key_enable(uint32_t layerx);
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/* disable TLI layer color keying */
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void tli_color_key_disable(uint32_t layerx);
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/* enable TLI layer LUT */
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void tli_lut_enable(uint32_t layerx);
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/* disable TLI layer LUT */
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void tli_lut_disable(uint32_t layerx);
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/* set line mark value */
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void tli_line_mark_set(uint16_t line_num);
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/* get current displayed position */
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uint32_t tli_current_pos_get(void);
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/* flag and interrupt functions */
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/* enable TLI interrupt */
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void tli_interrupt_enable(uint32_t int_flag);
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/* disable TLI interrupt */
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void tli_interrupt_disable(uint32_t int_flag);
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/* get TLI interrupt flag */
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FlagStatus tli_interrupt_flag_get(uint32_t int_flag);
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/* clear TLI interrupt flag */
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void tli_interrupt_flag_clear(uint32_t int_flag);
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/* get TLI flag or state in TLI_INTF register or TLI_STAT register */
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FlagStatus tli_flag_get(uint32_t flag);
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#endif /* GD32F4XX_TLI_H */
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