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89 lines
2.7 KiB
C
89 lines
2.7 KiB
C
/*
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* File : drv_sdram.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2016, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2016-08-20 xuzhuoyi The first version for STM32F42x
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "drv_sdram.h"
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#include "stm32f4xx_ll_fmc.h"
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#include <rtdevice.h>
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SDRAM_HandleTypeDef hsdram1;
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#ifndef USE_Delay
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static void delay(__IO uint32_t nCount);
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#endif /* USE_Delay*/
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/**
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* @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
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* This function must be called before any read/write operation
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* on the SDRAM.
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* @param None
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* @retval None
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*/
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void SDRAM_Init(void)
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{
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FMC_SDRAM_TimingTypeDef SdramTiming;
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/** Perform the SDRAM1 memory initialization sequence
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*/
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hsdram1.Instance = FMC_SDRAM_DEVICE;
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/* hsdram1.Init */
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hsdram1.Init.SDBank = FMC_SDRAM_BANK2;
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hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
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hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_11;
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hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
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hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1;
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hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE;
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hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
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hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
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/* SdramTiming */
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SdramTiming.LoadToActiveDelay = 16;
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SdramTiming.ExitSelfRefreshDelay = 16;
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SdramTiming.SelfRefreshTime = 16;
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SdramTiming.RowCycleDelay = 16;
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SdramTiming.WriteRecoveryTime = 16;
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SdramTiming.RPDelay = 16;
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SdramTiming.RCDDelay = 16;
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if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
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{
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Error_Handler();
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}
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}
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rt_err_t sdram_hw_init(void)
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{
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SDRAM_Init();
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return RT_EOK;
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}
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static int rt_sdram_hw_init(void)
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{
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return (int)sdram_hw_init();
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}
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INIT_BOARD_EXPORT(rt_sdram_hw_init);
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