376 lines
9.7 KiB
C
376 lines
9.7 KiB
C
/*
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* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <string.h>
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#include <stdio.h>
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#include "mmio.h"
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#include "dw_spi.h"
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#include <rthw.h>
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#ifdef SPI_DEBUG
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#define SP_DEBUG_LOG printf
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#else
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#define SP_DEBUG_LOG
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#endif
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/* Restart the controller, disable all interrupts, clean rx fifo */
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void spi_hw_init(struct dw_spi *dws)
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{
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/*
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* Try to detect the FIFO depth if not set by interface driver,
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* the depth could be from 2 to 256 from HW spec
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*/
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if (!dws->fifo_len) {
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uint32_t fifo;
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for (fifo = 1; fifo < 256; fifo++) {
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dw_writel(dws, CVI_DW_SPI_TXFTLR, fifo);
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if (fifo != dw_readl(dws, CVI_DW_SPI_TXFTLR))
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break;
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}
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dw_writel(dws, CVI_DW_SPI_TXFTLR, 0);
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dws->fifo_len = (fifo == 1) ? 0 : fifo;
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SP_DEBUG_LOG("Detected FIFO size: %u bytes\n", dws->fifo_len);
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}
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}
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uint32_t min3(uint32_t a, uint32_t b, uint32_t c)
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{
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uint32_t tmp;
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tmp = (a < b) ? a : b;
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return (tmp < c) ? tmp : c;
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}
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static inline void cpu_relax(void)
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{
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//asm volatile("" ::: "memory");
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}
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static inline uint32_t tx_max(struct dw_spi *dws)
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{
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uint32_t tx_left, tx_room, rxtx_gap, temp;
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cpu_relax();
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tx_left = dws->tx_len;
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tx_room = dws->fifo_len - dw_readl(dws, CVI_DW_SPI_TXFLR);
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/*
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* Another concern is about the tx/rx mismatch, we
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* though to use (dws->fifo_len - rxflr - txflr) as
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* one maximum value for tx, but it doesn't cover the
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* data which is out of tx/rx fifo and inside the
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* shift registers. So a control from sw point of
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* view is taken.
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*/
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SP_DEBUG_LOG("tx left: %#x, tx room: %#x\n", tx_left, tx_room);
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if (dws->rx != NULL && dws->tx != NULL) {
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cpu_relax();
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rxtx_gap = dws->fifo_len - (dws->rx_len - dws->tx_len);
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temp = min3(tx_left, tx_room, (uint32_t)(rxtx_gap));
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} else {
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temp = tx_left < tx_room ? tx_left : tx_room;
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}
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SP_DEBUG_LOG("temp: %#x\n", temp);
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return temp;
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}
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void dw_writer(struct dw_spi *dws)
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{
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uint32_t max;
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uint16_t txw = 0;
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max = tx_max(dws);
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SP_DEBUG_LOG("max: %#x \n", max);
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while (max--) {
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if (dws->tx) {
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if (dws->n_bytes == 1)
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txw = *(uint8_t *)(dws->tx);
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else
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txw = *(uint16_t *)(dws->tx);
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}
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dw_writel(dws, CVI_DW_SPI_DR, txw);
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dws->tx += dws->n_bytes;
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--dws->tx_len;
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}
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}
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static inline uint32_t rx_max(struct dw_spi *dws)
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{
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uint32_t temp;
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uint32_t rx_left = dws->rx_len;
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uint32_t data_in_fifo = dw_readl(dws, CVI_DW_SPI_RXFLR);
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temp = (rx_left < data_in_fifo ? rx_left : data_in_fifo);
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SP_DEBUG_LOG("data_in_fifo:%u temp: %u\n", data_in_fifo, temp);
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return temp;
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}
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int dw_spi_check_status(struct dw_spi *dws, bool raw)
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{
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uint32_t irq_status;
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int ret = 0;
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if (raw)
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irq_status = dw_readl(dws, CVI_DW_SPI_RISR);
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else
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irq_status = dw_readl(dws, CVI_DW_SPI_ISR);
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if (irq_status & CVI_SPI_INT_RXOI) {
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SP_DEBUG_LOG("RX FIFO overflow detected\n");
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ret = -1;
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}
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if (irq_status & CVI_SPI_INT_RXUI) {
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SP_DEBUG_LOG("RX FIFO underflow detected\n");
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ret = -1;
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}
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if (irq_status & CVI_SPI_INT_TXOI) {
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SP_DEBUG_LOG("TX FIFO overflow detected\n");
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ret = -1;
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}
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if (ret)
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spi_reset_chip(dws);
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return ret;
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}
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void dw_reader(struct dw_spi *dws)
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{
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uint32_t max;
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uint16_t rxw;
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max = rx_max(dws);
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SP_DEBUG_LOG("max: %#x \n", max);
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while (max--) {
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rxw = dw_readl(dws, CVI_DW_SPI_DR);
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if (dws->rx) {
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if (dws->n_bytes == 1)
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*(uint8_t *)(dws->rx) = rxw;
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else
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*(uint16_t *)(dws->rx) = rxw;
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dws->rx += dws->n_bytes;
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}
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--dws->rx_len;
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}
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}
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int spi_delay_to_ns(struct spi_delay *_delay, struct dw_spi *dws)
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{
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uint32_t delay = _delay->value;
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uint32_t unit = _delay->unit;
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uint32_t hz;
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if (!delay)
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return 0;
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switch (unit) {
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case SPI_DELAY_UNIT_USECS:
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delay *= 1000;
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break;
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case SPI_DELAY_UNIT_NSECS: /* nothing to do here */
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break;
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case SPI_DELAY_UNIT_SCK:
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/* clock cycles need to be obtained from spi_transfer */
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if (!dws)
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return -1;
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/* if there is no effective speed know, then approximate
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* by underestimating with half the requested hz
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*/
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hz = dws->speed_hz / 2;
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if (!hz)
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return -1;
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delay *= DIV_ROUND_UP(1000000000, hz);
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break;
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default:
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return -EINVAL;
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}
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return delay;
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}
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static void _spi_transfer_delay_ns(uint32_t ns)
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{
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if (!ns)
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return;
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if (ns <= 1000) {
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rt_hw_us_delay(1);
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} else {
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uint32_t us = DIV_ROUND_UP(ns, 1000);
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rt_hw_us_delay(us);
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}
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}
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int spi_delay_exec(struct spi_delay *_delay, struct dw_spi *dws)
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{
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int delay;
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if (!_delay)
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return -1;
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delay = spi_delay_to_ns(_delay, dws);
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if (delay < 0)
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return delay;
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_spi_transfer_delay_ns(delay);
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return 0;
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}
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int poll_transfer(struct dw_spi *dws)
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{
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struct spi_delay delay;
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uint16_t nbits;
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delay.unit = SPI_DELAY_UNIT_SCK;
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nbits = dws->n_bytes * BITS_PER_BYTE;
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int ret = 0;
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do
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{
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dw_writer(dws);
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cpu_relax();
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delay.value = nbits * (dws->rx_len - dws->tx_len);
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spi_delay_exec(&delay, dws);
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dw_reader(dws);
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cpu_relax();
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ret = dw_spi_check_status(dws, true);
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if (ret)
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return ret;
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} while (dws->rx_len && dws->tx_len);
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return 0;
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}
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void set_tran_mode(struct dw_spi *dws)
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{
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uint32_t reg = dw_readl(dws, CVI_DW_SPI_CTRLR0);
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uint8_t tmode;
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if (dws->rx && dws->tx) {
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tmode = CVI_SPI_TMOD_TR;
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} else if (dws->rx) {
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tmode = CVI_SPI_TMOD_RO;
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} else {
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tmode = CVI_SPI_TMOD_TO;
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}
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reg &= ~CVI_SPI_TMOD_MASK;
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reg |= (tmode << CVI_SPI_TMOD_OFFSET);
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dw_writel(dws, CVI_DW_SPI_CTRLR0, reg);
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}
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void dw_spi_set_controller_mode(struct dw_spi *dws, uint8_t enable_master)
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{
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/* do not support to switch controller mode, it is default master mode */
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}
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void dw_spi_set_cs(struct dw_spi *dws, bool enable, uint32_t index)
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{
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uint32_t reg = dw_readl(dws, CVI_DW_SPI_SER);
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if (enable)
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dw_writel(dws, CVI_DW_SPI_SER, reg | BIT(index));
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else
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dw_writel(dws, CVI_DW_SPI_SER, reg & ~BIT(index));
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}
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void dw_spi_set_polarity_and_phase(struct dw_spi *dws, uint8_t format)
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{
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uint32_t reg = dw_readl(dws, CVI_DW_SPI_CTRLR0);
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reg &= ~(0x3 << 6);
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switch (format) {
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case SPI_FORMAT_CPOL0_CPHA0:
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reg |= (SPI_MODE_0 << 6);
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break;
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case SPI_FORMAT_CPOL0_CPHA1:
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reg |= (SPI_MODE_1 << 6);
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break;
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case SPI_FORMAT_CPOL1_CPHA0:
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reg |= (SPI_MODE_2 << 6);
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break;
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case SPI_FORMAT_CPOL1_CPHA1:
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reg |= (SPI_MODE_3 << 6);
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break;
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default:
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reg = dw_readl(dws, CVI_DW_SPI_CTRLR0);
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break;
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}
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SP_DEBUG_LOG("set phase and polarity: %#x\n", reg);
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dw_writel(dws, CVI_DW_SPI_CTRLR0, reg);
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}
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uint32_t dw_spi_set_clock(struct dw_spi *dws, uint32_t clock_in, uint32_t clock_out)
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{
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uint16_t div;
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div = (DIV_ROUND_UP(clock_in, clock_out) + 1) & 0xfffe;
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dws->speed_hz = clock_in / div;
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SP_DEBUG_LOG("clk div value is: %u, hz:%u\n", div, dws->speed_hz);
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spi_set_clk(dws, div);
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return dws->speed_hz;
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}
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int dw_spi_set_data_frame_len(struct dw_spi *dws, uint32_t size)
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{
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uint32_t temp = dw_readl(dws, CVI_DW_SPI_CTRLR0);
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temp &= ~0xf;
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if (size == 8) {
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dws->n_bytes = 1;
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} else if (size == 16) {
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dws->n_bytes = 2;
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} else {
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SP_DEBUG_LOG("do not support %u bit data!\n", size);
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return -1;
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}
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temp |= (size - 1);
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dw_writel(dws, CVI_DW_SPI_CTRLR0, temp);
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SP_DEBUG_LOG("set data frame len: %#x\n", temp);
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return 0;
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}
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void dw_spi_show_regs(struct dw_spi *dws)
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{
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SP_DEBUG_LOG("CTRLR0: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_CTRLR0));
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SP_DEBUG_LOG("CTRLR1: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_CTRLR1));
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SP_DEBUG_LOG("SSIENR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_SSIENR));
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SP_DEBUG_LOG("SER: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_SER));
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SP_DEBUG_LOG("BAUDR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_BAUDR));
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SP_DEBUG_LOG("TXFTLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_TXFTLR));
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SP_DEBUG_LOG("RXFTLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_RXFTLR));
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SP_DEBUG_LOG("TXFLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_TXFLR));
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SP_DEBUG_LOG("RXFLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_RXFLR));
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SP_DEBUG_LOG("SR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_SR));
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SP_DEBUG_LOG("IMR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_IMR));
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SP_DEBUG_LOG("ISR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_ISR));
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SP_DEBUG_LOG("DMACR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_DMACR));
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SP_DEBUG_LOG("DMATDLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_DMATDLR));
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SP_DEBUG_LOG("DMARDLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_DMARDLR));
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}
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