655 lines
16 KiB
C
655 lines
16 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-06 balanceTWK change to new framework
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*/
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#include <board.h>
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#include "drv_gpio.h"
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#ifdef RT_USING_PIN
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static const struct pin_index pins[] =
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{
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#ifdef GPIOA
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__STM32_PIN(0 , A, 0 ),
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__STM32_PIN(1 , A, 1 ),
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__STM32_PIN(2 , A, 2 ),
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__STM32_PIN(3 , A, 3 ),
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__STM32_PIN(4 , A, 4 ),
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__STM32_PIN(5 , A, 5 ),
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__STM32_PIN(6 , A, 6 ),
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__STM32_PIN(7 , A, 7 ),
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__STM32_PIN(8 , A, 8 ),
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__STM32_PIN(9 , A, 9 ),
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__STM32_PIN(10, A, 10),
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__STM32_PIN(11, A, 11),
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__STM32_PIN(12, A, 12),
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__STM32_PIN(13, A, 13),
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__STM32_PIN(14, A, 14),
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__STM32_PIN(15, A, 15),
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#endif
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#ifdef GPIOB
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__STM32_PIN(16, B, 0),
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__STM32_PIN(17, B, 1),
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__STM32_PIN(18, B, 2),
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__STM32_PIN(19, B, 3),
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__STM32_PIN(20, B, 4),
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__STM32_PIN(21, B, 5),
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__STM32_PIN(22, B, 6),
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__STM32_PIN(23, B, 7),
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__STM32_PIN(24, B, 8),
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__STM32_PIN(25, B, 9),
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__STM32_PIN(26, B, 10),
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__STM32_PIN(27, B, 11),
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__STM32_PIN(28, B, 12),
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__STM32_PIN(29, B, 13),
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__STM32_PIN(30, B, 14),
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__STM32_PIN(31, B, 15),
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#endif
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#ifdef GPIOC
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__STM32_PIN(32, C, 0),
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__STM32_PIN(33, C, 1),
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__STM32_PIN(34, C, 2),
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__STM32_PIN(35, C, 3),
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__STM32_PIN(36, C, 4),
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__STM32_PIN(37, C, 5),
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__STM32_PIN(38, C, 6),
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__STM32_PIN(39, C, 7),
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__STM32_PIN(40, C, 8),
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__STM32_PIN(41, C, 9),
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__STM32_PIN(42, C, 10),
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__STM32_PIN(43, C, 11),
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__STM32_PIN(44, C, 12),
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__STM32_PIN(45, C, 13),
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__STM32_PIN(46, C, 14),
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__STM32_PIN(47, C, 15),
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#endif
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#ifdef GPIOD
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__STM32_PIN(48, D, 0),
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__STM32_PIN(49, D, 1),
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__STM32_PIN(50, D, 2),
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__STM32_PIN(51, D, 3),
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__STM32_PIN(52, D, 4),
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__STM32_PIN(53, D, 5),
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__STM32_PIN(54, D, 6),
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__STM32_PIN(55, D, 7),
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__STM32_PIN(56, D, 8),
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__STM32_PIN(57, D, 9),
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__STM32_PIN(58, D, 10),
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__STM32_PIN(59, D, 11),
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__STM32_PIN(60, D, 12),
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__STM32_PIN(61, D, 13),
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__STM32_PIN(62, D, 14),
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__STM32_PIN(63, D, 15),
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#endif
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#ifdef GPIOE
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__STM32_PIN(64, E, 0),
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__STM32_PIN(65, E, 1),
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__STM32_PIN(66, E, 2),
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__STM32_PIN(67, E, 3),
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__STM32_PIN(68, E, 4),
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__STM32_PIN(69, E, 5),
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__STM32_PIN(70, E, 6),
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__STM32_PIN(71, E, 7),
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__STM32_PIN(72, E, 8),
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__STM32_PIN(73, E, 9),
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__STM32_PIN(74, E, 10),
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__STM32_PIN(75, E, 11),
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__STM32_PIN(76, E, 12),
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__STM32_PIN(77, E, 13),
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__STM32_PIN(78, E, 14),
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__STM32_PIN(79, E, 15),
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#endif
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#ifdef GPIOF
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__STM32_PIN(80, F, 0),
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__STM32_PIN(81, F, 1),
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__STM32_PIN(82, F, 2),
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__STM32_PIN(83, F, 3),
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__STM32_PIN(84, F, 4),
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__STM32_PIN(85, F, 5),
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__STM32_PIN(86, F, 6),
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__STM32_PIN(87, F, 7),
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__STM32_PIN(88, F, 8),
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__STM32_PIN(89, F, 9),
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__STM32_PIN(90, F, 10),
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__STM32_PIN(91, F, 11),
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__STM32_PIN(92, F, 12),
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__STM32_PIN(93, F, 13),
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__STM32_PIN(94, F, 14),
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__STM32_PIN(95, F, 15),
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#endif
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#ifdef GPIOG
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__STM32_PIN(96, G, 0),
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__STM32_PIN(97, G, 1),
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__STM32_PIN(98, G, 2),
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__STM32_PIN(99, G, 3),
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__STM32_PIN(100, G, 4),
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__STM32_PIN(101, G, 5),
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__STM32_PIN(102, G, 6),
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__STM32_PIN(103, G, 7),
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__STM32_PIN(104, G, 8),
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__STM32_PIN(105, G, 9),
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__STM32_PIN(106, G, 10),
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__STM32_PIN(107, G, 11),
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__STM32_PIN(108, G, 12),
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__STM32_PIN(109, G, 13),
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__STM32_PIN(110, G, 14),
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__STM32_PIN(111, G, 15),
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#endif
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#ifdef GPIOH
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__STM32_PIN(112, H, 0),
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__STM32_PIN(113, H, 1),
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__STM32_PIN(114, H, 2),
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__STM32_PIN(115, H, 3),
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__STM32_PIN(116, H, 4),
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__STM32_PIN(117, H, 5),
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__STM32_PIN(118, H, 6),
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__STM32_PIN(119, H, 7),
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__STM32_PIN(120, H, 8),
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__STM32_PIN(121, H, 9),
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__STM32_PIN(122, H, 10),
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__STM32_PIN(124, H, 11),
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__STM32_PIN(125, H, 12),
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__STM32_PIN(126, H, 13),
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__STM32_PIN(127, H, 14),
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__STM32_PIN(128, H, 15),
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#endif
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#ifdef GPIOI
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__STM32_PIN(129, I, 0),
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__STM32_PIN(130, I, 1),
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__STM32_PIN(131, I, 2),
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__STM32_PIN(132, I, 3),
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__STM32_PIN(133, I, 4),
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__STM32_PIN(134, I, 5),
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__STM32_PIN(135, I, 6),
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__STM32_PIN(136, I, 7),
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__STM32_PIN(137, I, 8),
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__STM32_PIN(138, I, 9),
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__STM32_PIN(139, I, 10),
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__STM32_PIN(140, I, 11),
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__STM32_PIN(141, I, 12),
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__STM32_PIN(142, I, 13),
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__STM32_PIN(143, I, 14),
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__STM32_PIN(144, I, 15),
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#endif
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#ifdef GPIOJ
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__STM32_PIN(145, J, 0),
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__STM32_PIN(146, J, 1),
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__STM32_PIN(147, J, 2),
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__STM32_PIN(148, J, 3),
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__STM32_PIN(149, J, 4),
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__STM32_PIN(150, J, 5),
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__STM32_PIN(151, J, 6),
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__STM32_PIN(152, J, 7),
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__STM32_PIN(153, J, 8),
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__STM32_PIN(154, J, 9),
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__STM32_PIN(155, J, 10),
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__STM32_PIN(156, J, 11),
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__STM32_PIN(157, J, 12),
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__STM32_PIN(158, J, 13),
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__STM32_PIN(159, J, 14),
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__STM32_PIN(160, J, 15),
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#endif
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#ifdef GPIOK
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__STM32_PIN(161, K, 0),
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__STM32_PIN(162, K, 1),
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__STM32_PIN(163, K, 2),
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__STM32_PIN(164, K, 3),
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__STM32_PIN(165, K, 4),
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__STM32_PIN(166, K, 5),
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__STM32_PIN(167, K, 6),
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__STM32_PIN(168, K, 7),
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__STM32_PIN(169, K, 8),
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__STM32_PIN(170, K, 9),
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__STM32_PIN(171, K, 10),
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__STM32_PIN(172, K, 11),
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__STM32_PIN(173, K, 12),
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__STM32_PIN(174, K, 13),
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__STM32_PIN(175, K, 14),
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__STM32_PIN(176, K, 15),
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#endif
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};
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static const struct pin_irq_map pin_irq_map[] =
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{
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{GPIO_PIN_0, EXTI0_IRQn},
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{GPIO_PIN_1, EXTI1_IRQn},
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{GPIO_PIN_2, EXTI2_IRQn},
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{GPIO_PIN_3, EXTI3_IRQn},
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{GPIO_PIN_4, EXTI4_IRQn},
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{GPIO_PIN_5, EXTI9_5_IRQn},
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{GPIO_PIN_6, EXTI9_5_IRQn},
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{GPIO_PIN_7, EXTI9_5_IRQn},
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{GPIO_PIN_8, EXTI9_5_IRQn},
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{GPIO_PIN_9, EXTI9_5_IRQn},
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{GPIO_PIN_10, EXTI15_10_IRQn},
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{GPIO_PIN_11, EXTI15_10_IRQn},
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{GPIO_PIN_12, EXTI15_10_IRQn},
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{GPIO_PIN_13, EXTI15_10_IRQn},
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{GPIO_PIN_14, EXTI15_10_IRQn},
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{GPIO_PIN_15, EXTI15_10_IRQn},
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};
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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static const struct pin_index *get_pin(uint8_t pin)
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{
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const struct pin_index *index;
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if (pin < ITEM_NUM(pins))
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{
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index = &pins[pin];
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if (index->index == -1)
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index = RT_NULL;
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}
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else
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{
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index = RT_NULL;
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}
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return index;
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};
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static void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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const struct pin_index *index;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value);
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}
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static int stm32_pin_read(rt_device_t dev, rt_base_t pin)
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{
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int value;
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const struct pin_index *index;
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value = PIN_LOW;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return value;
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}
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value = HAL_GPIO_ReadPin(index->gpio, index->pin);
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return value;
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}
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static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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const struct pin_index *index;
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GPIO_InitTypeDef GPIO_InitStruct;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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/* Configure GPIO_InitStructure */
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GPIO_InitStruct.Pin = index->pin;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_PULLUP;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_PULLDOWN;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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}
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HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
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}
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rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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{
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int i;
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for (i = 0; i < 32; i++)
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{
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if ((0x01 << i) == bit)
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{
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return i;
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}
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}
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return -1;
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
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{
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rt_int32_t mapindex = bit2bitno(pinbit);
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if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_NULL;
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}
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return &pin_irq_map[mapindex];
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};
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static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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irqindex = bit2bitno(index->pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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irqindex = bit2bitno(index->pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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const struct pin_index *index;
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const struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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GPIO_InitTypeDef GPIO_InitStruct;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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if (enabled == PIN_IRQ_ENABLE)
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{
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irqindex = bit2bitno(index->pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_ENOSYS;
|
|
}
|
|
|
|
irqmap = &pin_irq_map[irqindex];
|
|
|
|
/* Configure GPIO_InitStructure */
|
|
GPIO_InitStruct.Pin = index->pin;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
switch (pin_irq_hdr_tab[irqindex].mode)
|
|
{
|
|
case PIN_IRQ_MODE_RISING:
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
break;
|
|
case PIN_IRQ_MODE_FALLING:
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
|
break;
|
|
case PIN_IRQ_MODE_RISING_FALLING:
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
|
|
break;
|
|
}
|
|
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
|
|
|
|
HAL_NVIC_SetPriority(irqmap->irqno, 5, 0);
|
|
HAL_NVIC_EnableIRQ(irqmap->irqno);
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
}
|
|
else if (enabled == PIN_IRQ_DISABLE)
|
|
{
|
|
irqmap = get_pin_irq_map(index->pin);
|
|
if (irqmap == RT_NULL)
|
|
{
|
|
return RT_ENOSYS;
|
|
}
|
|
|
|
HAL_NVIC_DisableIRQ(irqmap->irqno);
|
|
}
|
|
else
|
|
{
|
|
return RT_ENOSYS;
|
|
}
|
|
|
|
return RT_EOK;
|
|
}
|
|
const static struct rt_pin_ops _stm32_pin_ops =
|
|
{
|
|
stm32_pin_mode,
|
|
stm32_pin_write,
|
|
stm32_pin_read,
|
|
stm32_pin_attach_irq,
|
|
stm32_pin_dettach_irq,
|
|
stm32_pin_irq_enable,
|
|
};
|
|
|
|
rt_inline void pin_irq_hdr(int irqno)
|
|
{
|
|
if (pin_irq_hdr_tab[irqno].hdr)
|
|
{
|
|
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
|
|
}
|
|
}
|
|
|
|
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
|
{
|
|
pin_irq_hdr(bit2bitno(GPIO_Pin));
|
|
}
|
|
|
|
void EXTI0_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI1_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI2_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI3_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI4_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI9_5_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI15_10_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
int rt_hw_pin_init(void)
|
|
{
|
|
#if defined(__HAL_RCC_GPIOA_CLK_ENABLE)
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
#endif
|
|
|
|
#if defined(__HAL_RCC_GPIOB_CLK_ENABLE)
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
#endif
|
|
|
|
#if defined(__HAL_RCC_GPIOC_CLK_ENABLE)
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
#endif
|
|
|
|
#if defined(__HAL_RCC_GPIOD_CLK_ENABLE)
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
#endif
|
|
|
|
#if defined(__HAL_RCC_GPIOE_CLK_ENABLE)
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
#endif
|
|
|
|
#if defined(__HAL_RCC_GPIOF_CLK_ENABLE)
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
#endif
|
|
|
|
#if defined(__HAL_RCC_GPIOG_CLK_ENABLE)
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
#endif
|
|
|
|
#if defined(__HAL_RCC_GPIOH_CLK_ENABLE)
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
#endif
|
|
|
|
#if defined(__HAL_RCC_GPIOI_CLK_ENABLE)
|
|
__HAL_RCC_GPIOI_CLK_ENABLE();
|
|
#endif
|
|
|
|
#if defined(__HAL_RCC_GPIOJ_CLK_ENABLE)
|
|
__HAL_RCC_GPIOJ_CLK_ENABLE();
|
|
#endif
|
|
|
|
return rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
|
|
}
|
|
|
|
#endif /* RT_USING_PIN */
|