237 lines
5.5 KiB
ArmAsm
237 lines
5.5 KiB
ArmAsm
;/*
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; * File : context_gcc.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * This program is free software; you can redistribute it and/or modify
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; * it under the terms of the GNU General Public License as published by
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; * the Free Software Foundation; either version 2 of the License, or
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; * (at your option) any later version.
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; *
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; * This program is distributed in the hope that it will be useful,
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; * but WITHOUT ANY WARRANTY; without even the implied warranty of
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; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; * GNU General Public License for more details.
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; *
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; * You should have received a copy of the GNU General Public License along
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; * with this program; if not, write to the Free Software Foundation, Inc.,
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; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2017-07-16 zhangjun for hifive1
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; */
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#include "encoding.h"
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#include "sifive/bits.h"
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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addi sp, sp, -12
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sw a5, (sp)
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li a5, 0x800
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csrr a0, mie
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blt a0, a5, 1f
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/* interrupt is enable before disable it*/
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addi a0, a0, 1
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li a5, 0x1
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addi a5, a5, -2048
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csrrc a5, mie, a5
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/* csrrc a5, mie, 128*/
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j 2f
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/* interrupt is disabled before disable it*/
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1:
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li a0, 0
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2:
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lw a5, (sp)
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addi sp, sp, 12
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ret
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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addi sp, sp, -12
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sw a5, (sp)
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beqz a0, 1f
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li a5, 0x1
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addi a5, a5, -2048
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csrrs a5, mie, a5
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/* csrrs a5, mie, 128*/
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1:
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lw a5, (sp)
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addi sp, sp, 12
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ret
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* a0 --> from
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* a1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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addi sp, sp, -32*REGBYTES
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STORE sp, (a0)
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STORE x30, 1*REGBYTES(sp)
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STORE x31, 2*REGBYTES(sp)
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STORE x3, 3*REGBYTES(sp)
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STORE x4, 4*REGBYTES(sp)
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STORE x5, 5*REGBYTES(sp)
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STORE x6, 6*REGBYTES(sp)
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STORE x7, 7*REGBYTES(sp)
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STORE x8, 8*REGBYTES(sp)
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STORE x9, 9*REGBYTES(sp)
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STORE x10, 10*REGBYTES(sp)
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STORE x11, 11*REGBYTES(sp)
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STORE x12, 12*REGBYTES(sp)
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STORE x13, 13*REGBYTES(sp)
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STORE x14, 14*REGBYTES(sp)
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STORE x15, 15*REGBYTES(sp)
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STORE x16, 16*REGBYTES(sp)
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STORE x17, 17*REGBYTES(sp)
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STORE x18, 18*REGBYTES(sp)
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STORE x19, 19*REGBYTES(sp)
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STORE x20, 20*REGBYTES(sp)
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STORE x21, 21*REGBYTES(sp)
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STORE x22, 22*REGBYTES(sp)
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STORE x23, 23*REGBYTES(sp)
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STORE x24, 24*REGBYTES(sp)
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STORE x25, 25*REGBYTES(sp)
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STORE x26, 26*REGBYTES(sp)
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STORE x27, 27*REGBYTES(sp)
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STORE x28, 28*REGBYTES(sp)
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STORE x10, 29*REGBYTES(sp)
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STORE x1, 30*REGBYTES(sp)
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STORE x1, 31*REGBYTES(sp)
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csrr x10, mie
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STORE x10, 0*REGBYTES(sp)
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/*
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*Remain in M-mode after mret
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*enable interrupt in M-mode
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*/
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li t0, 136
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csrrs t0, mstatus, t0
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LOAD sp, (a1)
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LOAD x30, 1*REGBYTES(sp)
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LOAD x31, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x29, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x10, 31*REGBYTES(sp)
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csrw mepc,x10
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LOAD x10, 0*REGBYTES(sp)
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csrw mie, x10
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LOAD x10, 29*REGBYTES(sp)
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LOAD x1, 30*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* a0 --> to
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LOAD sp, (a0)
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LOAD x30, 1*REGBYTES(sp)
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LOAD x31, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x29, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x10, 31*REGBYTES(sp)
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csrw mepc,a0
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LOAD x10, 29*REGBYTES(sp)
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LOAD x1, 30*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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/*
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* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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*/
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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addi sp, sp, -16
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sw s0, 12(sp)
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sw a0, 8(sp)
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sw a5, 4(sp)
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la a0, rt_thread_switch_interrupt_flag
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lw a5, (a0)
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bnez a5, _reswitch
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li a5, 1
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sw a5, (a0)
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la a5, rt_interrupt_from_thread
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lw a0, 8(sp)
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sw a0, (a5)
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_reswitch:
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la a5, rt_interrupt_to_thread
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sw a1, (a5)
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lw a5, 4(sp)
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lw a0, 8(sp)
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lw s0, 12(sp)
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addi sp, sp, 16
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ret
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