189 lines
4.9 KiB
C
189 lines
4.9 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2012-01-10 bernard porting to AM1808
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* 2019-07-28 zdzn add smp support
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*/
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#include "mmu.h"
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/* dump 2nd level page table */
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void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
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{
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int i;
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int fcnt = 0;
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for (i = 0; i < 256; i++)
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{
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rt_uint32_t pte2 = ptb[i];
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if ((pte2 & 0x3) == 0)
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{
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if (fcnt == 0)
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rt_kprintf(" ");
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rt_kprintf("%04x: ", i);
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fcnt++;
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if (fcnt == 16)
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{
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rt_kprintf("fault\n");
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fcnt = 0;
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}
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continue;
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}
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if (fcnt != 0)
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{
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rt_kprintf("fault\n");
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fcnt = 0;
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}
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rt_kprintf(" %04x: %x: ", i, pte2);
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if ((pte2 & 0x3) == 0x1)
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{
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rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
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((pte2 >> 7) | (pte2 >> 4))& 0xf,
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(pte2 >> 15) & 0x1,
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((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
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}
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else
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{
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rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
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((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
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((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
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}
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}
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}
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void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
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{
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int i;
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int fcnt = 0;
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rt_kprintf("page table@%p\n", ptb);
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for (i = 0; i < 1024*4; i++)
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{
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rt_uint32_t pte1 = ptb[i];
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if ((pte1 & 0x3) == 0)
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{
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rt_kprintf("%03x: ", i);
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fcnt++;
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if (fcnt == 16)
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{
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rt_kprintf("fault\n");
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fcnt = 0;
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}
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continue;
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}
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if (fcnt != 0)
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{
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rt_kprintf("fault\n");
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fcnt = 0;
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}
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rt_kprintf("%03x: %08x: ", i, pte1);
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if ((pte1 & 0x3) == 0x3)
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{
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rt_kprintf("LPAE\n");
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}
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else if ((pte1 & 0x3) == 0x1)
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{
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rt_kprintf("pte,ns:%d,domain:%d\n",
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(pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
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/*
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*rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
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* - 0x80000000 + 0xC0000000));
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*/
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}
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else if (pte1 & (1 << 18))
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{
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rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
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(pte1 >> 19) & 0x1,
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((pte1 >> 13) | (pte1 >> 10))& 0xf,
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(pte1 >> 4) & 0x1,
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((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
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}
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else
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{
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rt_kprintf("section,ns:%d,ap:%x,"
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"xn:%d,texcb:%02x,domain:%d\n",
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(pte1 >> 19) & 0x1,
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((pte1 >> 13) | (pte1 >> 10))& 0xf,
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(pte1 >> 4) & 0x1,
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(((pte1 & (0x7 << 12)) >> 10) |
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((pte1 & 0x0c) >> 2)) & 0x1f,
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(pte1 >> 5) & 0xf);
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}
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}
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}
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/* level1 page table, each entry for 1MB memory. */
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volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
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void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
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rt_uint32_t vaddrEnd,
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rt_uint32_t paddrStart,
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rt_uint32_t attr)
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{
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volatile rt_uint32_t *pTT;
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volatile int i, nSec;
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pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
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nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
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for (i = 0; i <= nSec; i++)
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{
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*pTT = attr | (((paddrStart >> 20) + i) << 20);
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pTT++;
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}
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}
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unsigned long rt_hw_set_domain_register(unsigned long domain_val)
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{
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unsigned long old_domain;
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asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
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asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
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return old_domain;
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}
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void rt_hw_init_mmu_table()
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{
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/* set page table */
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/* 4G 1:1 memory */
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rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
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/* IO memory region */
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rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
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}
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void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
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rt_uint32_t size,
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rt_uint32_t paddrStart, rt_uint32_t attr)
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{
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rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
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#ifndef RT_USING_SMP
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rt_cpu_dcache_clean_flush();
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rt_cpu_icache_flush();
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#endif
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}
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void rt_hw_mmu_init(void)
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{
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rt_cpu_dcache_clean_flush();
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rt_cpu_icache_flush();
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rt_hw_cpu_dcache_disable();
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rt_hw_cpu_icache_disable();
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rt_cpu_mmu_disable();
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/*rt_hw_cpu_dump_page_table(MMUTable);*/
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rt_hw_set_domain_register(0x55555555);
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rt_cpu_tlb_set(MMUTable);
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rt_cpu_mmu_enable();
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rt_hw_cpu_icache_enable();
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rt_hw_cpu_dcache_enable();
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}
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