281 lines
6.3 KiB
C
281 lines
6.3 KiB
C
/*
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* File : mips_context_asm.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2016Äê9ÔÂ7ÈÕ Urey the first version
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*/
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#ifndef _MIPS_CONTEXT_ASM_H_
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#define _MIPS_CONTEXT_ASM_H_
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#define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ )
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#ifdef __mips_hard_float
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#define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */
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#define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ )
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#else
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#define FPU_ADJ 0
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#endif
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#ifdef __ASSEMBLY__
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#ifdef __mips_hard_float
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.global _fpctx_save
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.global _fpctx_load
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#endif
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.macro SAVE_CONTEXT
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.set push
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.set noat
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.set noreorder
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.set volatile
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//save SP
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move k1, sp
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move k0, sp
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subu sp, k1, CONTEXT_SIZE
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sw k0, (29 * 4)(sp)
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//save REG
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sw $0, ( 0 * 4)(sp)
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sw $1, ( 1 * 4)(sp)
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sw $2, ( 2 * 4)(sp)
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sw $3, ( 3 * 4)(sp)
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sw $4, ( 4 * 4)(sp)
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sw $5, ( 5 * 4)(sp)
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sw $6, ( 6 * 4)(sp)
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sw $7, ( 7 * 4)(sp)
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sw $8, ( 8 * 4)(sp)
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sw $9, ( 9 * 4)(sp)
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sw $10, (10 * 4)(sp)
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sw $11, (11 * 4)(sp)
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sw $12, (12 * 4)(sp)
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sw $13, (13 * 4)(sp)
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sw $14, (14 * 4)(sp)
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sw $15, (15 * 4)(sp)
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sw $16, (16 * 4)(sp)
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sw $17, (17 * 4)(sp)
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sw $18, (18 * 4)(sp)
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sw $19, (19 * 4)(sp)
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sw $20, (20 * 4)(sp)
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sw $21, (21 * 4)(sp)
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sw $22, (22 * 4)(sp)
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sw $23, (23 * 4)(sp)
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sw $24, (24 * 4)(sp)
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sw $25, (25 * 4)(sp)
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/* K0 K1 */
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sw $28, (28 * 4)(sp)
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/* SP */
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sw $30, (30 * 4)(sp)
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sw $31, (31 * 4)(sp)
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/* STATUS CAUSE EPC.... */
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mfc0 $2, CP0_STATUS
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sw $2, STK_OFFSET_SR(sp)
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mfc0 $2, CP0_CAUSE
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sw $2, STK_OFFSET_CAUSE(sp)
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mfc0 $2, CP0_BADVADDR
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sw $2, STK_OFFSET_BADVADDR(sp)
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MFC0 $2, CP0_EPC
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sw $2, STK_OFFSET_EPC(sp)
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mfhi $2
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sw $2, STK_OFFSET_HI(sp)
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mflo $2
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sw $2, STK_OFFSET_LO(sp)
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#ifdef __mips_hard_float
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add a0, sp,STK_CTX_SIZE
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mfc0 t0, CP0_STATUS
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.set push
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.set at
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or t0, M_StatusCU1
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.set push
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mtc0 t0, CP0_STATUS
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cfc1 t0, CP1_STATUS
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sw t0 , 0x00(a0)
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swc1 $f0,(0x04 * 1)(a0)
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swc1 $f1,(0x04 * 2)(a0)
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swc1 $f2,(0x04 * 3)(a0)
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swc1 $f3,(0x04 * 4)(a0)
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swc1 $f4,(0x04 * 5)(a0)
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swc1 $f5,(0x04 * 6)(a0)
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swc1 $f6,(0x04 * 7)(a0)
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swc1 $f7,(0x04 * 8)(a0)
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swc1 $f8,(0x04 * 9)(a0)
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swc1 $f9,(0x04 * 10)(a0)
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swc1 $f10,(0x04 * 11)(a0)
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swc1 $f11,(0x04 * 12)(a0)
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swc1 $f12,(0x04 * 13)(a0)
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swc1 $f13,(0x04 * 14)(a0)
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swc1 $f14,(0x04 * 15)(a0)
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swc1 $f15,(0x04 * 16)(a0)
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swc1 $f16,(0x04 * 17)(a0)
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swc1 $f17,(0x04 * 18)(a0)
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swc1 $f18,(0x04 * 19)(a0)
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swc1 $f19,(0x04 * 20)(a0)
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swc1 $f20,(0x04 * 21)(a0)
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swc1 $f21,(0x04 * 22)(a0)
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swc1 $f22,(0x04 * 23)(a0)
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swc1 $f23,(0x04 * 24)(a0)
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swc1 $f24,(0x04 * 25)(a0)
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swc1 $f25,(0x04 * 26)(a0)
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swc1 $f26,(0x04 * 27)(a0)
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swc1 $f27,(0x04 * 28)(a0)
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swc1 $f28,(0x04 * 29)(a0)
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swc1 $f29,(0x04 * 30)(a0)
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swc1 $f30,(0x04 * 31)(a0)
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swc1 $f31,(0x04 * 32)(a0)
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nop
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#endif
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//restore a0
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lw a0, (REG_A0 * 4)(sp)
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.set pop
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.endm
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.macro RESTORE_CONTEXT
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.set push
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.set noat
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.set noreorder
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.set volatile
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#ifdef __mips_hard_float
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add a0, sp,STK_CTX_SIZE
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mfc0 t0, CP0_STATUS
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.set push
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.set at
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or t0, M_StatusCU1
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.set noat
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mtc0 t0, CP0_STATUS
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lw t0 , 0x00(a0)
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lwc1 $f0,(0x04 * 1)(a0)
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lwc1 $f1,(0x04 * 2)(a0)
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lwc1 $f2,(0x04 * 3)(a0)
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lwc1 $f3,(0x04 * 4)(a0)
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lwc1 $f4,(0x04 * 5)(a0)
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lwc1 $f5,(0x04 * 6)(a0)
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lwc1 $f6,(0x04 * 7)(a0)
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lwc1 $f7,(0x04 * 8)(a0)
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lwc1 $f8,(0x04 * 9)(a0)
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lwc1 $f9,(0x04 * 10)(a0)
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lwc1 $f10,(0x04 * 11)(a0)
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lwc1 $f11,(0x04 * 12)(a0)
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lwc1 $f12,(0x04 * 13)(a0)
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lwc1 $f13,(0x04 * 14)(a0)
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lwc1 $f14,(0x04 * 15)(a0)
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lwc1 $f15,(0x04 * 16)(a0)
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lwc1 $f16,(0x04 * 17)(a0)
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lwc1 $f17,(0x04 * 18)(a0)
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lwc1 $f18,(0x04 * 19)(a0)
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lwc1 $f19,(0x04 * 20)(a0)
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lwc1 $f20,(0x04 * 21)(a0)
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lwc1 $f21,(0x04 * 22)(a0)
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lwc1 $f22,(0x04 * 23)(a0)
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lwc1 $f23,(0x04 * 24)(a0)
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lwc1 $f24,(0x04 * 25)(a0)
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lwc1 $f25,(0x04 * 26)(a0)
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lwc1 $f26,(0x04 * 27)(a0)
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lwc1 $f27,(0x04 * 28)(a0)
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lwc1 $f28,(0x04 * 29)(a0)
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lwc1 $f29,(0x04 * 30)(a0)
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lwc1 $f30,(0x04 * 31)(a0)
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lwc1 $f31,(0x04 * 32)(a0)
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ctc1 t0, CP1_STATUS ;/* restore fpp status reg */
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nop
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#endif
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/* ͨÓüĴæÆ÷ */
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/* ZERO */
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lw $1, ( 1 * 4)(sp)
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/* V0 */
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lw $3, ( 3 * 4)(sp)
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lw $4, ( 4 * 4)(sp)
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lw $5, ( 5 * 4)(sp)
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lw $6, ( 6 * 4)(sp)
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lw $7, ( 7 * 4)(sp)
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lw $8, ( 8 * 4)(sp)
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lw $9, ( 9 * 4)(sp)
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lw $10, (10 * 4)(sp)
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lw $11, (11 * 4)(sp)
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lw $12, (12 * 4)(sp)
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lw $13, (13 * 4)(sp)
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lw $14, (14 * 4)(sp)
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lw $15, (15 * 4)(sp)
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lw $16, (16 * 4)(sp)
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lw $17, (17 * 4)(sp)
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lw $18, (18 * 4)(sp)
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lw $19, (19 * 4)(sp)
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lw $20, (20 * 4)(sp)
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lw $21, (21 * 4)(sp)
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lw $22, (22 * 4)(sp)
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lw $23, (23 * 4)(sp)
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lw $24, (24 * 4)(sp)
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lw $25, (25 * 4)(sp)
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lw $26, (26 * 4)(sp)
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lw $27, (27 * 4)(sp)
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lw $28, (28 * 4)(sp)
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/* SP */
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lw $30, (30 * 4)(sp)
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lw $31, (31 * 4)(sp)
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/* STATUS CAUSE EPC.... */
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lw $2, STK_OFFSET_HI(sp)
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mthi $2
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lw $2, STK_OFFSET_LO(sp)
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mtlo $2
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lw $2, STK_OFFSET_SR(sp)
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mtc0 $2, CP0_STATUS
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lw $2, STK_OFFSET_BADVADDR(sp)
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mtc0 $2, CP0_BADVADDR
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lw $2, STK_OFFSET_CAUSE(sp)
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mtc0 $2, CP0_CAUSE
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lw $2, STK_OFFSET_EPC(sp)
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MTC0 $2, CP0_EPC
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//restore $2
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lw $2, ( 2 * 4)(sp)
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//restore sp
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lw $29, (29 * 4)(sp)
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eret
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nop
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.set pop
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.endm
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#endif
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#endif /* _MIPS_CONTEXT_ASM_H_ */
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