252 lines
11 KiB
C
252 lines
11 KiB
C
/*
|
|
** ###################################################################
|
|
** Processors: MK64FN1M0CAJ12
|
|
** MK64FN1M0VDC12
|
|
** MK64FN1M0VLL12
|
|
** MK64FN1M0VLQ12
|
|
** MK64FN1M0VMD12
|
|
** MK64FX512VDC12
|
|
** MK64FX512VLL12
|
|
** MK64FX512VLQ12
|
|
** MK64FX512VMD12
|
|
**
|
|
** Compilers: Keil ARM C/C++ Compiler
|
|
** Freescale C/C++ for Embedded ARM
|
|
** GNU C Compiler
|
|
** IAR ANSI C/C++ Compiler for ARM
|
|
** MCUXpresso Compiler
|
|
**
|
|
** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
|
|
** Version: rev. 2.9, 2016-03-21
|
|
** Build: b170112
|
|
**
|
|
** Abstract:
|
|
** Provides a system configuration function and a global variable that
|
|
** contains the system frequency. It configures the device and initializes
|
|
** the oscillator (PLL) that is part of the microcontroller device.
|
|
**
|
|
** Copyright (c) 2016 Freescale Semiconductor, Inc.
|
|
** Copyright 2016 - 2017 NXP
|
|
** Redistribution and use in source and binary forms, with or without modification,
|
|
** are permitted provided that the following conditions are met:
|
|
**
|
|
** o Redistributions of source code must retain the above copyright notice, this list
|
|
** of conditions and the following disclaimer.
|
|
**
|
|
** o Redistributions in binary form must reproduce the above copyright notice, this
|
|
** list of conditions and the following disclaimer in the documentation and/or
|
|
** other materials provided with the distribution.
|
|
**
|
|
** o Neither the name of the copyright holder nor the names of its
|
|
** contributors may be used to endorse or promote products derived from this
|
|
** software without specific prior written permission.
|
|
**
|
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
|
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
**
|
|
** http: www.nxp.com
|
|
** mail: support@nxp.com
|
|
**
|
|
** Revisions:
|
|
** - rev. 1.0 (2013-08-12)
|
|
** Initial version.
|
|
** - rev. 2.0 (2013-10-29)
|
|
** Register accessor macros added to the memory map.
|
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
|
** System initialization updated.
|
|
** MCG - registers updated.
|
|
** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
|
|
** - rev. 2.1 (2013-10-30)
|
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
|
** - rev. 2.2 (2013-12-09)
|
|
** DMA - EARS register removed.
|
|
** AIPS0, AIPS1 - MPRA register updated.
|
|
** - rev. 2.3 (2014-01-24)
|
|
** Update according to reference manual rev. 2
|
|
** ENET, MCG, MCM, SIM, USB - registers updated
|
|
** - rev. 2.4 (2014-02-10)
|
|
** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
|
|
** Update of SystemInit() and SystemCoreClockUpdate() functions.
|
|
** - rev. 2.5 (2014-02-10)
|
|
** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
|
|
** Update of SystemInit() and SystemCoreClockUpdate() functions.
|
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
|
** - rev. 2.6 (2014-08-28)
|
|
** Update of system files - default clock configuration changed.
|
|
** Update of startup files - possibility to override DefaultISR added.
|
|
** - rev. 2.7 (2014-10-14)
|
|
** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
|
|
** - rev. 2.8 (2015-02-19)
|
|
** Renamed interrupt vector LLW to LLWU.
|
|
** - rev. 2.9 (2016-03-21)
|
|
** Added MK64FN1M0CAJ12 part.
|
|
** GPIO - renamed port instances: PTx -> GPIOx.
|
|
**
|
|
** ###################################################################
|
|
*/
|
|
|
|
/*!
|
|
* @file MK64F12
|
|
* @version 2.9
|
|
* @date 2016-03-21
|
|
* @brief Device specific configuration file for MK64F12 (implementation file)
|
|
*
|
|
* Provides a system configuration function and a global variable that contains
|
|
* the system frequency. It configures the device and initializes the oscillator
|
|
* (PLL) that is part of the microcontroller device.
|
|
*/
|
|
|
|
#include <stdint.h>
|
|
#include "fsl_device_registers.h"
|
|
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- Core clock
|
|
---------------------------------------------------------------------------- */
|
|
|
|
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SystemInit()
|
|
---------------------------------------------------------------------------- */
|
|
|
|
void SystemInit (void) {
|
|
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
|
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
|
|
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
|
#if (DISABLE_WDOG)
|
|
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
|
|
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
|
|
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
|
|
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
|
|
/* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
|
|
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
|
|
WDOG_STCTRLH_WAITEN_MASK |
|
|
WDOG_STCTRLH_STOPEN_MASK |
|
|
WDOG_STCTRLH_ALLOWUPDATE_MASK |
|
|
WDOG_STCTRLH_CLKSRC_MASK |
|
|
0x0100U;
|
|
#endif /* (DISABLE_WDOG) */
|
|
|
|
}
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SystemCoreClockUpdate()
|
|
---------------------------------------------------------------------------- */
|
|
|
|
void SystemCoreClockUpdate (void) {
|
|
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
|
|
uint16_t Divider;
|
|
|
|
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
|
|
/* Output of FLL or PLL is selected */
|
|
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
|
|
/* FLL is selected */
|
|
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
|
|
/* External reference clock is selected */
|
|
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
|
|
case 0x00U:
|
|
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
|
break;
|
|
case 0x01U:
|
|
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
|
break;
|
|
case 0x02U:
|
|
default:
|
|
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
|
|
break;
|
|
}
|
|
if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
|
|
switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
|
|
case 0x38U:
|
|
Divider = 1536U;
|
|
break;
|
|
case 0x30U:
|
|
Divider = 1280U;
|
|
break;
|
|
default:
|
|
Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
|
break;
|
|
}
|
|
} else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
|
|
Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
|
}
|
|
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
|
|
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
|
|
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
|
|
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
|
|
/* Select correct multiplier to calculate the MCG output clock */
|
|
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
|
|
case 0x00U:
|
|
MCGOUTClock *= 640U;
|
|
break;
|
|
case 0x20U:
|
|
MCGOUTClock *= 1280U;
|
|
break;
|
|
case 0x40U:
|
|
MCGOUTClock *= 1920U;
|
|
break;
|
|
case 0x60U:
|
|
MCGOUTClock *= 2560U;
|
|
break;
|
|
case 0x80U:
|
|
MCGOUTClock *= 732U;
|
|
break;
|
|
case 0xA0U:
|
|
MCGOUTClock *= 1464U;
|
|
break;
|
|
case 0xC0U:
|
|
MCGOUTClock *= 2197U;
|
|
break;
|
|
case 0xE0U:
|
|
MCGOUTClock *= 2929U;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
|
|
/* PLL is selected */
|
|
Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
|
|
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
|
|
Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
|
|
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
|
|
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
|
|
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
|
|
/* Internal reference clock is selected */
|
|
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
|
|
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
|
|
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
|
|
Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
|
|
MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
|
|
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
|
|
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
|
|
/* External reference clock is selected */
|
|
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
|
|
case 0x00U:
|
|
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
|
break;
|
|
case 0x01U:
|
|
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
|
break;
|
|
case 0x02U:
|
|
default:
|
|
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
|
|
break;
|
|
}
|
|
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
|
|
/* Reserved value */
|
|
return;
|
|
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
|
|
SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
|
}
|