699 lines
18 KiB
C
699 lines
18 KiB
C
/**
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*
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* \file
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*
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* \brief SAM Segment Liquid Crystal Display(SLCD) Controller.
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*
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* This file defines a useful set of functions for the SLCD on SAM devices.
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*
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* Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include <slcd.h>
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#include <conf_slcd.h>
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#include <system.h>
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#if !defined(CONF_SLCD_CLOCK_SOURCE)
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# warning SLCD_CLOCK_SOURCE is not defined, assuming 0.
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# define CONF_SLCD_CLOCK_SOURCE 0
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#endif
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#if !defined(CONF_SLCD_DUTY)
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# warning CONF_SLCD_DUTY is not defined, assuming 0.
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# define CONF_SLCD_DUTY 0
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#endif
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#if !defined(CONF_SLCD_BIAS)
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# warning CONF_SLCD_BIAS is not defined, assuming 0.
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# define CONF_SLCD_BIAS 0
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#endif
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#if !defined(CONF_SLCD_PVAL)
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# warning CONF_SLCD_PVAL is not defined, assuming 0.
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# define CONF_SLCD_PVAL 0
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#endif
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#if !defined(CONF_SLCD_CKDIV)
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# warning CONF_SLCD_CKDIV is not defined, assuming 0.
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# define CONF_SLCD_CKDIV 0
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#endif
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#if !defined(CONF_SLCD_VLCD_SEL)
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# warning CONF_SLCD_VLCD_SEL is not defined, assuming 0.
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# define CONF_SLCD_VLCD_SEL 0
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#endif
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#if !defined(CONF_SLCD_REF_REFRESH_FREQ)
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# warning CONF_SLCD_REF_REFRESH_FREQ is not defined, assuming 0.
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# define CONF_SLCD_REF_REFRESH_FREQ 0
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#endif
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#if !defined(CONF_SLCD_POWER_REFRESH_FREQ)
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# warning CONF_SLCD_POWER_REFRESH_FREQ is not defined, assuming 0.
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# define CONF_SLCD_POWER_REFRESH_FREQ 0
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#endif
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#if !defined(CONF_SLCD_POWER_MODE)
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# warning CONF_SLCD_POWER_MODE is not defined, assuming 0.
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# define CONF_SLCD_POWER_MODE 0
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#endif
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#if !defined(CONF_SLCD_PIN_L_MASK)
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# warning CONF_SLCD_PIN_L_MASK is not defined, assuming 0.
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# define CONF_SLCD_PIN_L_MASK 0
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#endif
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#if !defined(CONF_SLCD_PIN_H_MASK)
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# warning CONF_SLCD_PIN_H_MASK is not defined, assuming 0.
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# define CONF_SLCD_PIN_H_MASK 0
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#endif
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/**
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* \brief Initializes SLCD configurations struct to defaults
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*
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* Initailizes SLCD configuration struct to predefined safe default settings.
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*
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* \param[in] config Pointer to an instance of \ref struct slcd_config
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*
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*/
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void slcd_get_config_defaults(struct slcd_config *config)
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{
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Assert(config);
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config->run_in_standby = false;
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config->waveform_mode = SLCD_LOW_POWER_WAVEFORM_MODE;
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config->low_resistance_duration = 0;
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config->enable_low_resistance = false;
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config->bias_buffer_duration = 0;
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config->enable_bias_buffer = false;
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}
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/**
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* \brief Initialize SLCD module
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*
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* \param[in] config Pointer to an SLCD configuration structure
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*
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* \note SLCD cannot be Initialized while it is enabled.
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*
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* \return Status of the configuration procedure.
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* \retval STATUS_OK SLCD configuration went successful
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* \retval STATUS_ERR_INVALID_ARG If an invalid configuration was supplied
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*/
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enum status_code slcd_init(struct slcd_config *const config)
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{
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if (!config) {
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return STATUS_ERR_INVALID_ARG;
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}
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system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_SLCD);
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/* Select SLCD clock */
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OSC32KCTRL->SLCDCTRL.reg = CONF_SLCD_CLOCK_SOURCE & OSC32KCTRL_SLCDCTRL_MASK;
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slcd_disable();
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slcd_reset();
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SLCD->CTRLA.reg = SLCD_CTRLA_DUTY(CONF_SLCD_DUTY) | SLCD_CTRLA_BIAS(CONF_SLCD_BIAS)
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| SLCD_CTRLA_PRESC(CONF_SLCD_PVAL) | SLCD_CTRLA_CKDIV(CONF_SLCD_CKDIV)
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| (CONF_SLCD_VLCD_SEL << SLCD_CTRLA_XVLCD_Pos)
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| (config->run_in_standby << SLCD_CTRLA_RUNSTDBY_Pos)
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| SLCD_CTRLA_RRF(CONF_SLCD_REF_REFRESH_FREQ)
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| SLCD_CTRLA_PRF(CONF_SLCD_POWER_REFRESH_FREQ)
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| (config->waveform_mode << SLCD_CTRLA_WMOD_Pos);
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SLCD->CTRLB.reg = SLCD_CTRLB_BBD(config->bias_buffer_duration)
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| (config->enable_bias_buffer << SLCD_CTRLB_BBEN_Pos)
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| SLCD_CTRLB_LRD(config->low_resistance_duration)
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| (config->enable_low_resistance << SLCD_CTRLB_LREN_Pos);
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SLCD->CTRLC.reg |= SLCD_CTRLC_LPPM(CONF_SLCD_POWER_MODE) | SLCD_CTRLC_CTST(0x0F);
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SLCD->LPENL.reg = CONF_SLCD_PIN_L_MASK & SLCD_LPENL_MASK;
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SLCD->LPENH.reg = CONF_SLCD_PIN_H_MASK & SLCD_LPENH_MASK;
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return STATUS_OK;
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}
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/**
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* \brief Enables the SLCD module
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*
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* Enables the SLCD module once it has been configured, ready for use. Most
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* module configuration parameters cannot be altered while the module is enabled.
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*/
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void slcd_enable(void)
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{
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SLCD->CTRLA.reg |= SLCD_CTRLA_ENABLE;
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while (slcd_is_syncing()) {
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/* Wait for synchronization */
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}
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while (!slcd_get_vlcd_ready_status()) {
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}
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}
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/**
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* \brief Disables the SLCD module
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*
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* Disables the SLCD module.
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*/
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void slcd_disable(void)
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{
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SLCD->INTENCLR.reg = SLCD_INTENCLR_MASK;
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SLCD->INTFLAG.reg = SLCD_INTFLAG_MASK;
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SLCD->CTRLA.reg &= ~(SLCD_CTRLA_ENABLE);
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while (slcd_is_syncing()) {
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/* Wait for synchronization */
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}
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}
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/**
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* \brief Check if SLCD module is enabled or not
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*
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* Check if SLCD module is enabled or not.
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*
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* \return Enable status.
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* \retval true SLCD module is enabled
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* \retval false SLCD module is disabled
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*/
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bool slcd_is_enabled(void)
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{
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return ((SLCD->CTRLA.reg & SLCD_CTRLA_ENABLE) == SLCD_CTRLA_ENABLE);
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}
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/**
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* \brief Reset the SLCD module
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*
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* Reset the SLCD module.
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*/
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void slcd_reset(void)
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{
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slcd_disable();
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SLCD->CTRLA.reg |= SLCD_CTRLA_SWRST;
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while (slcd_is_syncing()) {
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/* Wait for synchronization */
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}
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}
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/**
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* \brief Set the SLCD fine contrast
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*
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* The LCD contrast is defined by the value of VLCD voltage. The higher is the
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* VLCD voltage, the higher is the contrast. The software contrast adjustment
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* is only possible in internal supply mode.
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* In internal supply mode, VLCD is in the range 2.5V to 3.5V. VLCD can be
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* adjusted with 16 steps, each step is 60 mV.The contrast value can be written
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* at any time.
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*
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* \param[in] contrast Contrast value
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*
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* \return Status of set contrast.
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* \retval STATUS_OK SLCD contrast set successful
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* \retval STATUS_ERR_INVALID_ARG SLCD is not working in internal supply mode
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*/
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enum status_code slcd_set_contrast(uint8_t contrast)
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{
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if (SLCD->CTRLA.bit.XVLCD) {
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return STATUS_ERR_INVALID_ARG;
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}
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uint16_t temp = SLCD->CTRLC.reg;
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temp &= ~ SLCD_CTRLC_CTST(0xf);
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temp |= SLCD_CTRLC_CTST(contrast);
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SLCD->CTRLC.reg = temp;
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return STATUS_OK;
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}
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/**
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* \brief Initializes SLCD blink configurations struct to defaults
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*
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* Initailizes SLCD blink configuration struct to predefined safe default settings.
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*
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* \param[in] config Pointer to an instance of \ref struct slcd_blink_config
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*
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*/
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void slcd_blink_get_config_defaults(struct slcd_blink_config *blink_config)
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{
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Assert(blink_config);
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blink_config->fc = SLCD_FRAME_COUNTER_0;
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blink_config->blink_all_seg = true;
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}
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/**
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* \brief Set SLCD blink mode
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*
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* Set SLCD blink mode.
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*
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* \note SLCD blink cannot be set while module or blink is enabled.
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*
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* \param[in] config Pointer to an SLCD blink configuration structure
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*
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* \return Status of the configuration procedure.
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* \retval STATUS_OK SLCD blink configuration went successful
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* \retval STATUS_ERR_INVALID_ARG If blink configuration failed
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*/
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enum status_code slcd_blink_set_config(struct slcd_blink_config *const blink_config)
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{
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if (!blink_config) {
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return STATUS_ERR_INVALID_ARG;
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}
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SLCD->BCFG.bit.MODE = (!(blink_config->blink_all_seg) << SLCD_BCFG_MODE_Pos);
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SLCD->BCFG.bit.FCS = SLCD_BCFG_FCS(blink_config->fc);
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return STATUS_OK;
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}
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/**
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* \brief Start an SLCD pixel/segment blinking
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*
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* \param[in] pix_com Pixel/segment COM coordinate
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* \param[in] pix_seg Pixel/segment SEG coordinate (range 0 to 1 inclusive)
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*/
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void slcd_set_blink_pixel(
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uint8_t pix_com,
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uint8_t pix_seg)
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{
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/* Validate parameters. */
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Assert(pix_seg<=1);
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if (pix_seg == 0) {
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SLCD->BCFG.reg |= SLCD_BCFG_BSS0(1 << pix_com);
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}
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if (pix_seg == 1) {
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SLCD->BCFG.reg |= SLCD_BCFG_BSS1(1 << pix_com);
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}
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}
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/**
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* \brief Stop a specified SLCD pixel/segment from blinking
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*
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* \param[in] pix_com Pixel/segment COM coordinate
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* \param[in] pix_seg Pixel/segment SEG coordinate (range 0 to 1 inclusive)
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*/
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void slcd_clear_blink_pixel(
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uint8_t pix_com,
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uint8_t pix_seg)
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{
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/* Validate parameters. */
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Assert(pix_seg<=1);
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if (pix_seg == 0) {
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SLCD->BCFG.reg &= ~ SLCD_BCFG_BSS0(1 << pix_com);
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}
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if (pix_seg == 1) {
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SLCD->BCFG.reg &= ~ SLCD_BCFG_BSS1(1 << pix_com);
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}
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}
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/**
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* \brief Stop all SLCD pixels/segments from blinking
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*/
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void slcd_clear_blink_all_pixel(void)
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{
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SLCD->BCFG.bit.BSS0 = 0;
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SLCD->BCFG.bit.BSS1 = 0;
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}
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/**
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* \brief Set all bits in the SLCD display memory high
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*/
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void slcd_set_display_memory(void)
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{
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SLCD->SDATAH0.reg = SLCD_SDATAH0_MASK;
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SLCD->SDATAL0.reg = SLCD_SDATAL0_MASK;
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SLCD->SDATAH1.reg = SLCD_SDATAH1_MASK;
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SLCD->SDATAL1.reg = SLCD_SDATAL1_MASK;
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SLCD->SDATAH2.reg = SLCD_SDATAH2_MASK;
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SLCD->SDATAL2.reg = SLCD_SDATAL2_MASK;
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SLCD->SDATAH3.reg = SLCD_SDATAH3_MASK;
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SLCD->SDATAL3.reg = SLCD_SDATAL3_MASK;
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SLCD->SDATAH4.reg = SLCD_SDATAH4_MASK;
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SLCD->SDATAL4.reg = SLCD_SDATAL4_MASK;
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SLCD->SDATAH5.reg = SLCD_SDATAH5_MASK;
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SLCD->SDATAL5.reg = SLCD_SDATAL5_MASK;
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SLCD->SDATAH6.reg = SLCD_SDATAH6_MASK;
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SLCD->SDATAL6.reg = SLCD_SDATAL6_MASK;
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SLCD->SDATAH7.reg = SLCD_SDATAH7_MASK;
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SLCD->SDATAL7.reg = SLCD_SDATAL7_MASK;
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}
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/**
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* \brief Enable the specified pixel/segment in the SLCD display memory
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*
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* \param[in] pix_com Pixel/segment COM coordinate,within [0-7]
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* \param[in] pix_seg Pixel/segment SEG coordinate within [0-43]
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*/
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void slcd_set_pixel(
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uint8_t pix_com,
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uint8_t pix_seg)
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{
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if ((pix_com < SLCD_MAX_COM) &&
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(pix_seg < SLCD_MAX_SEG)) {
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switch(pix_com){
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case 0:
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if (pix_seg >= 32) {
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SLCD->SDATAH0.reg |= (1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL0.reg |= 1 <<pix_seg;
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}
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break;
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case 1:
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if (pix_seg >= 32) {
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SLCD->SDATAH1.reg |= (1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL1.reg |= 1 <<pix_seg;
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}
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break;
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case 2:
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if (pix_seg >= 32) {
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SLCD->SDATAH2.reg |= (1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL2.reg |= 1 <<pix_seg;
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}
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break;
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case 3:
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if (pix_seg >= 32) {
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SLCD->SDATAH3.reg |= (1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL3.reg |= 1 <<pix_seg;
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}
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break;
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case 4:
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if (pix_seg >= 32) {
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SLCD->SDATAH4.reg |= (1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL4.reg |= 1 <<pix_seg;
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}
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break;
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case 5:
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if (pix_seg >= 32) {
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SLCD->SDATAH5.reg |= (1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL5.reg |= 1 <<pix_seg;
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}
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break;
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case 6:
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if (pix_seg >= 32) {
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SLCD->SDATAH6.reg |= (1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL6.reg |= 1 <<pix_seg;
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}
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break;
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case 7:
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if (pix_seg >= 32) {
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SLCD->SDATAH7.reg |= (1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL7.reg |= 1 <<pix_seg;
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}
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break;
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}
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while (slcd_get_char_writing_status()) {
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}
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}
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}
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/**
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* \brief Disable the specified pixel/segment in the SLCD display memory
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*
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* \param[in] pix_com Pixel/segment COM coordinate
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* \param[in] pix_seg Pixel/segment SEG coordinate
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*/
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void slcd_clear_pixel(uint8_t pix_com, uint8_t pix_seg)
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{
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if ((pix_com < SLCD_MAX_COM) &&
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(pix_seg < SLCD_MAX_SEG)) {
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switch(pix_com){
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case 0:
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if (pix_seg >= 32) {
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SLCD->SDATAH0.reg &= ~(1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL0.reg &= ~(1 <<pix_seg);
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}
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break;
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case 1:
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if (pix_seg >= 32) {
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SLCD->SDATAH1.reg &= ~(1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL1.reg &= ~(1 <<pix_seg);
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}
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break;
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case 2:
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if (pix_seg >= 32) {
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SLCD->SDATAH2.reg &= (1 <<(pix_seg-32));
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} else {
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SLCD->SDATAL2.reg &= ~(1 <<pix_seg);
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}
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break;
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case 3:
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if (pix_seg >= 32) {
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SLCD->SDATAH3.reg &= ~(1 <<(pix_seg-32));
|
|
} else {
|
|
SLCD->SDATAL3.reg &= ~(1 <<pix_seg);
|
|
}
|
|
break;
|
|
case 4:
|
|
if (pix_seg >= 32) {
|
|
SLCD->SDATAH4.reg &= ~(1 <<(pix_seg-32));
|
|
} else {
|
|
SLCD->SDATAL4.reg &= ~(1 <<pix_seg);
|
|
}
|
|
break;
|
|
case 5:
|
|
if (pix_seg >= 32) {
|
|
SLCD->SDATAH5.reg &= ~(1 <<(pix_seg-32));
|
|
} else {
|
|
SLCD->SDATAL5.reg &= ~(1 <<pix_seg);
|
|
}
|
|
break;
|
|
case 6:
|
|
if (pix_seg >= 32) {
|
|
SLCD->SDATAH6.reg &= ~(1 <<(pix_seg-32));
|
|
} else {
|
|
SLCD->SDATAL6.reg &= ~(1 <<pix_seg);
|
|
}
|
|
break;
|
|
case 7:
|
|
if (pix_seg >= 32) {
|
|
SLCD->SDATAH7.reg &= ~(1 <<(pix_seg-32));
|
|
} else {
|
|
SLCD->SDATAL7.reg &= ~(1 <<pix_seg);
|
|
}
|
|
break;
|
|
}
|
|
while (slcd_get_char_writing_status()) {
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Set the specified segment in the SLCD display memory
|
|
*
|
|
* \param[in] pix_seg Pixel/segment SEG coordinate
|
|
* \param[in] byte_offset Byte offset in display memory
|
|
* \param[in] seg_mask Byte offset in display memory
|
|
*/
|
|
void slcd_set_seg_data(uint8_t seg_data,uint8_t byte_offset,uint8_t seg_mask)
|
|
{
|
|
SLCD->ISDATA.reg = SLCD_ISDATA_SDATA(seg_data)
|
|
| SLCD_ISDATA_OFF(byte_offset)
|
|
| SLCD_ISDATA_SDMASK(seg_mask);
|
|
|
|
while (slcd_get_char_writing_status()) {
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Initializes SLCD Automated Character configurations struct to defaults
|
|
*
|
|
* Initailizes SLCD Automated Character configuration struct to predefined safe default settings.
|
|
*
|
|
* \param[in] config Pointer to an instance of \ref struct slcd_automated_char_config
|
|
*
|
|
*/
|
|
void slcd_automated_char_get_config_default(
|
|
struct slcd_automated_char_config *config)
|
|
{
|
|
Assert(config);
|
|
|
|
config->order = SLCD_AUTOMATED_CHAR_START_FROM_BOTTOM_RIGHT;
|
|
config->fc = SLCD_FRAME_COUNTER_0;
|
|
config->mode = SLCD_AUTOMATED_CHAR_SEQ;
|
|
config->seg_line_num = 0;
|
|
config->start_seg_line = 0;
|
|
config->row_digit_num = 1;
|
|
config->digit_num = 0;
|
|
config->scrolling_step = 1;
|
|
config->com_line_num = 1;
|
|
config->data_mask = 0;
|
|
|
|
}
|
|
|
|
/**
|
|
* \brief Set SLCD automated character
|
|
*
|
|
* Set automated character mode.
|
|
*
|
|
* \note SLCD automated character mode cannot be set while module or
|
|
* automated character is enabled.
|
|
*
|
|
* \param[in] config Pointer to an SLCD automated character configuration structure
|
|
*
|
|
* \return Status of the configuration procedure.
|
|
* \retval STATUS_OK SLCD automated character configuration went successful
|
|
* \retval STATUS_ERR_INVALID_ARG If automated character configuration failed
|
|
*/
|
|
enum status_code slcd_automated_char_set_config(
|
|
struct slcd_automated_char_config *const config)
|
|
{
|
|
if (!config) {
|
|
return STATUS_ERR_INVALID_ARG;
|
|
}
|
|
SLCD->CMCFG.reg = SLCD_CMCFG_NSEG(config->seg_line_num)
|
|
| (config->order << SLCD_CMCFG_DEC_Pos);
|
|
SLCD->ACMCFG.reg = SLCD_ACMCFG_FCS(config->fc)
|
|
| (config->mode << SLCD_ACMCFG_MODE_Pos)
|
|
| SLCD_ACMCFG_STSEG(config->start_seg_line)
|
|
| SLCD_ACMCFG_NDROW(config->row_digit_num)
|
|
| SLCD_ACMCFG_NDIG(config->digit_num)
|
|
| SLCD_ACMCFG_STEPS(config->scrolling_step)
|
|
| SLCD_ACMCFG_NCOM(config->com_line_num);
|
|
|
|
SLCD->CMDMASK.reg = SLCD_CMDMASK_SDMASK(config->data_mask);
|
|
|
|
return STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* \brief Set SLCD character mapping
|
|
*
|
|
* Set Character mode amd SEG line per digit.
|
|
*
|
|
* \param[in] order Mapping order in char mode
|
|
* \param[in] seg_line_num Define the number of SEG line per digit,
|
|
* it equal to number of SEG line - 1
|
|
*/
|
|
void slcd_character_map_set(
|
|
enum slcd_automated_char_order order,
|
|
uint8_t seg_line_num)
|
|
{
|
|
SLCD->CMCFG.reg = SLCD_CMCFG_NSEG(seg_line_num)
|
|
| (order << SLCD_CMCFG_DEC_Pos);
|
|
}
|
|
|
|
/**
|
|
* \brief Write segments data to display memory in character mode
|
|
*
|
|
* \param[in] seg_data Pixel/segment data
|
|
* \param[in] data_mask Segments data mask
|
|
* \param[in] com_line_index COM line index
|
|
* \param[in] seg_line_index Segments line index
|
|
*/
|
|
void slcd_character_write_data(uint8_t com_line_index,
|
|
uint8_t seg_line_index,
|
|
uint32_t seg_data,uint32_t data_mask)
|
|
{
|
|
|
|
SLCD->CMINDEX.reg = SLCD_CMINDEX_SINDEX(seg_line_index)
|
|
| SLCD_CMINDEX_CINDEX(com_line_index);
|
|
SLCD->CMDMASK.reg = SLCD_CMDMASK_SDMASK(data_mask);
|
|
SLCD->CMDATA.reg = SLCD_CMDATA_SDATA(seg_data);
|
|
while (slcd_get_char_writing_status()) {
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Initializes circular shift configurations struct to defaults
|
|
*
|
|
* Initailizes circular shift configuration struct to predefined safe default settings.
|
|
*
|
|
* \param[in] config Pointer to an instance of \ref struct slcd_circular_shift_config
|
|
*
|
|
*/
|
|
void slcd_circular_shift_get_config_defaults(
|
|
struct slcd_circular_shift_config *const config)
|
|
{
|
|
Assert(config);
|
|
|
|
config->fc = SLCD_FRAME_COUNTER_0;
|
|
config->dir = SLCD_CIRCULAR_SHIFT_LEFT;
|
|
config->size = 0;
|
|
config->data = 0;
|
|
}
|
|
|
|
/**
|
|
* \brief Set SLCD circular shift
|
|
*
|
|
* Set circular shift mode.
|
|
*
|
|
* \note SLCD circular shift mode cannot be set while module or circular shift is enabled.
|
|
*
|
|
* \param[in] config Pointer to an SLCD circular shift configuration structure
|
|
*
|
|
* \return Status of the configuration procedure.
|
|
* \retval STATUS_OK SLCD circular shift configuration went successful
|
|
* \retval STATUS_ERR_INVALID_ARG If circular shift configuration failed
|
|
*/
|
|
|
|
enum status_code slcd_circular_shift_set_config(
|
|
struct slcd_circular_shift_config *const config)
|
|
{
|
|
if (!config) {
|
|
return STATUS_ERR_INVALID_ARG;
|
|
}
|
|
SLCD->CSRCFG.reg = SLCD_CSRCFG_FCS(config->fc)
|
|
| (config->dir << SLCD_CSRCFG_DIR_Pos)
|
|
| SLCD_CSRCFG_SIZE(config->size)
|
|
| SLCD_CSRCFG_DATA(config->data);
|
|
|
|
return STATUS_OK;
|
|
}
|
|
|