173 lines
2.7 KiB
C
173 lines
2.7 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2006-03-13 Bernard first version
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*/
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#include <rtthread.h>
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#include <sep4020.h>
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extern rt_base_t rt_hw_interrupt_disable(void);
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//TODO
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#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020
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/**
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* @addtogroup S3C24X0
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*/
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/*@{*/
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#define ICACHE_MASK (rt_uint32_t)(1 << 12)
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#define DCACHE_MASK (rt_uint32_t)(1 << 2)
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#ifdef __GNUC__
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rt_inline rt_uint32_t cp15_rd(void)
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{
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rt_uint32_t i;
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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return i;
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}
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rt_inline void cache_enable(rt_uint32_t bit)
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{
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__asm__ __volatile__( \
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"mrc p15,0,r0,c1,c0,0\n\t" \
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"orr r0,r0,%0\n\t" \
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"mcr p15,0,r0,c1,c0,0" \
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: \
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:"r" (bit) \
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:"memory");
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}
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rt_inline void cache_disable(rt_uint32_t bit)
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{
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__asm__ __volatile__( \
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"mrc p15,0,r0,c1,c0,0\n\t" \
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"bic r0,r0,%0\n\t" \
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"mcr p15,0,r0,c1,c0,0" \
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: \
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:"r" (bit) \
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:"memory");
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}
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#endif
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#ifdef __CC_ARM
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rt_inline rt_uint32_t cp15_rd(void)
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{
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rt_uint32_t i;
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__asm
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{
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mrc p15, 0, i, c1, c0, 0
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}
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return i;
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}
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rt_inline void cache_enable(rt_uint32_t bit)
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{
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rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, bit
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mcr p15, 0, value, c1, c0, 0
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}
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}
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rt_inline void cache_disable(rt_uint32_t bit)
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{
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rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, bit
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mcr p15, 0, value, c1, c0, 0
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}
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}
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#endif
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/**
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* enable I-Cache
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*
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*/
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void rt_hw_cpu_icache_enable()
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{
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cache_enable(ICACHE_MASK);
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}
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/**
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* disable I-Cache
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*
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*/
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void rt_hw_cpu_icache_disable()
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{
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cache_disable(ICACHE_MASK);
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}
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/**
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* return the status of I-Cache
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*
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*/
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rt_base_t rt_hw_cpu_icache_status()
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{
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return (cp15_rd() & ICACHE_MASK);
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}
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/**
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* enable D-Cache
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*
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*/
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void rt_hw_cpu_dcache_enable()
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{
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cache_enable(DCACHE_MASK);
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}
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/**
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* disable D-Cache
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*
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*/
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void rt_hw_cpu_dcache_disable()
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{
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cache_disable(DCACHE_MASK);
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}
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/**
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* return the status of D-Cache
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*
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*/
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rt_base_t rt_hw_cpu_dcache_status()
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{
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return (cp15_rd() & DCACHE_MASK);
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}
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/**
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* reset cpu by dog's time-out
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*
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*/
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void rt_hw_cpu_reset()
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{
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/* enable watchdog */
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*(RP)(RTC_CTR) = 0x02;
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/*Enable watchdog reset*/
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*(RP)(RTC_INT_EN) = 0x20;
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/* Initialize watchdog timer count register */
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*(RP)(RTC_WD_CNT) = 0x0001;
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while(1); /* loop forever and wait for reset to happen */
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/* NEVER REACHED */
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}
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/*@}*/
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