123 lines
4.0 KiB
C
123 lines
4.0 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-05-23 aozima first implementation for PIC32.
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*/
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// Adds support for PIC32 Peripheral library functions and macros
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#include <plib.h>
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#include <rtthread.h>
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// Configuration Bits
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#pragma config FNOSC = PRIPLL // Oscillator Selection
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#pragma config FPLLIDIV = DIV_2 // PLL Input Divider (PIC32 Starter Kit: use divide by 2 only)
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#pragma config FPLLMUL = MUL_20 // PLL Multiplier
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#pragma config FPLLODIV = DIV_1 // PLL Output Divider
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#pragma config FPBDIV = DIV_1 // Peripheral Clock divisor
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#pragma config FWDTEN = OFF // Watchdog Timer
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#pragma config WDTPS = PS1 // Watchdog Timer Postscale
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#pragma config FCKSM = CSDCMD // Clock Switching & Fail Safe Clock Monitor
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#pragma config OSCIOFNC = OFF // CLKO Enable
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#pragma config POSCMOD = XT // Primary Oscillator
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#pragma config IESO = OFF // Internal/External Switch-over
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#pragma config FSOSCEN = OFF // Secondary Oscillator Enable
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#pragma config CP = OFF // Code Protect
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#pragma config BWP = OFF // Boot Flash Write Protect
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#pragma config PWP = OFF // Program Flash Write Protect
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#pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select
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#pragma config DEBUG = OFF // Debugger Disabled for Starter Kit
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// The following is used by the main application
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#define SYS_FREQ (80000000UL)
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#define PB_DIV (1 << ((OSCCON&_OSCCON_PBDIV0_MASK)>>_OSCCON_PBDIV0_POSITION) )
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#define PRESCALE 256
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#define TOGGLES_PER_SEC RT_TICK_PER_SECOND
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#define T1_TICK (SYS_FREQ/PB_DIV/PRESCALE/TOGGLES_PER_SEC)
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static void rt_hw_show_info(void)
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{
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rt_kprintf("\r\n\r\n---------- board info ----------\r\n");
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rt_kprintf("DEVICE_FAMILY: PIC32\r\n");
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rt_kprintf("CPU_ARCHITECTURE: MIPS\r\n");
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rt_kprintf("CPU_FREQ: %uMHz\r\n",SYS_FREQ/1000000UL);
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}
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static void rt_hw_timer_handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/**
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* This function will initial board.
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*/
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void rt_hw_board_init()
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{
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// Configure the device for maximum performance, but do not change the PBDIV clock divisor.
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// Given the options, this function will change the program Flash wait states,
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// RAM wait state and enable prefetch cache, but will not change the PBDIV.
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// The PBDIV value is already set via the pragma FPBDIV option above.
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SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
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/* use DBPRINTF */
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/* rt_hw_console_init(); */
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rt_hw_usart_init();
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rt_console_set_device("uart1");
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rt_hw_show_info();
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// enable multi-vector interrupts
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INTEnableSystemMultiVectoredInt();
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rt_hw_interrupt_disable();
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// // STEP 2. configure the core timer
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// OpenCoreTimer(CORE_TICK_RATE);
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//
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// // set up the core timer interrupt with a prioirty of 2 and zero sub-priority
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// mConfigIntCoreTimer((CT_INT_ON | CT_INT_PRIOR_2 | CT_INT_SUB_PRIOR_0));
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// STEP 2. configure Timer 1 using internal clock, 1:256 prescale
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OpenTimer1(T1_ON | T1_SOURCE_INT | T1_PS_1_256, T1_TICK);
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// set up the timer interrupt with a priority of 2
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ConfigIntTimer1(T1_INT_ON | T1_INT_PRIOR_2);
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/* Setup the software interrupt. */
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mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 );
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}
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void __ISR(_TIMER_1_VECTOR, ipl2) Timer1Handler(void)
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{
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// clear the interrupt flag
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mT1ClearIntFlag();
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// .. things to do
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rt_hw_timer_handler();
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}
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//void __ISR(_CORE_TIMER_VECTOR, ipl2) CoreTimerHandler(void)
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//{
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// // clear the interrupt flag
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// mCTClearIntFlag();
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//
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// // .. things to do
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// rt_hw_timer_handler();
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//
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// // update the period
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// UpdateCoreTimer(CORE_TICK_RATE);
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//}
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void __ISR(_CORE_SOFTWARE_0_VECTOR, ipl1) CoreSW0Handler(void);
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