210 lines
6.1 KiB
C
210 lines
6.1 KiB
C
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-30 lizhirui first version
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* 2021-05-03 lizhirui porting to c906
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* 2023-10-12 Shell Add permission control API
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*/
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#ifndef __RISCV_MMU_H__
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#define __RISCV_MMU_H__
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#include <rtthread.h>
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#include <rthw.h>
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#include "riscv.h"
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#undef PAGE_SIZE
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/* C-SKY extend */
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#define PTE_SEC (1UL << 59) /* Security */
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#define PTE_SHARE (1UL << 60) /* Shareable */
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#define PTE_BUF (1UL << 61) /* Bufferable */
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#define PTE_CACHE (1UL << 62) /* Cacheable */
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#define PTE_SO (1UL << 63) /* Strong Order */
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#define PAGE_OFFSET_SHIFT 0
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#define PAGE_OFFSET_BIT 12
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#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
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#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT)
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#define VPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
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#define VPN0_BIT 9
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#define VPN1_SHIFT (VPN0_SHIFT + VPN0_BIT)
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#define VPN1_BIT 9
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#define VPN2_SHIFT (VPN1_SHIFT + VPN1_BIT)
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#define VPN2_BIT 9
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#define PPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
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#define PPN0_BIT 9
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#define PPN1_SHIFT (PPN0_SHIFT + PPN0_BIT)
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#define PPN1_BIT 9
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#define PPN2_SHIFT (PPN1_SHIFT + PPN1_BIT)
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#define PPN2_BIT 26
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#define PPN_BITS (PPN0_BIT + PPN1_BIT + PPN2_BIT)
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#define L1_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT + VPN1_BIT)
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#define L2_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT)
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#define L3_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
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#define ARCH_ADDRESS_WIDTH_BITS 64
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#define PHYSICAL_ADDRESS_WIDTH_BITS 56
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#define PAGE_ATTR_NEXT_LEVEL (0)
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#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R)
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#define PAGE_ATTR_READONLY (PTE_R)
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#define PAGE_ATTR_XN (PTE_W | PTE_R)
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#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R)
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#define PAGE_ATTR_USER (PTE_U)
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#define PAGE_ATTR_SYSTEM (0)
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#define PAGE_ATTR_CB (PTE_BUF | PTE_CACHE)
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#define PAGE_ATTR_DEV (PTE_SO)
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#define PAGE_DEFAULT_ATTR_LEAF \
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(PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_U | \
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PAGE_ATTR_RWX | PTE_V)
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#define PAGE_DEFAULT_ATTR_NEXT \
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(PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_V)
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#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)
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#define PTE_USED(pte) __MASKVALUE(pte, PTE_V)
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#define PTE_WRAP(attr) (attr | PTE_A | PTE_D)
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/**
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* encoding of SATP (Supervisor Address Translation and Protection register)
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*/
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#define SATP_MODE_OFFSET 60
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#define SATP_MODE_BARE 0
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#define SATP_MODE_SV39 8
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#define SATP_MODE_SV48 9
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#define SATP_MODE_SV57 10
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#define SATP_MODE_SV64 11
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#define ARCH_VADDR_WIDTH 39
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#define SATP_MODE SATP_MODE_SV39
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#define MMU_MAP_K_DEVICE PTE_WRAP(PAGE_ATTR_DEV | PTE_G | PAGE_ATTR_XN | PTE_V)
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#define MMU_MAP_K_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_G | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_K_RW PTE_WRAP(PTE_G | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_U_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_U_ROCB \
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PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_READONLY | PTE_V)
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#define MMU_MAP_U_RWCB_XN PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_XN | PTE_V)
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#define MMU_MAP_U_RW PTE_WRAP(PTE_U | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_EARLY \
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PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_CACHE | PTE_SHARE | PTE_BUF)
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#define MMU_MAP_TRACE(attr) (attr)
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#define PTE_XWR_MASK 0xe
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#define ARCH_PAGE_SIZE PAGE_SIZE
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#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
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#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT
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#define ARCH_INDEX_WIDTH 9
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#define ARCH_INDEX_SIZE (1ul << ARCH_INDEX_WIDTH)
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#define ARCH_INDEX_MASK (ARCH_INDEX_SIZE - 1)
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#define ARCH_MAP_FAILED ((void *)0x8000000000000000)
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void mmu_set_pagetable(rt_ubase_t addr);
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void mmu_enable_user_page_access(void);
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void mmu_disable_user_page_access(void);
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#define RT_HW_MMU_PROT_READ 1
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#define RT_HW_MMU_PROT_WRITE 2
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#define RT_HW_MMU_PROT_EXECUTE 4
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#define RT_HW_MMU_PROT_KERNEL 8
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#define RT_HW_MMU_PROT_USER 16
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#define RT_HW_MMU_PROT_CACHE 32
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void rt_hw_asid_init(void);
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struct rt_aspace;
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void rt_hw_asid_switch_pgtbl(struct rt_aspace *aspace, rt_ubase_t pgtbl);
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/**
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* @brief Remove permission from attribution
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*
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* @param attr architecture specified mmu attribution
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* @param prot protect that will be removed
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* @return size_t returned attribution
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*/
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rt_inline size_t rt_hw_mmu_attr_rm_perm(size_t attr, rt_base_t prot)
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{
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switch (prot)
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{
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/* remove write permission for user */
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case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
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attr &= ~PTE_W;
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break;
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/* remove write permission for kernel */
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case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_KERNEL:
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attr &= ~PTE_W;
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break;
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default:
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RT_ASSERT(0);
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}
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return attr;
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}
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/**
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* @brief Add permission from attribution
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*
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* @param attr architecture specified mmu attribution
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* @param prot protect that will be added
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* @return size_t returned attribution
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*/
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rt_inline size_t rt_hw_mmu_attr_add_perm(size_t attr, rt_base_t prot)
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{
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switch (prot)
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{
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/* add write permission for user */
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case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
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attr |= (PTE_R | PTE_W | PTE_U);
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break;
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default:
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RT_ASSERT(0);
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}
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return attr;
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}
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/**
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* @brief Test permission from attribution
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*
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* @param attr architecture specified mmu attribution
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* @param prot protect that will be test
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* @return rt_bool_t RT_TRUE if the prot is allowed, otherwise RT_FALSE
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*/
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rt_inline rt_bool_t rt_hw_mmu_attr_test_perm(size_t attr, rt_base_t prot)
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{
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rt_bool_t rc = 0;
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switch (prot & ~RT_HW_MMU_PROT_USER)
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{
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/* test write permission for user */
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case RT_HW_MMU_PROT_WRITE:
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rc = ((attr & PTE_W) && (attr & PTE_R));
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break;
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case RT_HW_MMU_PROT_READ:
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rc = !!(attr & PTE_R);
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break;
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case RT_HW_MMU_PROT_EXECUTE:
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rc = !!(attr & PTE_X);
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break;
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default:
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RT_ASSERT(0);
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}
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if (rc && (prot & RT_HW_MMU_PROT_USER))
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{
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rc = !!(attr & PTE_U);
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}
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return rc;
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}
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#endif
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