130 lines
3.7 KiB
C
130 lines
3.7 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-29 lizhirui first version
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* 2021-11-05 JasonHu add c906 cache inst
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* 2022-11-09 WangXiaoyao Support cache coherence operations;
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* improve portability and make
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* no assumption on undefined behavior
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*/
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#include <rthw.h>
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#include <rtdef.h>
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#include <board.h>
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#include <riscv.h>
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#include "opcode.h"
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#include "cache.h"
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#define L1_CACHE_BYTES (64)
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/**
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* GCC version not support t-head cache flush, so we use fixed code to achieve.
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* The following function cannot be optimized.
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*/
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static void dcache_wb_range(unsigned long start, unsigned long end) __attribute__((optimize("O0")));
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static void dcache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0")));
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static void dcache_wbinv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0")));
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static void icache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0")));
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#define CACHE_OP_RS1 %0
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#define CACHE_OP_RANGE(instr) \
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{ \
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register rt_ubase_t i = start & ~(L1_CACHE_BYTES - 1); \
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for (; i < end; i += L1_CACHE_BYTES) \
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{ \
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__asm__ volatile(instr ::"r"(i) \
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: "memory"); \
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} \
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}
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static void dcache_wb_range(unsigned long start, unsigned long end)
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{
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CACHE_OP_RANGE(OPC_DCACHE_CVA(CACHE_OP_RS1));
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}
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static void dcache_inv_range(unsigned long start, unsigned long end)
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{
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CACHE_OP_RANGE(OPC_DCACHE_IVA(CACHE_OP_RS1));
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}
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static void dcache_wbinv_range(unsigned long start, unsigned long end)
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{
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CACHE_OP_RANGE(OPC_DCACHE_CIVA(CACHE_OP_RS1));
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}
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static void icache_inv_range(unsigned long start, unsigned long end)
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{
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CACHE_OP_RANGE(OPC_ICACHE_IVA(CACHE_OP_RS1));
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}
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rt_inline rt_uint32_t rt_cpu_icache_line_size(void)
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{
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return L1_CACHE_BYTES;
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}
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rt_inline rt_uint32_t rt_cpu_dcache_line_size(void)
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{
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return L1_CACHE_BYTES;
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}
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void rt_hw_cpu_icache_invalidate_local(void *addr, int size)
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{
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icache_inv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size));
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rt_hw_cpu_sync_i();
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}
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void rt_hw_cpu_dcache_invalidate_local(void *addr, int size)
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{
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dcache_inv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size));
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rt_hw_cpu_sync();
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}
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void rt_hw_cpu_dcache_clean_local(void *addr, int size)
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{
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dcache_wb_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size));
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rt_hw_cpu_sync();
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}
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void rt_hw_cpu_dcache_clean_and_invalidate_local(void *addr, int size)
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{
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dcache_wbinv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size));
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rt_hw_cpu_sync();
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}
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/**
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* =====================================================
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* Architecture Independent API
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* =====================================================
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*/
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void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_INVALIDATE)
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{
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rt_hw_cpu_icache_invalidate_local(addr, size);
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}
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}
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void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_FLUSH)
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{
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rt_hw_cpu_dcache_clean_local(addr, size);
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}
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else
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{
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rt_hw_cpu_dcache_invalidate_local(addr, size);
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}
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}
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void rt_hw_sync_cache_local(void *addr, int size)
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{
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rt_hw_cpu_dcache_clean_local(addr, size);
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rt_hw_cpu_icache_invalidate_local(addr, size);
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}
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