207 lines
4.2 KiB
C
207 lines
4.2 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-02-25 GuEe-GUI the first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#define AHCI_REG_BAR 5
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struct pci_ahci_quirk
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{
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int bar_idx;
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rt_bool_t bar_offset;
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const struct rt_ahci_ops *ops;
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};
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struct pci_ahci_host
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{
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struct rt_ahci_host parent;
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const struct pci_ahci_quirk *quirk;
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rt_bool_t is_msi;
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};
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#define raw_to_pci_ahci_host(raw) rt_container_of(raw, struct pci_ahci_host, parent)
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static rt_err_t pci_ahci_init(struct rt_ahci_host *host)
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{
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struct rt_pci_device *pdev;
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pdev = rt_container_of(host->parent.dev, struct rt_pci_device, parent);
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if (pdev->vendor == PCI_VENDOR_ID_JMICRON)
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{
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rt_pci_write_config_u8(pdev, 0x41, 0xa1);
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}
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return RT_EOK;
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}
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static const struct rt_ahci_ops pci_ahci_ops =
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{
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.host_init = pci_ahci_init,
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};
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static rt_err_t pci_ahci_intel_init(struct rt_ahci_host *host)
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{
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rt_uint16_t val;
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struct rt_pci_device *pdev;
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pdev = rt_container_of(host->parent.dev, struct rt_pci_device, parent);
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rt_pci_read_config_u16(pdev, 0x92, &val);
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rt_pci_write_config_u16(pdev, 0x92, val & ~0xf);
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rt_thread_mdelay(10);
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rt_pci_write_config_u16(pdev, 0x92, val | 0xf);
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return RT_EOK;
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}
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static const struct rt_ahci_ops pci_ahci_intel_ops =
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{
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.host_init = pci_ahci_intel_init,
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};
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static rt_err_t pci_ahci_probe(struct rt_pci_device *pdev)
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{
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rt_err_t err;
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int bar_idx;
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struct rt_ahci_host *ahci;
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struct pci_ahci_host *pci_ahci = rt_calloc(1, sizeof(*pci_ahci));
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const struct pci_ahci_quirk *quirk = pdev->id->data;
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if (!pci_ahci)
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{
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return -RT_ENOMEM;
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}
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pci_ahci->quirk = quirk;
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ahci = &pci_ahci->parent;
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ahci->parent.dev = &pdev->parent;
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bar_idx = quirk && quirk->bar_offset ? quirk->bar_idx : AHCI_REG_BAR;
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ahci->regs = rt_pci_iomap(pdev, bar_idx);
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if (!ahci->regs)
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{
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err = -RT_EIO;
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goto _fail;
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}
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ahci->ops = quirk && quirk->ops ? quirk->ops : &pci_ahci_ops;
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if (rt_pci_msi_enable(pdev) > 0)
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{
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pci_ahci->is_msi = RT_TRUE;
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}
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else
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{
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rt_pci_irq_unmask(pdev);
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}
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ahci->irq = pdev->irq;
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rt_pci_set_master(pdev);
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if ((err = rt_ahci_host_register(ahci)))
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{
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goto _disable;
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}
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pdev->parent.user_data = pci_ahci;
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return RT_EOK;
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_disable:
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if (pci_ahci->is_msi)
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{
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rt_pci_msix_disable(pdev);
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}
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else
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{
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rt_pci_irq_mask(pdev);
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}
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rt_pci_clear_master(pdev);
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rt_iounmap(ahci->regs);
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_fail:
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rt_free(pci_ahci);
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return err;
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}
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static rt_err_t pci_ahci_remove(struct rt_pci_device *pdev)
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{
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struct rt_ahci_host *ahci;
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struct pci_ahci_host *pci_ahci = pdev->parent.user_data;
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ahci = &pci_ahci->parent;
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rt_ahci_host_unregister(ahci);
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if (pci_ahci->is_msi)
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{
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rt_pci_msi_disable(pdev);
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}
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else
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{
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/* INTx is shared, don't mask all */
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rt_hw_interrupt_umask(pdev->irq);
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rt_pci_irq_mask(pdev);
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}
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rt_pci_clear_master(pdev);
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rt_iounmap(ahci->regs);
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rt_free(pci_ahci);
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return RT_EOK;
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}
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static rt_err_t pci_ahci_shutdown(struct rt_pci_device *pdev)
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{
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return pci_ahci_remove(pdev);
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}
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static struct pci_ahci_quirk intel_quirk =
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{
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.ops = &pci_ahci_intel_ops,
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};
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static struct pci_ahci_quirk cavium_sata_quirk =
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{
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.bar_idx = 0,
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.bar_offset = RT_TRUE,
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};
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static const struct rt_pci_device_id pci_ahci_ids[] =
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{
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{ RT_PCI_DEVICE_ID(PCI_VENDOR_ID_INTEL, 0x2922), .data = &intel_quirk },
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{ RT_PCI_DEVICE_ID(PCI_VENDOR_ID_ASMEDIA, 0x0611) },
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{ RT_PCI_DEVICE_ID(PCI_VENDOR_ID_MARVELL, 0x6121) },
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{ RT_PCI_DEVICE_ID(PCI_VENDOR_ID_MARVELL, 0x6145) },
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{ RT_PCI_DEVICE_ID(PCI_VENDOR_ID_CAVIUM, 0xa01c), .data = &cavium_sata_quirk },
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{ RT_PCI_DEVICE_CLASS(PCIS_STORAGE_SATA_AHCI, ~0) },
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{ /* sentinel */ }
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};
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static struct rt_pci_driver pci_ahci_driver =
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{
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.name = "ahci-pci",
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.ids = pci_ahci_ids,
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.probe = pci_ahci_probe,
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.remove = pci_ahci_remove,
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.shutdown = pci_ahci_shutdown,
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};
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RT_PCI_DRIVER_EXPORT(pci_ahci_driver);
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