64 lines
2.2 KiB
C
64 lines
2.2 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-06 SummerGift first version
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* 2019-10-13 xuzhuoyi add stm32f429-st-disco bsp
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*/
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#include <board.h>
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#include <drv_common.h>
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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/** Configure the main internal regulator output voltage
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*/
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 4;
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RCC_OscInitStruct.PLL.PLLN = 168;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
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{
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Error_Handler();
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}
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/*##-2- LTDC Clock Configuration ###########################################*/
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/* LCD clock configuration */
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/* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 MHz */
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/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 MHz */
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/* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/4 = 48 MHz */
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/* LTDC clock frequency = PLLLCDCLK / RCC_PLLSAIDIVR_8 = 48/8 = 6 MHz */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
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PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
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PeriphClkInitStruct.PLLSAI.PLLSAIR = 4;
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PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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}
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