587 lines
23 KiB
ArmAsm
587 lines
23 KiB
ArmAsm
;*******************************************************************************
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; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
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; SmartFusion2 startup code for Keil-MDK.
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;
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; SmartFusion2 vector table and startup code for ARM tool chain.
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;
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; SVN $Revision: 7419 $
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; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
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;
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00001000
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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stack_start
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Stack_Mem SPACE Stack_Size
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__initial_sp
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stack_end
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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;===============================================================================
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WdogWakeup_IRQHandler
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DCD RTC_Wakeup_IRQHandler
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DCD SPI0_IRQHandler
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DCD SPI1_IRQHandler
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DCD I2C0_IRQHandler
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DCD I2C0_SMBAlert_IRQHandler
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DCD I2C0_SMBus_IRQHandler
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DCD I2C1_IRQHandler
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DCD I2C1_SMBAlert_IRQHandler
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DCD I2C1_SMBus_IRQHandler
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DCD UART0_IRQHandler
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DCD UART1_IRQHandler
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DCD EthernetMAC_IRQHandler
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DCD DMA_IRQHandler
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DCD Timer1_IRQHandler
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DCD Timer2_IRQHandler
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DCD CAN_IRQHandler
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DCD ENVM0_IRQHandler
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DCD ENVM1_IRQHandler
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DCD ComBlk_IRQHandler
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DCD USB_IRQHandler
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DCD USB_DMA_IRQHandler
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DCD PLL_Lock_IRQHandler
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DCD PLL_LockLost_IRQHandler
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DCD CommSwitchError_IRQHandler
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DCD CacheError_IRQHandler
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DCD DDR_IRQHandler
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DCD HPDMA_Complete_IRQHandler
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DCD HPDMA_Error_IRQHandler
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DCD ECC_Error_IRQHandler
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DCD MDDR_IOCalib_IRQHandler
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DCD FAB_PLL_Lock_IRQHandler
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DCD FAB_PLL_LockLost_IRQHandler
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DCD FIC64_IRQHandler
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DCD FabricIrq0_IRQHandler
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DCD FabricIrq1_IRQHandler
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DCD FabricIrq2_IRQHandler
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DCD FabricIrq3_IRQHandler
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DCD FabricIrq4_IRQHandler
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DCD FabricIrq5_IRQHandler
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DCD FabricIrq6_IRQHandler
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DCD FabricIrq7_IRQHandler
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DCD FabricIrq8_IRQHandler
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DCD FabricIrq9_IRQHandler
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DCD FabricIrq10_IRQHandler
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DCD FabricIrq11_IRQHandler
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DCD FabricIrq12_IRQHandler
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DCD FabricIrq13_IRQHandler
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DCD FabricIrq14_IRQHandler
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DCD FabricIrq15_IRQHandler
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DCD GPIO0_IRQHandler
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DCD GPIO1_IRQHandler
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DCD GPIO2_IRQHandler
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DCD GPIO3_IRQHandler
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DCD GPIO4_IRQHandler
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DCD GPIO5_IRQHandler
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DCD GPIO6_IRQHandler
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DCD GPIO7_IRQHandler
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DCD GPIO8_IRQHandler
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DCD GPIO9_IRQHandler
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DCD GPIO10_IRQHandler
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DCD GPIO11_IRQHandler
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DCD GPIO12_IRQHandler
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DCD GPIO13_IRQHandler
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DCD GPIO14_IRQHandler
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DCD GPIO15_IRQHandler
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DCD GPIO16_IRQHandler
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DCD GPIO17_IRQHandler
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DCD GPIO18_IRQHandler
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DCD GPIO19_IRQHandler
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DCD GPIO20_IRQHandler
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DCD GPIO21_IRQHandler
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DCD GPIO22_IRQHandler
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DCD GPIO23_IRQHandler
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DCD GPIO24_IRQHandler
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DCD GPIO25_IRQHandler
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DCD GPIO26_IRQHandler
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DCD GPIO27_IRQHandler
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DCD GPIO28_IRQHandler
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DCD GPIO29_IRQHandler
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DCD GPIO30_IRQHandler
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DCD GPIO31_IRQHandler
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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;===============================================================================
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; Reset Handler
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;
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AREA |.text|, CODE, READONLY
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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; IMPORT low_level_init
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IMPORT __main
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;---------------------------------------------------------------
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; Initialize stack RAM content to initialize the error detection
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; and correction (EDAC). This is done if EDAC is enabled for the
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; eSRAM blocks or the ECC/SECDED is enabled for the MDDR.
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; Register R11 is used to keep track of the RAM intialization
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; decision outcome for later use for heap RAM initialization at
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; the end of the startup code.
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; Please note that the stack has to be located in eSRAM at this
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; point and cannot be located in MDDR since MDDR is not available
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; at this point.
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; The bits of the content of register R11 have the foolwing
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; meaning:
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; reg11[0]: eSRAM EDAC enabled
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; reg11[1]: MDDR ECC/SECDED enabled
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;
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MOV R11, #0
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LDR R0, SF2_MDDR_MODE_CR
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LDR R0, [R0]
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LDR R1, SF2_EDAC_CR
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LDR R1, [R1]
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AND R1, R1, #3
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AND R0, R0, #0x1C
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CMP R0, #0x14
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BNE check_esram_edac
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ORR R11, R11, #2
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check_esram_edac
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CMP R1, #0
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BEQ check_stack_init
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ORR R11, R11, #1
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check_stack_init
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CMP R11, #0
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BEQ call_system_init
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clear_stack
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LDR R0, =stack_start
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LDR R1, =stack_end
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LDR R2, RAM_INIT_PATTERN
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BL fill_memory ; fill_memory takes r0 - r2 as arguments uses r4, r5, r6, r7, r8, r9, and does not preserve contents */
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;---------------------------------------------------------------
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; Call SystemInit() to perform Libero specified configuration.
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;
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call_system_init
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LDR R0, =SystemInit
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BLX R0
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; LDR R0, =low_level_init
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; BLX R0
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;---------------------------------------------------------------
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; Modify MDDR configuration if ECC/SECDED is enabled for MDDR.
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; Enable write combining on MDDR bridge, disable non-bufferable
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; regions.
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;
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adjust_mddr_cfg
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AND R10, R11, #0x2
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CMP R10, #0
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BEQ branch_to_main
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LDR R0, SF2_DDRB_NB_SIZE
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LDR R1, SF2_DDRB_CR
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LDR R2, [R0]
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LDR R3, [R1]
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push {R0, R1, R2, R3}
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MOV R2, #0
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MOV R3, #0xFF
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STR R2, [R0]
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STR R3, [R1]
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; --------------------------------------------------------------
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; Initialize heap RAM content to initialize the error detection
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; and correction (EDAC). We use the decision made earlier in the
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; startup code of whether or not the stack RAM should be
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; initialized. This decision is held in register R11. A non-zero
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; value indicates that the RAM content should be initialized.
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;
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clear_heap
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CMP R11, #0
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BEQ branch_to_main
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LDR R0, =__heap_base
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LDR R1, =__heap_limit
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LDR R2, HEAP_INIT_PATTERN
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BL fill_memory ; fill_memory takes r0 - r2 as arguments uses r4, r5, r6, r7, r8, r9, and does not preserve contents */
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;---------------------------------------------------------------
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; Branch to __main
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;
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branch_to_main
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LDR R0, =__main
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BX R0
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ENDP
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SF2_EDAC_CR DCD 0x40038038
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SF2_DDRB_NB_SIZE DCD 0x40038030
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SF2_DDRB_CR DCD 0x40038034
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SF2_MDDR_MODE_CR DCD 0x40020818
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RAM_INIT_PATTERN DCD 0x00000000
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HEAP_INIT_PATTERN DCD 0x00000000
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;------------------------------------------------------------------------------
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; * fill_memory.
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; * @brief Fills memory with Pattern contained in r2
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; * This routine uses the stmne instruction to copy 4 words at a time which is very efficient
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; * The instruction can only write to word aligned memory, hence the code at the start and end of this routine
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; * to handle possible unaligned bytes at start and end.
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; *
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; * @param param1 r0: start address
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; * @param param2 r1: end address
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; * @param param3 r2: FILL PATTETN
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; *
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; * @note note: Most efficient if memory aligned. Linker ALIGN(4) command
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; * should be used as per example linker scripts
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; * Stack is not used in this routine
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; * register contents r4, r5, r6, r7, r8, r9, will are used and will be returned undefined
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; * @return none - Used Registers are not preserved
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; */
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fill_memory PROC
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;push {r4, r5, r6, r7, r8, r9, lr} We will not use stack as may be not available */
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cmp r0, r1
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beq fill_memory_exit ; Exit early if source and destination the same */
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; copy non-aligned bytes at the start */
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and.w r6, r0, #3 ; see if non-alaigned bytes at the start */
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cmp r6, #0
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beq fill_memory_end_start ; no spare bytes at start, continue */
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mov r5, #4
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sub.w r4, r5, r6 ; now have number of non-aligned bytes in r4 */
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mov r7, #8
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mul r8, r7, r6 ; calculate number of shifts required to initalise pattern for non-aligned bytes */
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mov r9, r2 ; copy pattern */
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ror r9, r9, r8 ; Rotate right to keep pattern consistent */
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fill_memory_spare_bytes_start ; From above, R0 contains source address, R1 contains destination address */
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cmp r4, #0 ; no spare bytes at end- end now */
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beq fill_memory_end_start
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strb r9, [r0] ; fill byte */
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ror.w r9, r9, r7 ; Rotate right by one byte for the next time, to keep pattern consistent */
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add r0, r0, #1 ; add one to address */
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subs r4, r4, #1 ; subtract one from byte count 1 */
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b fill_memory_spare_bytes_start
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fill_memory_end_start
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mov r6, #0
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mov r7, r1 ; save end address */
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subs r1, r1, r0 ; Calculate number of bytes to fill */
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mov r8,r1 ; Save copy of byte count */
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asrs r1,r1, #4 ; Div by 16 to get number of chunks to move */
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mov r9, r2 ; copy pattern */
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mov r4, r2 ; copy pattern */
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mov r5, r2 ; copy pattern */
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cmp r1, r6 ; compare to see if all chunks copied */
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beq fill_memory_spare_bytes_end
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fill_memory_loop
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it ne
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stmne r0!, {r2, r4, r5, r9} ; copy pattern- note: stmne instruction must me word aligned (address in r0) */
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add.w r6, r6, #1 ; use Thumb2- make sure condition code reg. not updated */
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cmp r1, r6 ; compare to see if all chunks copied */
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bne fill_memory_loop
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fill_memory_spare_bytes_end ; copy spare bytes at the end if any */
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and.w r8, r8, #15 ; get spare bytes --check can you do an ands? */
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fill_memory_spare_end_loop ; From above, R0 contains source address, R1 contains destination address */
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cmp r8, #0 ; no spare bytes at end- end now */
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beq fill_memory_exit
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strb r2, [r0]
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ror.w r2, r2, #8 ; Rotate right by one byte for the next time, to keep pattern consistent */
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add r0, r0, #1 ; add one to address */
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subs r8, r8, #1 ; subtract one from byte count 1 */
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b fill_memory_spare_end_loop
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fill_memory_exit
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bx lr ; We will not use pop as stack may be not available */
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ENDP
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;===============================================================================
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WdogWakeup_IRQHandler [WEAK]
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EXPORT RTC_Wakeup_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C0_SMBAlert_IRQHandler [WEAK]
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EXPORT I2C0_SMBus_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT I2C1_SMBAlert_IRQHandler [WEAK]
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EXPORT I2C1_SMBus_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT EthernetMAC_IRQHandler [WEAK]
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EXPORT DMA_IRQHandler [WEAK]
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EXPORT Timer1_IRQHandler [WEAK]
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EXPORT Timer2_IRQHandler [WEAK]
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EXPORT CAN_IRQHandler [WEAK]
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EXPORT ENVM0_IRQHandler [WEAK]
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EXPORT ENVM1_IRQHandler [WEAK]
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EXPORT ComBlk_IRQHandler [WEAK]
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EXPORT USB_IRQHandler [WEAK]
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EXPORT USB_DMA_IRQHandler [WEAK]
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EXPORT PLL_Lock_IRQHandler [WEAK]
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EXPORT PLL_LockLost_IRQHandler [WEAK]
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EXPORT CommSwitchError_IRQHandler [WEAK]
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EXPORT CacheError_IRQHandler [WEAK]
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EXPORT DDR_IRQHandler [WEAK]
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EXPORT HPDMA_Complete_IRQHandler [WEAK]
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EXPORT HPDMA_Error_IRQHandler [WEAK]
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EXPORT ECC_Error_IRQHandler [WEAK]
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EXPORT MDDR_IOCalib_IRQHandler [WEAK]
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EXPORT FAB_PLL_Lock_IRQHandler [WEAK]
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EXPORT FAB_PLL_LockLost_IRQHandler [WEAK]
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EXPORT FIC64_IRQHandler [WEAK]
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EXPORT FabricIrq0_IRQHandler [WEAK]
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EXPORT FabricIrq1_IRQHandler [WEAK]
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EXPORT FabricIrq2_IRQHandler [WEAK]
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EXPORT FabricIrq3_IRQHandler [WEAK]
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EXPORT FabricIrq4_IRQHandler [WEAK]
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EXPORT FabricIrq5_IRQHandler [WEAK]
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EXPORT FabricIrq6_IRQHandler [WEAK]
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EXPORT FabricIrq7_IRQHandler [WEAK]
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EXPORT FabricIrq8_IRQHandler [WEAK]
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EXPORT FabricIrq9_IRQHandler [WEAK]
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EXPORT FabricIrq10_IRQHandler [WEAK]
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EXPORT FabricIrq11_IRQHandler [WEAK]
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EXPORT FabricIrq12_IRQHandler [WEAK]
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EXPORT FabricIrq13_IRQHandler [WEAK]
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EXPORT FabricIrq14_IRQHandler [WEAK]
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EXPORT FabricIrq15_IRQHandler [WEAK]
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EXPORT GPIO0_IRQHandler [WEAK]
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EXPORT GPIO1_IRQHandler [WEAK]
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EXPORT GPIO2_IRQHandler [WEAK]
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EXPORT GPIO3_IRQHandler [WEAK]
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EXPORT GPIO4_IRQHandler [WEAK]
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EXPORT GPIO5_IRQHandler [WEAK]
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EXPORT GPIO6_IRQHandler [WEAK]
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EXPORT GPIO7_IRQHandler [WEAK]
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EXPORT GPIO8_IRQHandler [WEAK]
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EXPORT GPIO9_IRQHandler [WEAK]
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EXPORT GPIO10_IRQHandler [WEAK]
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EXPORT GPIO11_IRQHandler [WEAK]
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EXPORT GPIO12_IRQHandler [WEAK]
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EXPORT GPIO13_IRQHandler [WEAK]
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EXPORT GPIO14_IRQHandler [WEAK]
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EXPORT GPIO15_IRQHandler [WEAK]
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EXPORT GPIO16_IRQHandler [WEAK]
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EXPORT GPIO17_IRQHandler [WEAK]
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EXPORT GPIO18_IRQHandler [WEAK]
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EXPORT GPIO19_IRQHandler [WEAK]
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EXPORT GPIO20_IRQHandler [WEAK]
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EXPORT GPIO21_IRQHandler [WEAK]
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EXPORT GPIO22_IRQHandler [WEAK]
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EXPORT GPIO23_IRQHandler [WEAK]
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EXPORT GPIO24_IRQHandler [WEAK]
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EXPORT GPIO25_IRQHandler [WEAK]
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EXPORT GPIO26_IRQHandler [WEAK]
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EXPORT GPIO27_IRQHandler [WEAK]
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EXPORT GPIO28_IRQHandler [WEAK]
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EXPORT GPIO29_IRQHandler [WEAK]
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EXPORT GPIO30_IRQHandler [WEAK]
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EXPORT GPIO31_IRQHandler [WEAK]
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WdogWakeup_IRQHandler
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RTC_Wakeup_IRQHandler
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SPI0_IRQHandler
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SPI1_IRQHandler
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I2C0_IRQHandler
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I2C0_SMBAlert_IRQHandler
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I2C0_SMBus_IRQHandler
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I2C1_IRQHandler
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I2C1_SMBAlert_IRQHandler
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I2C1_SMBus_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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EthernetMAC_IRQHandler
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DMA_IRQHandler
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Timer1_IRQHandler
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Timer2_IRQHandler
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CAN_IRQHandler
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ENVM0_IRQHandler
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ENVM1_IRQHandler
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ComBlk_IRQHandler
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USB_IRQHandler
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USB_DMA_IRQHandler
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PLL_Lock_IRQHandler
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PLL_LockLost_IRQHandler
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CommSwitchError_IRQHandler
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CacheError_IRQHandler
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DDR_IRQHandler
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HPDMA_Complete_IRQHandler
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HPDMA_Error_IRQHandler
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ECC_Error_IRQHandler
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MDDR_IOCalib_IRQHandler
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FAB_PLL_Lock_IRQHandler
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FAB_PLL_LockLost_IRQHandler
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FIC64_IRQHandler
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FabricIrq0_IRQHandler
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FabricIrq1_IRQHandler
|
|
FabricIrq2_IRQHandler
|
|
FabricIrq3_IRQHandler
|
|
FabricIrq4_IRQHandler
|
|
FabricIrq5_IRQHandler
|
|
FabricIrq6_IRQHandler
|
|
FabricIrq7_IRQHandler
|
|
FabricIrq8_IRQHandler
|
|
FabricIrq9_IRQHandler
|
|
FabricIrq10_IRQHandler
|
|
FabricIrq11_IRQHandler
|
|
FabricIrq12_IRQHandler
|
|
FabricIrq13_IRQHandler
|
|
FabricIrq14_IRQHandler
|
|
FabricIrq15_IRQHandler
|
|
GPIO0_IRQHandler
|
|
GPIO1_IRQHandler
|
|
GPIO2_IRQHandler
|
|
GPIO3_IRQHandler
|
|
GPIO4_IRQHandler
|
|
GPIO5_IRQHandler
|
|
GPIO6_IRQHandler
|
|
GPIO7_IRQHandler
|
|
GPIO8_IRQHandler
|
|
GPIO9_IRQHandler
|
|
GPIO10_IRQHandler
|
|
GPIO11_IRQHandler
|
|
GPIO12_IRQHandler
|
|
GPIO13_IRQHandler
|
|
GPIO14_IRQHandler
|
|
GPIO15_IRQHandler
|
|
GPIO16_IRQHandler
|
|
GPIO17_IRQHandler
|
|
GPIO18_IRQHandler
|
|
GPIO19_IRQHandler
|
|
GPIO20_IRQHandler
|
|
GPIO21_IRQHandler
|
|
GPIO22_IRQHandler
|
|
GPIO23_IRQHandler
|
|
GPIO24_IRQHandler
|
|
GPIO25_IRQHandler
|
|
GPIO26_IRQHandler
|
|
GPIO27_IRQHandler
|
|
GPIO28_IRQHandler
|
|
GPIO29_IRQHandler
|
|
GPIO30_IRQHandler
|
|
GPIO31_IRQHandler
|
|
B .
|
|
|
|
ENDP
|
|
|
|
mscc_post_hw_cfg_init PROC
|
|
EXPORT mscc_post_hw_cfg_init [WEAK]
|
|
BX LR
|
|
ENDP
|
|
|
|
ALIGN
|
|
|
|
|
|
;===============================================================================
|
|
; User Initial Stack & Heap
|
|
|
|
IF :DEF:__MICROLIB
|
|
|
|
EXPORT __initial_sp
|
|
EXPORT __heap_base
|
|
EXPORT __heap_limit
|
|
|
|
ELSE
|
|
|
|
IMPORT __use_two_region_memory
|
|
EXPORT __user_initial_stackheap
|
|
__user_initial_stackheap
|
|
|
|
LDR R0, = Heap_Mem
|
|
LDR R1, =(Stack_Mem + Stack_Size)
|
|
LDR R2, = (Heap_Mem + Heap_Size)
|
|
LDR R3, = Stack_Mem
|
|
BX LR
|
|
|
|
ALIGN
|
|
|
|
ENDIF
|
|
|
|
|
|
END
|