151 lines
3.8 KiB
C
151 lines
3.8 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-03-04 Carl the first version
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*
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*/
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#include <rtthread.h>
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#include "ft_printf.h"
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#include "ft_assert.h"
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#include "ft_cpu.h"
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#include "ft_psci.h"
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#include "ft_parameters.h"
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#include "board.h"
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#include "gtimer.h"
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#include "ft_generic_timer.h"
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#include <gicv3.h>
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#include "interrupt.h"
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#include <mmu.h>
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#include "cp15.h"
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#include "ft2004.h"
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#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWT | DESC_SEC)
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struct mem_desc platform_mem_desc[] = {
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{0x80000000,
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0x80000000 + 0x7f000000,
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0x80000000,
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DDR_MEM},
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{0, //< QSPI
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0x1FFFFFFF,
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0,
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DEVICE_MEM},
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{0x20000000, //<! LPC
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0x27FFFFFF,
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0x20000000,
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DEVICE_MEM},
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{FT_DEV_BASE_ADDR, //<! Device register
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FT_DEV_END_ADDR,
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FT_DEV_BASE_ADDR,
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DEVICE_MEM},
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{0x30000000, //<! debug
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0x39FFFFFF,
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0x30000000,
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DEVICE_MEM},
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{0x3A000000, //<! Internal register space in the on-chip network
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0x3AFFFFFF,
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0x3A000000,
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DEVICE_MEM},
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{FT_PCI_CONFIG_BASEADDR,
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FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
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FT_PCI_CONFIG_BASEADDR,
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DEVICE_MEM},
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{FT_PCI_IO_CONFIG_BASEADDR,
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FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
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FT_PCI_IO_CONFIG_BASEADDR,
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DEVICE_MEM},
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{FT_PCI_MEM32_BASEADDR,
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FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
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FT_PCI_MEM32_BASEADDR,
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DEVICE_MEM},
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};
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const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
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static rt_uint32_t timerStep;
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void rt_hw_timer_isr(int vector, void *parameter)
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{
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gtimer_set_load_value(timerStep);
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rt_tick_increase();
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}
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int rt_hw_timer_init(void)
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{
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rt_hw_interrupt_install(30, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(30);
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timerStep = gtimer_get_counter_frequency();
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timerStep /= RT_TICK_PER_SECOND;
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gtimer_set_load_value(timerStep);
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gtimer_set_control(1);
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_timer_init);
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static void AssertCallback(const char *File, s32 Line)
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{
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Ft_printf("Assert Error is %s : %d \r\n", File, Line);
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}
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#ifdef RT_USING_SMP
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void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
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#endif
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/**
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* This function will initialize hardware board
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*/
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void rt_hw_board_init(void)
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{
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/* bsp debug */
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FCpu_SpinLockInit();
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Ft_GenericTimer_Init(0, RT_NULL);
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Ft_vsprintfRegister((vsprintf_p)rt_vsprintf);
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Ft_assertSetCallBack((Ft_assertCallback)AssertCallback);
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/* interrupt init */
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arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 0, 0);
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#if RT_CPUS_NR == 2
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Ft_printf("arm_gic_redist_address_set is 2 \r\n");
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arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + (2U << 16), 1);
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#elif RT_CPUS_NR == 3
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arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + (2U << 16), 1);
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arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 2 * (2U << 16), 2);
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#elif RT_CPUS_NR == 4
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arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + (2U << 16), 1);
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arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 2 * (2U << 16), 2);
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arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 3 * (2U << 16), 3);
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#endif
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rt_hw_interrupt_init();
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rt_components_board_init();
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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/* 初始化内存池 */
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#ifdef RT_USING_HEAP
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rt_system_heap_init(HEAP_BEGIN, HEAP_END);
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#endif
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#ifdef RT_USING_SMP
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/* install IPI handle */
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rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
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rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
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rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
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#endif
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}
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static void ft_reset(void)
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{
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FPsci_Reset();
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}
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MSH_CMD_EXPORT_ALIAS(ft_reset, ft_reset, ft_reset);
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/*@}*/
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