53 lines
1.1 KiB
C
53 lines
1.1 KiB
C
/*
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* Copyright (c) 2019-2020, Xim
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#ifndef ARCH_IO_H
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#define ARCH_IO_H
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#include <rtthread.h>
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#define RISCV_FENCE(p, s) \
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__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
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/* These barriers need to enforce ordering on both devices or memory. */
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#define mb() RISCV_FENCE(iorw,iorw)
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#define rmb() RISCV_FENCE(ir,ir)
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#define wmb() RISCV_FENCE(ow,ow)
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#define __arch_getl(a) (*(unsigned int *)(a))
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#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
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#define dmb() mb()
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#define __iormb() rmb()
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#define __iowmb() wmb()
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static inline void writel(uint32_t val, volatile void *addr)
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{
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__iowmb();
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__arch_putl(val, addr);
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}
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static inline uint32_t readl(const volatile void *addr)
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{
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uint32_t val;
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val = __arch_getl(addr);
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__iormb();
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return val;
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}
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static inline void write_reg(
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uint32_t val, volatile void *addr, unsigned offset)
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{
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writel(val, addr + offset);
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}
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static inline uint32_t read_reg(
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const volatile void *addr, unsigned offset)
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{
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return readl(addr + offset);
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}
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#endif // ARCH_IO_H
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