/*=============================================================*/
/* Created by Microsemi SmartDesign Fri May 22 15:04:18 2020   */
/*                                                             */
/* Warning: Do not modify this file, it may lead to unexpected */
/*          functional failures in your design.                */
/*                                                             */
/*=============================================================*/

#ifndef SYS_CONFIG_MSS_CLOCKS
#define SYS_CONFIG_MSS_CLOCKS

#define MSS_SYS_M3_CLK_FREQ             100000000u
#define MSS_SYS_MDDR_CLK_FREQ           100000000u
#define MSS_SYS_APB_0_CLK_FREQ          100000000u
#define MSS_SYS_APB_1_CLK_FREQ          100000000u
#define MSS_SYS_APB_2_CLK_FREQ          25000000u
#define MSS_SYS_FIC_0_CLK_FREQ          100000000u
#define MSS_SYS_FIC_1_CLK_FREQ          100000000u
#define MSS_SYS_FIC64_CLK_FREQ          100000000u

#endif /* SYS_CONFIG_MSS_CLOCKS */