/** @file reg_rti.h * @brief RTI Register Layer Header File * @date 23.May.2013 * @version 03.05.01 * * This file contains: * - Definitions * - Types * - Interface Prototypes * . * which are relevant for the RTI driver. */ /* (c) Texas Instruments 2009-2013, All rights reserved. */ #ifndef __REG_RTI_H__ #define __REG_RTI_H__ #include "sys_common.h" /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Rti Register Frame Definition */ /** @struct rtiBase * @brief RTI Register Frame Definition * * This type is used to access the RTI Registers. */ /** @typedef rtiBASE_t * @brief RTI Register Frame Type Definition * * This type is used to access the RTI Registers. */ typedef volatile struct rtiBase { uint32 GCTRL; /**< 0x0000: Global Control Register */ uint32 TBCTRL; /**< 0x0004: Timebase Control Register */ uint32 CAPCTRL; /**< 0x0008: Capture Control Register */ uint32 COMPCTRL; /**< 0x000C: Compare Control Register */ struct { uint32 FRCx; /**< 0x0010,0x0030: Free Running Counter x Register */ uint32 UCx; /**< 0x0014,0x0034: Up Counter x Register */ uint32 CPUCx; /**< 0x0018,0x0038: Compare Up Counter x Register */ uint32 rsvd1; /**< 0x001C,0x003C: Reserved */ uint32 CAFRCx; /**< 0x0020,0x0040: Capture Free Running Counter x Register */ uint32 CAUCx; /**< 0x0024,0x0044: Capture Up Counter x Register */ uint32 rsvd2[2U]; /**< 0x0028,0x0048: Reserved */ } CNT[2U]; /**< Counter x selection: - 0: Counter 0 - 1: Counter 1 */ struct { uint32 COMPx; /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register */ uint32 UDCPx; /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */ } CMP[4U]; /**< Compare x selection: - 0: Compare 0 - 1: Compare 1 - 2: Compare 2 - 3: Compare 3 */ uint32 TBLCOMP; /**< 0x0070: External Clock Timebase Low Compare Register */ uint32 TBHCOMP; /**< 0x0074: External Clock Timebase High Compare Register */ uint32 rsvd3[2U]; /**< 0x0078: Reserved */ uint32 SETINT; /**< 0x0080: Set/Status Interrupt Register */ uint32 CLEARINT; /**< 0x0084: Clear/Status Interrupt Register */ uint32 INTFLAG; /**< 0x0088: Interrupt Flag Register */ uint32 rsvd4; /**< 0x008C: Reserved */ uint32 DWDCTRL; /**< 0x0090: Digital Watchdog Control Register */ uint32 DWDPRLD; /**< 0x0094: Digital Watchdog Preload Register */ uint32 WDSTATUS; /**< 0x0098: Watchdog Status Register */ uint32 WDKEY; /**< 0x009C: Watchdog Key Register */ uint32 DWDCNTR; /**< 0x00A0: Digital Watchdog Down Counter */ uint32 WWDRXNCTRL; /**< 0x00A4: Digital Windowed Watchdog Reaction Control */ uint32 WWDSIZECTRL; /**< 0x00A8: Digital Windowed Watchdog Window Size Control */ uint32 INTCLRENABLE; /**< 0x00AC: RTI Compare Interrupt Clear Enable Register */ uint32 COMP0CLR; /**< 0x00B0: RTI Compare 0 Clear Register */ uint32 COMP1CLR; /**< 0x00B4: RTI Compare 1 Clear Register */ uint32 COMP2CLR; /**< 0x00B8: RTI Compare 2 Clear Register */ uint32 COMP3CLR; /**< 0x00BC: RTI Compare 3 Clear Register */ } rtiBASE_t; /** @def rtiREG1 * @brief RTI1 Register Frame Pointer * * This pointer is used by the RTI driver to access the RTI1 registers. */ #define rtiREG1 ((rtiBASE_t *)0xFFFFFC00U) /* USER CODE BEGIN (1) */ /* USER CODE END */ #endif