/* ** ################################################################### ** Processor: PK40X256VLQ100 ** Compilers: ARM Compiler ** Freescale C/C++ for Embedded ARM ** GNU ARM C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Reference manual: K40P144M100SF2RM, Rev. 3, 4 Nov 2010 ** Version: rev. 1.6, 2011-01-14 ** ** Abstract: ** CMSIS Peripheral Access Layer for MK40N512MD100 ** ** Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http: www.freescale.com ** mail: support@freescale.com ** ** Revisions: ** - rev. 0.1 (2010-09-29) ** Initial version ** - rev. 1.0 (2010-10-15) ** First public version ** - rev. 1.1 (2010-10-27) ** Registers updated according to the new reference manual revision - Rev. 2, 15 Oct 2010 ** ADC - Peripheral register PGA bit definition has been fixed, bits PGALP, PGACHP removed. ** CAN - Peripheral register MCR bit definition has been fixed, bit WAKSRC removed. ** CRC - Peripheral register layout structure has been extended with 8/16-bit access to shadow registers. ** CMP - Peripheral base address macro renamed from HSCMPx_BASE to CMPx_BASE. ** CMP - Peripheral base pointer macro renamed from HSCMPx to CMPx. ** DMA - Peripheral base address macro renamed from eDMA_BASE to DMA_BASE. ** DMA - Peripheral base pointer macro renamed from eDMA to DMA. ** GPIO - Port Output Enable Register (POER) has been renamed to Port Data Direction Register (PDDR), all POER related macros fixed to PDDR. ** LCD - Peripheral base address macro renamed from SLCD_BASE to LCD_BASE. ** LCD - Peripheral base pointer macro renamed from SLCD to LCD. ** PDB - Peripheral register layout structure has been extended for Channel n and DAC n register array access (#MTWX44115). ** RFSYS - System regfile registers have been added (#MTWX43999) ** RFVBAT - VBAT regfile registers have been added (#MTWX43999) ** RTC - Peripheral register CR bit definition has been fixed, bit OTE removed. ** TSI - Peripheral registers STATUS, SCANC bit definition have been fixed, bit groups CAPTRM, DELVOL and AMCLKDIV added. ** USB - Peripheral base address macro renamed from USBOTG0_BASE to USB0_BASE. ** USB - Peripheral base pointer macro renamed from USBOTG0 to USB0. ** VREF - Peripheral register TRM removed. ** - rev. 1.2 (2010-11-11) ** Registers updated according to the new reference manual revision - Rev. 3, 4 Nov 2010 ** CAN - Individual Matching Element Update (IMEU) feature has been removed. ** CAN - Peripheral register layout structure has been fixed, registers IMEUR, LRFR have been removed. ** CAN - Peripheral register CTRL2 bit definition has been fixed, bits IMEUMASK, LOSTRMMSK, LOSTRLMSK, IMEUEN have been removed. ** CAN - Peripheral register ESR2 bit definition has been fixed, bits IMEUF, LOSTRMF, LOSTRLF have been removed. ** NV - Fixed offset address of BACKKEYx, FPROTx registers. ** TSI - Peripheral register layout structure has been fixed, register WUCNTR has been removed. ** - rev. 1.3 (2010-11-19) ** CAN - Support for CAN0_IMEU_IRQn, CAN0_Lost_Rx_IRQn interrupts has been removed. ** CAN - Support for CAN1_IMEU_IRQn, CAN1_Lost_Rx_IRQn interrupts has been removed. ** - rev. 1.4 (2010-11-30) ** EWM - Peripheral base address EWM_BASE definition has been fixed from 0x4005F000u to 0x40061000u (#MTWX44776). ** - rev. 1.5 (2010-12-17) ** AIPS0, AIPS1 - Fixed offset of PACRE-PACRP registers (#MTWX45259). ** - rev. 1.6 (2011-01-14) ** Added BITBAND_REG() macro to provide access to register bits using bit band region. ** ** ################################################################### */ /*! \file PK40X256VLQ100.h */ /*! \version 1.6 */ /*! \date 2011-01-14 */ /*! \brief CMSIS Peripheral Access Layer for PK40X256VLQ100 */ /*! \detailed CMSIS Peripheral Access Layer for PK40X256VLQ100 */ #if !defined(PK40X256VLQ100) #define PK40X256VLQ100_H_ /*!< Symbol preventing repeated inclusion */ /*! Memory map version 1.6 */ #define MCU_MEM_MAP_VERSION 0x0106u /*! * \def BITBAND_REG(reg,bit) * \brief Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access. * \param Reg Register to access * \param Bit Bit number to access * \return Value of the targeted bit in the bit band region. */ #define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! \addtogroup Interrupt_vector_numbers Interrupt vector numbers */ /*! \{ */ /*! Interrupt Number Definitions */ typedef enum IRQn { /* Core interrupts */ NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ DMA0_IRQn = 0, /*!< DMA Channel 0 Transfer Complete */ DMA1_IRQn = 1, /*!< DMA Channel 1 Transfer Complete */ DMA2_IRQn = 2, /*!< DMA Channel 2 Transfer Complete */ DMA3_IRQn = 3, /*!< DMA Channel 3 Transfer Complete */ DMA4_IRQn = 4, /*!< DMA Channel 4 Transfer Complete */ DMA5_IRQn = 5, /*!< DMA Channel 5 Transfer Complete */ DMA6_IRQn = 6, /*!< DMA Channel 6 Transfer Complete */ DMA7_IRQn = 7, /*!< DMA Channel 7 Transfer Complete */ DMA8_IRQn = 8, /*!< DMA Channel 8 Transfer Complete */ DMA9_IRQn = 9, /*!< DMA Channel 9 Transfer Complete */ DMA10_IRQn = 10, /*!< DMA Channel 10 Transfer Complete */ DMA11_IRQn = 11, /*!< DMA Channel 11 Transfer Complete */ DMA12_IRQn = 12, /*!< DMA Channel 12 Transfer Complete */ DMA13_IRQn = 13, /*!< DMA Channel 13 Transfer Complete */ DMA14_IRQn = 14, /*!< DMA Channel 14 Transfer Complete */ DMA15_IRQn = 15, /*!< DMA Channel 15 Transfer Complete */ DMA_Error_IRQn = 16, /*!< DMA Error Interrupt */ MCM_IRQn = 17, /*!< Normal Interrupt */ FTFL_IRQn = 18, /*!< FTFL Interrupt */ Read_Collision_IRQn = 19, /*!< Read Collision Interrupt */ LVD_LVW_IRQn = 20, /*!< Low Voltage Detect, Low Voltage Warning */ LLW_IRQn = 21, /*!< Low Leakage Wakeup */ Watchdog_IRQn = 22, /*!< WDOG Interrupt */ Reserved39_IRQn = 23, /*!< Reserved interrupt 39 */ I2C0_IRQn = 24, /*!< I2C0 interrupt */ I2C1_IRQn = 25, /*!< I2C1 interrupt */ SPI0_IRQn = 26, /*!< SPI0 Interrupt */ SPI1_IRQn = 27, /*!< SPI1 Interrupt */ SPI2_IRQn = 28, /*!< SPI2 Interrupt */ CAN0_ORed_Message_buffer_IRQn = 29, /*!< CAN0 OR'd Message Buffers Interrupt */ CAN0_Bus_Off_IRQn = 30, /*!< CAN0 Bus Off Interrupt */ CAN0_Error_IRQn = 31, /*!< CAN0 Error Interrupt */ CAN0_Tx_Warning_IRQn = 32, /*!< CAN0 Tx Warning Interrupt */ CAN0_Rx_Warning_IRQn = 33, /*!< CAN0 Rx Warning Interrupt */ CAN0_Wake_Up_IRQn = 34, /*!< CAN0 Wake Up Interrupt */ Reserved51_IRQn = 35, /*!< Reserved interrupt 51 */ Reserved52_IRQn = 36, /*!< Reserved interrupt 52 */ CAN1_ORed_Message_buffer_IRQn = 37, /*!< CAN1 OR'd Message Buffers Interrupt */ CAN1_Bus_Off_IRQn = 38, /*!< CAN1 Bus Off Interrupt */ CAN1_Error_IRQn = 39, /*!< CAN1 Error Interrupt */ CAN1_Tx_Warning_IRQn = 40, /*!< CAN1 Tx Warning Interrupt */ CAN1_Rx_Warning_IRQn = 41, /*!< CAN1 Rx Warning Interrupt */ CAN1_Wake_Up_IRQn = 42, /*!< CAN1 Wake Up Interrupt */ Reserved59_IRQn = 43, /*!< Reserved interrupt 59 */ Reserved60_IRQn = 44, /*!< Reserved interrupt 60 */ UART0_RX_TX_IRQn = 45, /*!< UART0 Receive/Transmit interrupt */ UART0_ERR_IRQn = 46, /*!< UART0 Error interrupt */ UART1_RX_TX_IRQn = 47, /*!< UART1 Receive/Transmit interrupt */ UART1_ERR_IRQn = 48, /*!< UART1 Error interrupt */ UART2_RX_TX_IRQn = 49, /*!< UART2 Receive/Transmit interrupt */ UART2_ERR_IRQn = 50, /*!< UART2 Error interrupt */ UART3_RX_TX_IRQn = 51, /*!< UART3 Receive/Transmit interrupt */ UART3_ERR_IRQn = 52, /*!< UART3 Error interrupt */ UART4_RX_TX_IRQn = 53, /*!< UART4 Receive/Transmit interrupt */ UART4_ERR_IRQn = 54, /*!< UART4 Error interrupt */ UART5_RX_TX_IRQn = 55, /*!< UART5 Receive/Transmit interrupt */ UART5_ERR_IRQn = 56, /*!< UART5 Error interrupt */ ADC0_IRQn = 57, /*!< ADC0 interrupt */ ADC1_IRQn = 58, /*!< ADC1 interrupt */ CMP0_IRQn = 59, /*!< CMP0 interrupt */ CMP1_IRQn = 60, /*!< CMP1 interrupt */ CMP2_IRQn = 61, /*!< CMP2 interrupt */ FTM0_IRQn = 62, /*!< FTM0 fault, overflow and channels interrupt */ FTM1_IRQn = 63, /*!< FTM1 fault, overflow and channels interrupt */ FTM2_IRQn = 64, /*!< FTM2 fault, overflow and channels interrupt */ CMT_IRQn = 65, /*!< CMT interrupt */ RTC_IRQn = 66, /*!< RTC interrupt */ Reserved83_IRQn = 67, /*!< Reserved interrupt 83 */ PIT0_IRQn = 68, /*!< PIT timer channel 0 interrupt */ PIT1_IRQn = 69, /*!< PIT timer channel 1 interrupt */ PIT2_IRQn = 70, /*!< PIT timer channel 2 interrupt */ PIT3_IRQn = 71, /*!< PIT timer channel 3 interrupt */ PDB0_IRQn = 72, /*!< PDB0 Interrupt */ USB0_IRQn = 73, /*!< USB0 interrupt */ USBDCD_IRQn = 74, /*!< USBDCD Interrupt */ Reserved91_IRQn = 75, /*!< Reserved interrupt 91 */ Reserved92_IRQn = 76, /*!< Reserved interrupt 92 */ Reserved93_IRQn = 77, /*!< Reserved interrupt 93 */ Reserved94_IRQn = 78, /*!< Reserved interrupt 94 */ I2S0_IRQn = 79, /*!< I2S0 Interrupt */ SDHC_IRQn = 80, /*!< SDHC Interrupt */ DAC0_IRQn = 81, /*!< DAC0 interrupt */ DAC1_IRQn = 82, /*!< DAC1 interrupt */ TSI0_IRQn = 83, /*!< TSI0 Interrupt */ MCG_IRQn = 84, /*!< MCG Interrupt */ LPTimer_IRQn = 85, /*!< LPTimer interrupt */ LCD_IRQn = 86, /*!< Segment LCD Interrupt */ PORTA_IRQn = 87, /*!< Port A interrupt */ PORTB_IRQn = 88, /*!< Port B interrupt */ PORTC_IRQn = 89, /*!< Port C interrupt */ PORTD_IRQn = 90, /*!< Port D interrupt */ PORTE_IRQn = 91, /*!< Port E interrupt */ Reserved108_IRQn = 92, /*!< Reserved interrupt 108 */ Reserved109_IRQn = 93, /*!< Reserved interrupt 109 */ Reserved110_IRQn = 94, /*!< Reserved interrupt 110 */ Reserved111_IRQn = 95, /*!< Reserved interrupt 111 */ Reserved112_IRQn = 96, /*!< Reserved interrupt 112 */ Reserved113_IRQn = 97, /*!< Reserved interrupt 113 */ Reserved114_IRQn = 98, /*!< Reserved interrupt 114 */ Reserved115_IRQn = 99, /*!< Reserved interrupt 115 */ Reserved116_IRQn = 100, /*!< Reserved interrupt 116 */ Reserved117_IRQn = 101, /*!< Reserved interrupt 117 */ Reserved118_IRQn = 102, /*!< Reserved interrupt 118 */ Reserved119_IRQn = 103 /*!< Reserved interrupt 119 */ } IRQn_Type; /*! \} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Cortex M4 Core Configuration ---------------------------------------------------------------------------- */ /*! \addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration */ /*! \{ */ #define __MPU_PRESENT 0 /*!< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 4 /*!< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /*!< Vendor specific implementation of SysTickConfig is defined */ #include "core_cm4.h" /* Core Peripheral Access Layer */ #include "system_PK40X256VLQ100.h" /* Device specific configuration file */ /*! \} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! \addtogroup Peripheral_access_layer Device Peripheral Access Layer */ /*! \{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #pragma push #pragma anon_unions #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! \addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer */ /*! \{ */ /*! ADC - Register Layout Typedef */ typedef struct { __IO uint32_t SC1[2]; /*!< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ __IO uint32_t CFG1; /*!< ADC configuration register 1, offset: 0x8 */ __IO uint32_t CFG2; /*!< Configuration register 2, offset: 0xC */ __I uint32_t R[2]; /*!< ADC data result register, array offset: 0x10, array step: 0x4 */ __IO uint32_t CV1; /*!< Compare value registers, offset: 0x18 */ __IO uint32_t CV2; /*!< Compare value registers, offset: 0x1C */ __IO uint32_t SC2; /*!< Status and control register 2, offset: 0x20 */ __IO uint32_t SC3; /*!< Status and control register 3, offset: 0x24 */ __IO uint32_t OFS; /*!< ADC offset correction register, offset: 0x28 */ __IO uint32_t PG; /*!< ADC plus-side gain register, offset: 0x2C */ __IO uint32_t MG; /*!< ADC minus-side gain register, offset: 0x30 */ __IO uint32_t CLPD; /*!< ADC plus-side general calibration value register, offset: 0x34 */ __IO uint32_t CLPS; /*!< ADC plus-side general calibration value register, offset: 0x38 */ __IO uint32_t CLP4; /*!< ADC plus-side general calibration value register, offset: 0x3C */ __IO uint32_t CLP3; /*!< ADC plus-side general calibration value register, offset: 0x40 */ __IO uint32_t CLP2; /*!< ADC plus-side general calibration value register, offset: 0x44 */ __IO uint32_t CLP1; /*!< ADC plus-side general calibration value register, offset: 0x48 */ __IO uint32_t CLP0; /*!< ADC plus-side general calibration value register, offset: 0x4C */ __IO uint32_t PGA; /*!< ADC PGA register, offset: 0x50 */ __IO uint32_t CLMD; /*!< ADC minus-side general calibration value register, offset: 0x54 */ __IO uint32_t CLMS; /*!< ADC minus-side general calibration value register, offset: 0x58 */ __IO uint32_t CLM4; /*!< ADC minus-side general calibration value register, offset: 0x5C */ __IO uint32_t CLM3; /*!< ADC minus-side general calibration value register, offset: 0x60 */ __IO uint32_t CLM2; /*!< ADC minus-side general calibration value register, offset: 0x64 */ __IO uint32_t CLM1; /*!< ADC minus-side general calibration value register, offset: 0x68 */ __IO uint32_t CLM0; /*!< ADC minus-side general calibration value register, offset: 0x6C */ } ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! \addtogroup ADC_Register_Masks ADC Register Masks */ /*! \{ */ /* SC1 Bit Fields */ #define ADC_SC1_ADCH_MASK 0x1Fu #define ADC_SC1_ADCH_SHIFT 0 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<