/* * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-11-27 zylx first version * 2019-04-11 ZYH port from stm32f7serial */ #include #include #include #include #include #ifdef BSP_USING_QSPI_FLASH #include "spi_flash.h" #include "spi_flash_sfud.h" char n25qxxa_read_status_register2(struct rt_qspi_device *device) { /* 0x35 read status register2 */ char instruction = 0x35, status; rt_qspi_send_then_recv(device, &instruction, 1, &status, 1); return status; } void n25qxxa_write_enable(struct rt_qspi_device *device) { /* 0x06 write enable */ char instruction = 0x06; rt_qspi_send(device, &instruction, 1); } void n25qxxa_enter_qspi_mode(struct rt_qspi_device *device) { char status = 0; /* 0x38 enter qspi mode */ char instruction = 0x38; char write_status2_buf[2] = {0}; /* 0x31 write status register2 */ write_status2_buf[0] = 0x31; status = n25qxxa_read_status_register2(device); if (!(status & 0x02)) { status |= 1 << 1; n25qxxa_write_enable(device); write_status2_buf[1] = status; rt_qspi_send(device, &write_status2_buf, 2); rt_qspi_send(device, &instruction, 1); rt_kprintf("flash already enter qspi mode\n"); rt_thread_mdelay(10); } } static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, n25qxxa_enter_qspi_mode, RT_NULL); /* init n25qxx */ if (RT_NULL == rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi10")) { return -RT_ERROR; } return RT_EOK; } INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_with_sfud_init); #endif/* BSP_USING_QSPI_FLASH */