/* * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2021-09-09 WCH the first version */ #include #include #include "ch32v10x.h" #include "cpuport.h" #ifndef RT_USING_SMP volatile rt_ubase_t rt_interrupt_from_thread = 0; volatile rt_ubase_t rt_interrupt_to_thread = 0; volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0; #endif struct rt_hw_stack_frame { rt_ubase_t epc; /* epc - epc - program counter */ rt_ubase_t ra; /* x1 - ra - return address for jumps */ rt_ubase_t mstatus; /* - machine status register */ rt_ubase_t gp; /* x3 - gp - global pointer */ rt_ubase_t tp; /* x4 - tp - thread pointer */ rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ rt_ubase_t t2; /* x7 - t2 - temporary register 2 */ rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ rt_ubase_t s1; /* x9 - s1 - saved register 1 */ rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */ rt_ubase_t a2; /* x12 - a2 - function argument 2 */ rt_ubase_t a3; /* x13 - a3 - function argument 3 */ rt_ubase_t a4; /* x14 - a4 - function argument 4 */ rt_ubase_t a5; /* x15 - a5 - function argument 5 */ rt_ubase_t a6; /* x16 - a6 - function argument 6 */ rt_ubase_t a7; /* x17 - s7 - function argument 7 */ rt_ubase_t s2; /* x18 - s2 - saved register 2 */ rt_ubase_t s3; /* x19 - s3 - saved register 3 */ rt_ubase_t s4; /* x20 - s4 - saved register 4 */ rt_ubase_t s5; /* x21 - s5 - saved register 5 */ rt_ubase_t s6; /* x22 - s6 - saved register 6 */ rt_ubase_t s7; /* x23 - s7 - saved register 7 */ rt_ubase_t s8; /* x24 - s8 - saved register 8 */ rt_ubase_t s9; /* x25 - s9 - saved register 9 */ rt_ubase_t s10; /* x26 - s10 - saved register 10 */ rt_ubase_t s11; /* x27 - s11 - saved register 11 */ rt_ubase_t t3; /* x28 - t3 - temporary register 3 */ rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ /* float register */ #ifdef ARCH_RISCV_FPU rv_floatreg_t f0; /* f0 */ rv_floatreg_t f1; /* f1 */ rv_floatreg_t f2; /* f2 */ rv_floatreg_t f3; /* f3 */ rv_floatreg_t f4; /* f4 */ rv_floatreg_t f5; /* f5 */ rv_floatreg_t f6; /* f6 */ rv_floatreg_t f7; /* f7 */ rv_floatreg_t f8; /* f8 */ rv_floatreg_t f9; /* f9 */ rv_floatreg_t f10; /* f10 */ rv_floatreg_t f11; /* f11 */ rv_floatreg_t f12; /* f12 */ rv_floatreg_t f13; /* f13 */ rv_floatreg_t f14; /* f14 */ rv_floatreg_t f15; /* f15 */ rv_floatreg_t f16; /* f16 */ rv_floatreg_t f17; /* f17 */ rv_floatreg_t f18; /* f18 */ rv_floatreg_t f19; /* f19 */ rv_floatreg_t f20; /* f20 */ rv_floatreg_t f21; /* f21 */ rv_floatreg_t f22; /* f22 */ rv_floatreg_t f23; /* f23 */ rv_floatreg_t f24; /* f24 */ rv_floatreg_t f25; /* f25 */ rv_floatreg_t f26; /* f26 */ rv_floatreg_t f27; /* f27 */ rv_floatreg_t f28; /* f28 */ rv_floatreg_t f29; /* f29 */ rv_floatreg_t f30; /* f30 */ rv_floatreg_t f31; /* f31 */ #endif }; /* * This function will initialize thread stack * * @param tentry the entry of thread * @param parameter the parameter of entry * @param stack_addr the beginning stack address * @param texit the function will be called when thread exit * * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { struct rt_hw_stack_frame *frame; rt_uint8_t *stk; int i; stk = stack_addr + sizeof(rt_ubase_t); stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); stk -= sizeof(struct rt_hw_stack_frame); frame = (struct rt_hw_stack_frame *)stk; for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) { ((rt_ubase_t *)frame)[i] = 0xdeadbeef; } frame->ra = (rt_ubase_t)texit; frame->a0 = (rt_ubase_t)parameter; frame->epc = (rt_ubase_t)tentry; /* force to machine mode(MPP=11) and set MPIE to 1 and FS=11 */ frame->mstatus = 0x00001880; return stk; } /* * trigger soft interrupt */ void sw_setpend(void) { NVIC_SetPendingIRQ(Software_IRQn); } /* * clear soft interrupt */ void sw_clearpend(void) { NVIC_ClearPendingIRQ(Software_IRQn); } /* * disable interrupt and save mstatus */ rt_base_t rt_hw_interrupt_disable(void) { register rt_base_t value = 0; asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800)); return value; } /* * enable interrupt and resume mstatus */ void rt_hw_interrupt_enable(rt_base_t level) { asm("csrw mstatus, %0": :"r"(level)); } /* * #ifdef RT_USING_SMP * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); * #else * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); * #endif */ void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) { if (rt_thread_switch_interrupt_flag == 0) rt_interrupt_from_thread = from; rt_interrupt_to_thread = to; rt_thread_switch_interrupt_flag = 1; /* switch just in sw_handler */ sw_setpend(); } /* shutdown CPU */ void rt_hw_cpu_shutdown(void) { rt_base_t level; rt_kprintf("shutdown...\n"); level = rt_hw_interrupt_disable(); while (level) { RT_ASSERT(0); } }