/* * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017-10-20 ZYH the first version * 2018-04-23 misonyo port to gd32f30x * 2019-03-31 xuzhuoyi Porting for gd32e230 */ #include "drv_gpio.h" #include #include #include "gd32e230.h" #include "gd32e230_exti.h" #ifdef RT_USING_PIN #define __GD32_PIN(index, port, pin) {index, RCU_GPIO##port, GPIO##port, \ GPIO_PIN_##pin, EXTI_SOURCE_GPIO##port, EXTI_SOURCE_PIN##pin} #define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} /* GD32 GPIO driver */ struct pin_index { rt_int16_t index; rcu_periph_enum clk; rt_uint32_t gpio_periph; rt_uint32_t pin; rt_uint32_t port_src; rt_uint32_t pin_src; }; static const struct pin_index pins[] = { __GD32_PIN_DEFAULT, __GD32_PIN(2, F, 0), __GD32_PIN(3, F, 1), __GD32_PIN_DEFAULT, __GD32_PIN_DEFAULT, __GD32_PIN(6, A, 0), __GD32_PIN(7, A, 1), __GD32_PIN(8, A, 2), __GD32_PIN(9, A, 3), __GD32_PIN(10, A, 4), __GD32_PIN(11, A, 5), __GD32_PIN(12, A, 6), __GD32_PIN(13, A, 7), __GD32_PIN(14, B, 0), __GD32_PIN(15, B, 1), __GD32_PIN(16, B, 2), __GD32_PIN_DEFAULT, __GD32_PIN(18, A, 8), __GD32_PIN(19, A, 9), __GD32_PIN(20, A, 10), __GD32_PIN(21, A, 11), __GD32_PIN(22, A, 12), __GD32_PIN(23, A, 13), __GD32_PIN(24, A, 14), __GD32_PIN(25, A, 15), __GD32_PIN(26, B, 3), __GD32_PIN(27, B, 4), __GD32_PIN(28, B, 5), __GD32_PIN(29, B, 6), __GD32_PIN(30, B, 7), __GD32_PIN_DEFAULT, __GD32_PIN(32, B, 8), }; struct pin_irq_map { rt_uint16_t pinbit; IRQn_Type irqno; }; static const struct pin_irq_map pin_irq_map[] = { {GPIO_PIN_0, EXTI0_1_IRQn}, {GPIO_PIN_1, EXTI0_1_IRQn}, {GPIO_PIN_2, EXTI2_3_IRQn}, {GPIO_PIN_3, EXTI2_3_IRQn}, {GPIO_PIN_4, EXTI4_15_IRQn}, {GPIO_PIN_5, EXTI4_15_IRQn}, {GPIO_PIN_6, EXTI4_15_IRQn}, {GPIO_PIN_7, EXTI4_15_IRQn}, {GPIO_PIN_8, EXTI4_15_IRQn}, {GPIO_PIN_9, EXTI4_15_IRQn}, {GPIO_PIN_10, EXTI4_15_IRQn}, {GPIO_PIN_11, EXTI4_15_IRQn}, {GPIO_PIN_12, EXTI4_15_IRQn}, {GPIO_PIN_13, EXTI4_15_IRQn}, {GPIO_PIN_14, EXTI4_15_IRQn}, {GPIO_PIN_15, EXTI4_15_IRQn}, }; struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, }; #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) const struct pin_index *get_pin(rt_uint8_t pin) { const struct pin_index *index; if (pin < ITEM_NUM(pins)) { index = &pins[pin]; if (index->index == -1) index = RT_NULL; } else { index = RT_NULL; } return index; }; void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { const struct pin_index *index; rt_uint32_t pin_mode; rt_uint32_t otype; rt_uint32_t pull_up_down; index = get_pin(pin); if (index == RT_NULL) { return; } /* GPIO Periph clock enable */ rcu_periph_clock_enable(index->clk); pin_mode = GPIO_MODE_OUTPUT; otype = GPIO_OTYPE_PP; pull_up_down = GPIO_PUPD_NONE; switch(mode) { case PIN_MODE_OUTPUT: /* output setting */ break; case PIN_MODE_OUTPUT_OD: /* output setting: od. */ otype = GPIO_OTYPE_OD; break; case PIN_MODE_INPUT: /* input setting: not pull. */ pin_mode = GPIO_MODE_INPUT; break; case PIN_MODE_INPUT_PULLUP: /* input setting: pull up. */ pin_mode = GPIO_MODE_INPUT; pull_up_down = GPIO_PUPD_PULLUP; break; case PIN_MODE_INPUT_PULLDOWN: /* input setting: pull down. */ pin_mode = GPIO_MODE_INPUT; pull_up_down = GPIO_PUPD_PULLDOWN; break; default: break; } gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin); gpio_output_options_set(index->gpio_periph, otype, GPIO_OSPEED_50MHZ, index->pin); } void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { const struct pin_index *index; index = get_pin(pin); if (index == RT_NULL) { return; } gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); } int gd32_pin_read(rt_device_t dev, rt_base_t pin) { int value; const struct pin_index *index; value = PIN_LOW; index = get_pin(pin); if (index == RT_NULL) { return value; } value = gpio_input_bit_get(index->gpio_periph, index->pin); return value; } rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) { rt_uint8_t i; for (i = 0; i < 32; i++) { if ((0x01 << i) == bit) { return i; } } return -1; } rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) { rt_int32_t mapindex = bit2bitno(pinbit); if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) { return RT_NULL; } return &pin_irq_map[mapindex]; }; rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) { const struct pin_index *index; rt_base_t level; rt_int32_t hdr_index = -1; index = get_pin(pin); if (index == RT_NULL) { return -RT_EINVAL; } hdr_index = bit2bitno(index->pin); if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) { return -RT_EINVAL; } level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[hdr_index].pin == pin && pin_irq_hdr_tab[hdr_index].hdr == hdr && pin_irq_hdr_tab[hdr_index].mode == mode && pin_irq_hdr_tab[hdr_index].args == args) { rt_hw_interrupt_enable(level); return RT_EOK; } if (pin_irq_hdr_tab[hdr_index].pin != -1) { rt_hw_interrupt_enable(level); return -RT_EFULL; } pin_irq_hdr_tab[hdr_index].pin = pin; pin_irq_hdr_tab[hdr_index].hdr = hdr; pin_irq_hdr_tab[hdr_index].mode = mode; pin_irq_hdr_tab[hdr_index].args = args; rt_hw_interrupt_enable(level); return RT_EOK; } rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) { const struct pin_index *index; rt_base_t level; rt_int32_t hdr_index = -1; index = get_pin(pin); if (index == RT_NULL) { return -RT_EINVAL; } hdr_index = bit2bitno(index->pin); if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) { return -RT_EINVAL; } level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[hdr_index].pin == -1) { rt_hw_interrupt_enable(level); return RT_EOK; } pin_irq_hdr_tab[hdr_index].pin = -1; pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; pin_irq_hdr_tab[hdr_index].mode = 0; pin_irq_hdr_tab[hdr_index].args = RT_NULL; rt_hw_interrupt_enable(level); return RT_EOK; } rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) { const struct pin_index *index; const struct pin_irq_map *irqmap; rt_base_t level; rt_int32_t hdr_index = -1; exti_trig_type_enum trigger_mode; index = get_pin(pin); if (index == RT_NULL) { return -RT_EINVAL; } if (enabled == PIN_IRQ_ENABLE) { hdr_index = bit2bitno(index->pin); if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) { return -RT_EINVAL; } level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[hdr_index].pin == -1) { rt_hw_interrupt_enable(level); return -RT_EINVAL; } irqmap = &pin_irq_map[hdr_index]; switch (pin_irq_hdr_tab[hdr_index].mode) { case PIN_IRQ_MODE_RISING: trigger_mode = EXTI_TRIG_RISING; break; case PIN_IRQ_MODE_FALLING: trigger_mode = EXTI_TRIG_FALLING; break; case PIN_IRQ_MODE_RISING_FALLING: trigger_mode = EXTI_TRIG_BOTH; break; default: rt_hw_interrupt_enable(level); return -RT_EINVAL; } //rcu_periph_clock_enable(RCU_AF); /* enable and set interrupt priority */ nvic_irq_enable(irqmap->irqno, 5U); /* connect EXTI line to GPIO pin */ syscfg_exti_line_config(index->port_src, index->pin_src); /* configure EXTI line */ exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); exti_interrupt_flag_clear((exti_line_enum)(index->pin)); rt_hw_interrupt_enable(level); } else if (enabled == PIN_IRQ_DISABLE) { irqmap = get_pin_irq_map(index->pin); if (irqmap == RT_NULL) { return -RT_EINVAL; } nvic_irq_disable(irqmap->irqno); } else { return -RT_EINVAL; } return RT_EOK; } const static struct rt_pin_ops _gd32_pin_ops = { gd32_pin_mode, gd32_pin_write, gd32_pin_read, gd32_pin_attach_irq, gd32_pin_detach_irq, gd32_pin_irq_enable, RT_NULL, }; int rt_hw_pin_init(void) { int result; result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); return result; } INIT_BOARD_EXPORT(rt_hw_pin_init); rt_inline void pin_irq_hdr(int irqno) { if (pin_irq_hdr_tab[irqno].hdr) { pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); } } void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) { if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) { pin_irq_hdr(exti_line); exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); } } void EXTI0_IRQHandler(void) { rt_interrupt_enter(); GD32_GPIO_EXTI_IRQHandler(0); rt_interrupt_leave(); } void EXTI1_IRQHandler(void) { rt_interrupt_enter(); GD32_GPIO_EXTI_IRQHandler(1); rt_interrupt_leave(); } void EXTI2_IRQHandler(void) { rt_interrupt_enter(); GD32_GPIO_EXTI_IRQHandler(2); rt_interrupt_leave(); } void EXTI3_IRQHandler(void) { rt_interrupt_enter(); GD32_GPIO_EXTI_IRQHandler(3); rt_interrupt_leave(); } void EXTI4_IRQHandler(void) { rt_interrupt_enter(); GD32_GPIO_EXTI_IRQHandler(4); rt_interrupt_leave(); } void EXTI5_9_IRQHandler(void) { rt_interrupt_enter(); GD32_GPIO_EXTI_IRQHandler(5); GD32_GPIO_EXTI_IRQHandler(6); GD32_GPIO_EXTI_IRQHandler(7); GD32_GPIO_EXTI_IRQHandler(8); GD32_GPIO_EXTI_IRQHandler(9); rt_interrupt_leave(); } void EXTI10_15_IRQHandler(void) { rt_interrupt_enter(); GD32_GPIO_EXTI_IRQHandler(10); GD32_GPIO_EXTI_IRQHandler(11); GD32_GPIO_EXTI_IRQHandler(12); GD32_GPIO_EXTI_IRQHandler(13); GD32_GPIO_EXTI_IRQHandler(14); GD32_GPIO_EXTI_IRQHandler(15); rt_interrupt_leave(); } #endif