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#include "sunxi_timer.h"
#include "platform_timer.h"
#include "aw_common.h"
#include <stdlib.h>
#include <hal_interrupt.h>

static struct sunxi_timer g_timer[SUNXI_TMR_NUM];

static irqreturn_t sunxi_timer_irq_handle(int irq, void *dev)
{
    struct sunxi_timer *timer = (struct sunxi_timer *)dev;

    /* clear pending */
    hal_writel((0x1 << timer->timer_id), (unsigned long)TIMER_IRQ_ST_REG);

    /*callback*/
    if (timer->callback != NULL)
    {
        timer->callback(timer->param);
    }

    return 0;
}

static void sunxi_timer_sync(uint32_t timer)
{
    uint32_t old = hal_readl((unsigned long)TIMER_CNTVAL_REG(timer));

    while ((old - hal_readl((unsigned long)TIMER_CNTVAL_REG(timer))) < TIMER_SYNC_TICKS)
    {
        int i = 10;
        while (i--);
        break;
    }
}

uint32_t sunxi_timer_get_count(uint32_t timer)
{
    return hal_readl((unsigned long)TIMER_CNTVAL_REG(timer));
}

void sunxi_timer_stop(uint32_t timer)
{
    uint32_t val = hal_readl((unsigned long)TIMER_CTL_REG(timer));

    hal_writel(val & ~TIMER_CTL_ENABLE, (unsigned long)TIMER_CTL_REG(timer));

    sunxi_timer_sync(timer);
}

void sunxi_timer_start(uint32_t timer, bool periodic)
{
    uint32_t val = hal_readl((unsigned long)TIMER_CTL_REG(timer));

    if (periodic)
    {
        val &= ~TIMER_CTL_ONESHOT;
    }
    else
    {
        val |= TIMER_CTL_ONESHOT;
    }

    val |= TIMER_CTL_CLK_PRES(0);           //24M
    val &= ~TIMER_CTL_CLK_SRC(0x3);
    val |= TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M);

    hal_writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, (unsigned long)TIMER_CTL_REG(timer));
}

static void sunxi_timer_setup(uint32_t tick, uint32_t timer)
{
    hal_writel(tick, (unsigned long)TIMER_INTVAL_REG(timer));
}

int sunxi_timer_set_oneshot(uint32_t delay_us, uint32_t timer, timer_callback callback, void *callback_param)
{
    uint32_t tick = delay_us * 24;

    if (tick < g_timer[timer].min_delta_ticks || tick > g_timer[timer].max_delta_ticks)
    {
        return -1;
    }

    if (callback != NULL)
    {
        g_timer[timer].callback = callback;
        g_timer[timer].param = callback_param;
    }

    sunxi_timer_stop(timer);

    sunxi_timer_setup(tick, timer);

    sunxi_timer_start(timer, false);

    return 0;
}

int sunxi_timer_set_periodic(uint32_t delay_us, uint32_t timer, timer_callback callback, void *callback_param)
{
    uint32_t tick = delay_us * 24;

    if (tick < g_timer[timer].min_delta_ticks || tick > g_timer[timer].max_delta_ticks)
    {
        return -1;
    }

    if (callback != NULL)
    {
        g_timer[timer].callback = callback;
        g_timer[timer].param = callback_param;
    }

    sunxi_timer_stop(timer);

    sunxi_timer_setup(tick, timer);

    sunxi_timer_start(timer, true);

    return 0;
}

void sunxi_timer_init(hal_timer_id_t id)
{
    uint32_t val;

    /* disable all hrtimer */
    val = hal_readl((unsigned long)TIMER_CTL_REG(id));
    hal_writel(val & ~TIMER_CTL_ENABLE, (unsigned long)TIMER_CTL_REG(id));

    /* clear pending */
    hal_writel((0x1 << id), (unsigned long)TIMER_IRQ_ST_REG);

    g_timer[id].timer_id = id;
    g_timer[id].clk_rate = 24000000;      //ahb1,should get form clk driver
    g_timer[id].irq = SUNXI_IRQ_TMR(id);
    g_timer[id].min_delta_ticks = TIMER_SYNC_TICKS;
    g_timer[id].max_delta_ticks = 0xffffffff;
    g_timer[id].callback = NULL;
    g_timer[id].param = NULL;

    if (request_irq(g_timer[id].irq, sunxi_timer_irq_handle, 0, "timer-ctl", &g_timer[id]) < 0)
    {
    return ;
    }

    /*enable timer irq*/
    val = hal_readl((unsigned long)TIMER_IRQ_EN_REG);
    val |= TIMER_IRQ_EN(id);
    hal_writel(val, (unsigned long)TIMER_IRQ_EN_REG);

    /* enable irq */
    enable_irq(g_timer[id].irq);
}

void sunxi_timer_uninit(hal_timer_id_t id)
{
    disable_irq(g_timer[id].irq);
    free_irq(g_timer[id].irq, &g_timer[id]);
}