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7 Commits

Author SHA1 Message Date
zyh
39558535f2 [Bsp][Tina]Add spi driver 2018-04-20 11:48:04 +08:00
zyh
7cbeb251e4 [Bsp][Tina]Add SDIO Driver 2018-04-20 11:15:07 +08:00
zyh
75194461ea [Bsp][Tina]Add mmc clock and dram gate 2018-04-20 11:04:07 +08:00
tangyuxin
5301a1b9d3 [bsp][allwinner_tina]更改表意不清晰的函数名字 2018-03-08 12:02:25 +08:00
emlslxl
e65729660f fix uart register address structure type 2018-02-27 10:47:49 +08:00
ZYH
ccf15490c9 [Bsp][Tina]Fix uart bug 2018-02-19 15:31:28 +08:00
uestczyh222
9bf2a755e0 [Bsp][New BSP]New bsp for allwinner tina 2018-02-09 15:20:38 +08:00