rt-thread-official

Commit Graph

Author	SHA1	Message	Date
wangqinglin	edaa0d9c8a	更新rk3568 bsp 支持PSCI、amp模式	2023-06-11 21:41:37 -04:00
guo	ecf2d82159	sync branch rt-smart. (#6641 ) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>	2022-12-03 12:07:44 +08:00
GUI	f587a55bc2	[libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568 (#5722 ) * [libcpu/aarch64] add smp support * [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2 * [libcpu/aarch64] disable irq/fiq when switch thread * [libcpu/aarch64] add gtimer frq set and stack align * [libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568	2022-03-29 11:08:25 +08:00

Author

SHA1

Message

Date

wangqinglin

edaa0d9c8a

更新rk3568 bsp 支持PSCI、amp模式

2023-06-11 21:41:37 -04:00

guo

ecf2d82159

sync branch rt-smart. (#6641 )

* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>

2022-12-03 12:07:44 +08:00

GUI

f587a55bc2

[libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568 (#5722 )

* [libcpu/aarch64] add smp support

* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2

* [libcpu/aarch64] disable irq/fiq when switch thread

* [libcpu/aarch64] add gtimer frq set and stack align

* [libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568

2022-03-29 11:08:25 +08:00

3 Commits