5 Commits

Author	SHA1	Message	Date
heyuanjie87	49b6614763	[libcpu]添加对riscv vector的支持 (#9531) ... [libcpu]添加对riscv vector的支持	2024-10-16 14:10:09 +08:00
zhangjing0303	523b123995	[libcpu][risc-v] fix the bug when using ASID in the RV64 MMU ... * (fix) mmu: satp value should be 64-bit Corrected the SATP register to ensure it uses the correct 64-bit format as required by the system architecture. * use __asm__ instead of asm for the GNU C compiler Co-authored-by: Shell <smokewood@qq.com> --------- Co-authored-by: Shell <smokewood@qq.com>	2024-10-11 00:10:46 -04:00
zhangjing0303	65234401f3	[libcpu][risc-v]remove the redundant "0x" from the printed information when cpu is in exception (#9516) ... Remove redundant '0x' from printed output	2024-10-09 15:46:39 +08:00
zhangjing0303	bf8f7b04b5	[libcpu][risc-v]add README for RV64	2024-10-08 17:56:55 -04:00
Shell	57d002b25e	feat: remove redundant codes under virt64, c906 ... Changes: - create new folder name `common64` and save all common codes of rv64 inside Signed-off-by: Shell <smokewood@qq.com>	2024-09-13 17:35:00 -04:00