Commit Graph

5 Commits

Author SHA1 Message Date
zhangjun a5305c05df fix bug in context_gcc.s and start_gcc.s:
save mie into stack
msh  running normaly
2017-07-31 10:59:59 +08:00
zhangjun d9c0bdc70e add plic_driver.c for global interrupt
change interrupt num to 53
change stack size to 512 before system starup
add uart drivers
open msh
remain bug:
   uart just interrupt ones
2017-07-30 22:36:12 +08:00
zhangjun 2d56a27c20 修改: ../../libcpu/risc-v/e310/context_gcc.S
enable interrupt after return form rt_hw_context_switch
2017-07-30 15:34:32 +08:00
zhangjun 98a6896cfa remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();
it will lead to interrupt again in interrupt
2017-07-26 16:07:01 +08:00
zhangjun f147f3398a new bsp for risc-v 2017-07-16 20:37:03 +08:00