9 Commits

Author	SHA1	Message	Date
Shell	71560bafb5	🎯 Sync smart & scheduler codes (#8537) ... Signed-off-by: Shell <smokewood@qq.com> Co-authored-by: xqyjlj <xqyjlj@126.com>	2024-02-23 17:49:15 +08:00
Meco Man	c6a2f5b7bd	rt_hw_cpu_shutdown: implement default weak function ... and remvoe duplicated default functions in each cpu/bsp level	2023-08-08 22:34:25 -04:00
Shell	e991be9c51	[smart][risc-v/libcpu] port rv64 cpu code (#6704) ... * [risc-v/libcpu] porting Smart & RTOS * [fix] rv64 plic * [risc-v/rv64] remove macro in rtdef	2022-12-10 22:16:42 +08:00
guo	ecf2d82159	sync branch rt-smart. (#6641) ... * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>	2022-12-03 12:07:44 +08:00
thewon86	f5b0bfd3f4	uniform code writing-disable interrupt	2022-04-20 14:22:43 +08:00
Bernard Xiong	8da9f78d72	[libc] remove rtlibc	2021-09-11 11:07:51 +08:00
bigmagic123	d6f5fbcd5b	format code	2021-05-21 18:39:41 +08:00
bigmagic	b7c7c7f4de	Support for running with M-Mode	2021-05-21 17:10:07 +08:00
lizhirui	5036816967	add qemu-riscv-virt64 bsp ... add qemu-riscv-virt64 bsp	2021-05-18 09:57:25 +08:00